JP2011035398A - デュアルポートsramセルの構造 - Google Patents
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- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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Abstract
【解決手段】マルチポートSRAMセルと、第1ビット線導体と、第1相補ビット線導体と、第2ビット線導体と、第2相補ビット線導体と、SRAMセルのアクセスポートに接続された第1ワード線と第2ワード線、及びVdd電力供給導体と、4つのVss電力供給導体とを含み、前記ビット線導体と前記電力供給導体は、第1共通金属化層に平行に設置されるメモリデバイス。
【選択図】図3
Description
図16に示されたデバイスのレイアウトでは、BLとBLBの両方の電流経路の接続経路抵抗は、小さいセル電流低下と優れたベータ比を提供する200Ωより小さい。
Port-A WL、Port-B WL、WL-A、WL-B ワード線
Port-A BL、Port-A BLB、Port-B BL、Port-B BLB、A_BL、A_BLB、B_BL、B_BLB ビット線
I 交差領域
Vss、Vdd 導体
10、20、30、40、50、60、200、205、210、215、220、225 活性領域
70、80、90、100、230、235、240、245、250、255 ゲート
260 接続
Claims (15)
- マルチポートスタティックランダムアクセスメモリ(SRAM)セルと、
前記SRAMセルのアクセスポートに接続された第1ビット線導体と、第1相補ビット線導体、第2ビット線導体と、第2相補ビット線導体と、
前記SRAMセルのアクセスポートに接続された第1ワード線と第2ワード線と、及び
前記SRAMセルに接続されたVdd電力供給導体と、4つのVss電力供給導体とを含み、
前記ビット線導体と前記電力供給導体は、第1共通金属化層に平行に設置され、前記Vdd電力供給導体が、前記第1共通金属化層の導体である、前記Vdd電力供給導体の第1側にある第1対の前記ビット線導体と、前記Vdd電力供給導体の第2側にある第2対の前記ビット線導体と、前記Vdd電力供給導体の前記第1側と第2側にある前記Vdd電力供給導体に隣接してそれぞれ設置された前記4つのVss電力供給導体のうちの第1、第2Vss電力供給導体と、前記ビット線導体の前記第1対の前記ビット線導体間に設置された第3Vss電力供給導体と、前記ビット線導体の前記第2対の前記ビット線導体間に設置された第4Vss電力供給導体との間の中心に位置される
メモリデバイス。 - 前記第1対の前記ビット線導体は、前記第1ビット線導体と前記第2ビット線導体を含み、前記第2対の前記ビット線導体は、第1相補ビット線導体と第2相補ビット線導体を含む
請求項1に記載のメモリデバイス。 - 前記ワード線導体は、第2共通金属化層に形成され、前記第2共通金属化層は、前記第1共通金属化層の上に形成される
請求項1に記載のメモリデバイス。 - 前記SRAMセル内に内部セル領域接続を形成する導体を含む前記第1共通金属化層の下に設置される第3共通金属化層を更に含む
請求項3に記載のメモリデバイス。 - 列と行に配列されたマルチポートスタティックランダムアクセスメモリ(SRAM)セルのアレイを含むメモリデバイスであって、各SRAMセルは、
データ蓄積ノードとデータバー蓄積ノードを有し、プルアップトランジスタと、共通して接続されたソース、ドレイン、ゲート端子をそれぞれ有するプルダウンデバイスをそれぞれ含む第1と第2交差結合インバータと、及び
第1と第2ワード線導体に接続され、前記データ蓄積ノードに接続された第1パスゲートトランジスタと、前記データバー蓄積ノードに接続された第2パスゲートトランジスタとをそれぞれ含み、各パスゲートトランジスタが第1ビット線導体、第1相補ビット線導体、第2ビット線導体と、第2相補ビット線導体の対応する1つに接続される第1と第2アクセスポートを含み、
各セルは、Vdd電力供給導体と4つのVss電力供給導体に接続され、前記ビット線導体と前記電力供給導体は、第1共通金属化層に平行に設置され、前記Vdd電力供給導体が、前記第1共通金属化層の前記導体である、前記Vdd電力供給導体の第1側にある第1対の前記ビット線導体と、前記Vdd電力供給導体の第2側にある第2対の前記ビット線導体と、前記Vdd電力供給導体の前記第1側と第2側にある前記Vdd電力供給導体に隣接してそれぞれ設置された前記4つのVss電力供給導体のうちの第1、第2Vss電力供給導体と、前記ビット線導体の前記第1対の前記ビット線導体間に設置された第3Vss電力供給導体と、前記ビット線導体の前記第2対の前記ビット線導体間に設置された第4Vss電力供給導体との間の中心に位置される
メモリデバイス。 - 前記第1インバータの前記プルダウントランジスタは、第1活性領域に形成され、前記第2インバータの前記プルダウントランジスタは、第2活性領域に形成され、前記データ蓄積ノードに接続された前記パスゲートトランジスタは、第3活性領域に形成され、前記データバー蓄積ノードに接続された前記パスゲートトランジスタは、第4活性領域に形成される
請求項5に記載のメモリデバイス。 - 前記第1インバータの前記プルアップトランジスタは、第5活性領域に位置され、前記第2インバータの前記プルアップトランジスタは、第6活性領域に位置される
請求項6に記載のメモリデバイス。 - 前記活性領域は、前記アレイの複数のSRAMセル全体に延伸する
請求項6に記載のメモリデバイス。 - 前記第1インバータのプルダウントランジスタのゲート端子と前記第1インバータのプルアップトランジスタのゲート端子は、第1共通ゲートラインによって一緒に接続され、且つ
前記第2インバータのプルダウントランジスタのゲート端子と前記第2インバータのプルアップトランジスタのゲート端子は、第2共通ゲートラインによって一緒に接続される
請求項6に記載のメモリデバイス。 - 前記第1と第2共通ゲートラインは、前記第1と第2活性領域をそれぞれ覆うU型部分をそれぞれ含む
請求項9に記載のメモリデバイス。 - 前記第1対の前記ビット線導体は、前記第1ビット線導体と前記第2ビット線導体を含み、前記第2対の前記ビット線導体は、第1相補ビット線導体と第2相補ビット線導体を含む
請求項5に記載のメモリデバイス。 - 前記ワード線導体は、第2共通金属化層に形成され、前記第2共通金属化層は、前記第1共通金属化層の上に形成される
請求項5に記載のメモリデバイス。 - 前記SRAMセル内に内部セル領域接続を形成する導体を含む前記第1共通金属化層の下に設置される第3共通金属化層を更に含む
請求項12に記載のメモリデバイス。 - 前記第1金属化層は、前記パスゲートトランジスタと前記プルダウンデバイス間と、前記プルダウンデバイスと前記プルアップトランジスタ間の内部セル領域接続を形成する導体を含む
請求項13に記載のメモリデバイス。 - 各SRAMセルは、ねじれビット線導体接合によってアレイのもう1つのSRAMセルに接合される
請求項5に記載のメモリデバイス。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/533,394 US8009463B2 (en) | 2009-07-31 | 2009-07-31 | Cell structure for dual port SRAM |
US12/533,394 | 2009-07-31 | ||
US12/651,667 US8189368B2 (en) | 2009-07-31 | 2010-01-04 | Cell structure for dual port SRAM |
US12/651,667 | 2010-01-04 |
Publications (2)
Publication Number | Publication Date |
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JP2011035398A true JP2011035398A (ja) | 2011-02-17 |
JP5232201B2 JP5232201B2 (ja) | 2013-07-10 |
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Application Number | Title | Priority Date | Filing Date |
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JP2010170119A Active JP5232201B2 (ja) | 2009-07-31 | 2010-07-29 | デュアルポートsramセルの構造 |
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Country | Link |
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US (1) | US8189368B2 (ja) |
JP (1) | JP5232201B2 (ja) |
KR (1) | KR101161506B1 (ja) |
CN (1) | CN101989604B (ja) |
TW (1) | TWI427772B (ja) |
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WO2015019411A1 (ja) | 2013-08-06 | 2015-02-12 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
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JP2016531433A (ja) * | 2013-07-29 | 2016-10-06 | ザイリンクス インコーポレイテッドXilinx Incorporated | デュアルポートメモリセル |
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CN101989604B (zh) | 2012-12-12 |
KR101161506B1 (ko) | 2012-06-29 |
KR20110013212A (ko) | 2011-02-09 |
JP5232201B2 (ja) | 2013-07-10 |
US8189368B2 (en) | 2012-05-29 |
US20110026289A1 (en) | 2011-02-03 |
CN101989604A (zh) | 2011-03-23 |
TW201110326A (en) | 2011-03-16 |
TWI427772B (zh) | 2014-02-21 |
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