JP2010528402A5 - - Google Patents

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Publication number
JP2010528402A5
JP2010528402A5 JP2010509586A JP2010509586A JP2010528402A5 JP 2010528402 A5 JP2010528402 A5 JP 2010528402A5 JP 2010509586 A JP2010509586 A JP 2010509586A JP 2010509586 A JP2010509586 A JP 2010509586A JP 2010528402 A5 JP2010528402 A5 JP 2010528402A5
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JP
Japan
Prior art keywords
bit line
levels
level
line decoder
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2010509586A
Other languages
English (en)
Japanese (ja)
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JP2010528402A (ja
JP5339541B2 (ja
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Publication date
Application filed filed Critical
Priority claimed from PCT/US2008/064881 external-priority patent/WO2008148091A1/en
Publication of JP2010528402A publication Critical patent/JP2010528402A/ja
Publication of JP2010528402A5 publication Critical patent/JP2010528402A5/ja
Application granted granted Critical
Publication of JP5339541B2 publication Critical patent/JP5339541B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2010509586A 2007-05-25 2008-05-27 ビット線デコーダ及び集積回路 Expired - Fee Related JP5339541B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US94020607P 2007-05-25 2007-05-25
US60/940,206 2007-05-25
PCT/US2008/064881 WO2008148091A1 (en) 2007-05-25 2008-05-27 Tree type bit line decoder architecture for nor-type memory array

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013161466A Division JP5598803B2 (ja) 2007-05-25 2013-08-02 集積回路及び装置

Publications (3)

Publication Number Publication Date
JP2010528402A JP2010528402A (ja) 2010-08-19
JP2010528402A5 true JP2010528402A5 (enExample) 2011-07-21
JP5339541B2 JP5339541B2 (ja) 2013-11-13

Family

ID=39683760

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2010509586A Expired - Fee Related JP5339541B2 (ja) 2007-05-25 2008-05-27 ビット線デコーダ及び集積回路
JP2013161466A Expired - Fee Related JP5598803B2 (ja) 2007-05-25 2013-08-02 集積回路及び装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2013161466A Expired - Fee Related JP5598803B2 (ja) 2007-05-25 2013-08-02 集積回路及び装置

Country Status (4)

Country Link
US (5) US7869246B2 (enExample)
JP (2) JP5339541B2 (enExample)
CN (1) CN101681673B (enExample)
WO (1) WO2008148091A1 (enExample)

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* Cited by examiner, † Cited by third party
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US5047026A (en) * 1989-09-29 1991-09-10 Everest Medical Corporation Electrosurgical implement for tunneling through tissue
CN102568581B (zh) * 2010-12-20 2015-09-09 中国科学院电子学研究所 一种适用于可编程存储器的递进式译码器
JP6166098B2 (ja) * 2013-05-13 2017-07-19 サイプレス セミコンダクター コーポレーション 半導体メモリおよび半導体メモリの動作方法
DE102013222996A1 (de) * 2013-11-12 2015-05-28 Robert Bosch Gmbh Scheibenwischvorrichtung
CN113918481A (zh) * 2017-07-30 2022-01-11 纽罗布拉德有限公司 一种存储器芯片
US11895851B2 (en) * 2021-10-12 2024-02-06 Micron Technology, Inc. Cross point array architecture for multiple decks
WO2025235018A1 (en) * 2024-05-10 2025-11-13 Silicon Storage Technology, Inc. Array of multi-value non-volatile memory cells

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JPH06318683A (ja) * 1993-05-01 1994-11-15 Toshiba Corp 半導体記憶装置及びその製造方法
JP3130705B2 (ja) * 1993-06-25 2001-01-31 株式会社東芝 半導体メモリ回路
JP2975532B2 (ja) * 1994-02-10 1999-11-10 株式会社メガチップス 半導体記憶装置およびその製造方法
KR0172378B1 (ko) * 1995-12-30 1999-03-30 김광호 불휘발성 반도체 메모리소자
EP0783169B1 (de) * 1996-01-08 2003-03-19 Infineon Technologies AG Matrix-Speicher (Virtual Ground)
JP2836570B2 (ja) * 1996-03-28 1998-12-14 日本電気株式会社 半導体記憶装置
KR100243003B1 (ko) * 1997-02-26 2000-03-02 김영환 플랫셀 어레이의 온/오프전류비 개선회로
KR100252475B1 (ko) * 1997-05-24 2000-04-15 윤종용 반도체 롬 장치
KR100274591B1 (ko) * 1997-07-29 2001-01-15 윤종용 동기형 버스트 매스크 롬 및 그것의 데이터 독출 방법
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