JP2010252288A - 信号周波数変更回路及びその周波数変更方法 - Google Patents

信号周波数変更回路及びその周波数変更方法 Download PDF

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Publication number
JP2010252288A
JP2010252288A JP2009178346A JP2009178346A JP2010252288A JP 2010252288 A JP2010252288 A JP 2010252288A JP 2009178346 A JP2009178346 A JP 2009178346A JP 2009178346 A JP2009178346 A JP 2009178346A JP 2010252288 A JP2010252288 A JP 2010252288A
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Japan
Prior art keywords
signal
delay
clock signal
frequency
output
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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JP2009178346A
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English (en)
Japanese (ja)
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JP2010252288A5 (enExample
Inventor
椿 錫 ▲鄭▼
Chun Seok Jeong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
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Hynix Semiconductor Inc
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Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of JP2010252288A publication Critical patent/JP2010252288A/ja
Publication of JP2010252288A5 publication Critical patent/JP2010252288A5/ja
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits
    • G01R31/3163—Functional testing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
JP2009178346A 2009-04-15 2009-07-30 信号周波数変更回路及びその周波数変更方法 Ceased JP2010252288A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090032898A KR101069671B1 (ko) 2009-04-15 2009-04-15 신호 주파수 변경 회로 및 그 주파수 변경 방법

Publications (2)

Publication Number Publication Date
JP2010252288A true JP2010252288A (ja) 2010-11-04
JP2010252288A5 JP2010252288A5 (enExample) 2012-09-13

Family

ID=42958942

Family Applications (1)

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JP2009178346A Ceased JP2010252288A (ja) 2009-04-15 2009-07-30 信号周波数変更回路及びその周波数変更方法

Country Status (4)

Country Link
US (1) US7876134B2 (enExample)
JP (1) JP2010252288A (enExample)
KR (1) KR101069671B1 (enExample)
CN (1) CN101867357B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012120045A (ja) * 2010-12-02 2012-06-21 Olympus Corp パルス走行位置検出回路、ａ／ｄ変換回路および固体撮像素子
CN106646282A (zh) * 2017-01-03 2017-05-10 中国地质大学（武汉） 一种基于量化时延法提高fid信号测频精度的方法及电路

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101562440B (zh) * 2009-05-12 2010-11-10 华为技术有限公司 延迟模块和方法、时钟检测装置及数字锁相环
US8552783B2 (en) * 2011-06-10 2013-10-08 International Business Machines Corporation Programmable delay generator and cascaded interpolator
CN102854451A (zh) * 2011-06-29 2013-01-02 鸿富锦精密工业（深圳）有限公司 印刷电路板的信号群延迟分析系统及方法
CN103258571B (zh) * 2012-02-20 2016-02-17 北京兆易创新科技股份有限公司 一种串行接口快闪存储器及时钟倍频电路
US20140218084A1 (en) * 2013-02-06 2014-08-07 Nvidia Corporation Approach to clock frequency modulation of a fixed frequency clock source
US9319037B2 (en) * 2014-02-03 2016-04-19 Advanced Micro Devices, Inc. Self-adjusting clock doubler and integrated circuit clock distribution system using same
US10481187B2 (en) 2014-12-31 2019-11-19 Texas Instruments Incorporated Frequency synthesizer output cycle counter including ring encoder
US9923570B2 (en) * 2016-04-12 2018-03-20 Microchip Technology Incorporated Time-based delay line analog-to-digital converter with variable resolution
CN110502065A (zh) * 2018-05-17 2019-11-26 瑞昱半导体股份有限公司 时钟管理电路及时钟管理方法
CN108832915B (zh) * 2018-09-13 2024-05-14 长江存储科技有限责任公司 一种占空比校准电路
CN109856472B (zh) * 2018-12-13 2021-06-29 江汉大学 基于多路检测信号的小型化鱼池捕检定装置

Citations (7)

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JPH05199088A (ja) * 1991-02-25 1993-08-06 Toshiba Corp 遅延回路
JPH06164339A (ja) * 1992-11-17 1994-06-10 Nippondenso Co Ltd デジタル制御遅延装置及びデジタル制御発振装置
JPH11266239A (ja) * 1998-03-18 1999-09-28 Toshiba Corp クロック同期遅延制御回路
JP2002132375A (ja) * 2000-10-19 2002-05-10 Yamaha Corp クロック信号制御回路
JP2002158566A (ja) * 2000-11-21 2002-05-31 Nec Corp 固定長遅延生成回路
JP2004364252A (ja) * 2003-05-31 2004-12-24 Hynix Semiconductor Inc デジタル遅延固定ループ
JP2006093748A (ja) * 2004-09-16 2006-04-06 Renesas Technology Corp 半導体集積回路装置のタイミング制御回路

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JP2000132266A (ja) 1998-10-23 2000-05-12 Mitsubishi Electric Corp 内部クロック信号発生回路、位相比較器、および内部クロック信号発生回路の試験方法
JP2001228216A (ja) 2000-02-18 2001-08-24 Nec Corp デバイス動的特性測定用テスト回路
US6362668B1 (en) * 2000-03-23 2002-03-26 Cypress Semiconductor Corp. Circuit and method for frequency generator control
US6339346B1 (en) 2000-08-30 2002-01-15 United Memories, Inc. Low skew signal generation circuit
KR100500929B1 (ko) * 2002-11-27 2005-07-14 주식회사 하이닉스반도체 지연 고정 루프 회로
KR100576475B1 (ko) * 2003-12-26 2006-05-10 주식회사 하이닉스반도체 내부 클럭 더블러 및 이를 포함한 반도체 메모리 장치
KR100682182B1 (ko) 2004-04-12 2007-02-12 주식회사 하이닉스반도체 내부 클럭 더블러 및 이를 포함한 반도체 메모리 장치 및그의 데이터 출력방법
KR100613059B1 (ko) 2004-04-20 2006-08-16 주식회사 하이닉스반도체 지연 동기 루프
US7068081B2 (en) * 2004-05-04 2006-06-27 Hewlett-Packard Development Company, L.P. Frequency synthesizer with digital phase selection
US7145371B2 (en) * 2004-07-30 2006-12-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Variable frequency generator
US7132863B2 (en) 2005-04-04 2006-11-07 Freescale Semiconductor, Inc. Digital clock frequency doubler
US7667504B2 (en) * 2007-05-22 2010-02-23 International Business Machines Corporation Signal delay element, method and integrated circuit device for frequency adjustment of electronic signals

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JPH05199088A (ja) * 1991-02-25 1993-08-06 Toshiba Corp 遅延回路
JPH06164339A (ja) * 1992-11-17 1994-06-10 Nippondenso Co Ltd デジタル制御遅延装置及びデジタル制御発振装置
JPH11266239A (ja) * 1998-03-18 1999-09-28 Toshiba Corp クロック同期遅延制御回路
JP2002132375A (ja) * 2000-10-19 2002-05-10 Yamaha Corp クロック信号制御回路
JP2002158566A (ja) * 2000-11-21 2002-05-31 Nec Corp 固定長遅延生成回路
JP2004364252A (ja) * 2003-05-31 2004-12-24 Hynix Semiconductor Inc デジタル遅延固定ループ
JP2006093748A (ja) * 2004-09-16 2006-04-06 Renesas Technology Corp 半導体集積回路装置のタイミング制御回路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JPN6009010660; 湯山俊夫著: 「ディジタルＩＣ回路の設計」 第２版, 19870110, ４１〜４７頁, ＣＱ出版株式会社 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012120045A (ja) * 2010-12-02 2012-06-21 Olympus Corp パルス走行位置検出回路、ａ／ｄ変換回路および固体撮像素子
CN106646282A (zh) * 2017-01-03 2017-05-10 中国地质大学（武汉） 一种基于量化时延法提高fid信号测频精度的方法及电路

Also Published As

Publication number Publication date
KR20100114389A (ko) 2010-10-25
CN101867357A (zh) 2010-10-20
US20100264960A1 (en) 2010-10-21
KR101069671B1 (ko) 2011-10-04
US7876134B2 (en) 2011-01-25
CN101867357B (zh) 2014-07-23

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