JP2010177481A - 電子部材ならびに電子部品とその製造方法 - Google Patents
電子部材ならびに電子部品とその製造方法 Download PDFInfo
- Publication number
- JP2010177481A JP2010177481A JP2009018959A JP2009018959A JP2010177481A JP 2010177481 A JP2010177481 A JP 2010177481A JP 2009018959 A JP2009018959 A JP 2009018959A JP 2009018959 A JP2009018959 A JP 2009018959A JP 2010177481 A JP2010177481 A JP 2010177481A
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- Prior art keywords
- silver
- layer
- bonding
- silver oxide
- electrode
- Prior art date
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Images
Classifications
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
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- C25D11/34—Anodisation of metals or alloys not provided for in groups C25D11/04 - C25D11/32
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- Die Bonding (AREA)
Abstract
【解決手段】酸化銀から銀へ還元する際、酸化銀内に多数の金属銀の核が形成し、元の外形を維持したまま形骸化して還元され、生成する銀の曲率は大きくなる。この微粒子化メカニズムを利用することで、酸化銀を粒子状ではなく、緻密な層状で提供しても接合が可能となる。電気信号を入出力する電極または電気信号を接続するための接続端子を備えた電子部材であって、電極または接続端子の最表面が酸化銀層205であることを特徴とする。
【選択図】図2
Description
102 銀粒子
103 還元前の酸化銀外形
200 回路基板
201 基板絶縁層
202,706,809 配線
203 メタライズ層(電極)
204,506 レジスト
205,305,405,411,508,604,801,806,811 酸化銀層
205a 焼結銀層(接合層)
205b 焼結銀層(粗化層)
206 チップ
207,603,909 電極
208,705,802 メタライズ層
209 LSIチップ
300 リードフレーム
301 ダイパッド
302,402 リード
303,403 Niめっき
304,404,507 Agめっき
306,901,906 半導体素子
307,407,607,905 接合層
308,408a,408b 粗化層
309,409 Auワイヤ
310,410 エポキシ樹脂
400 リードフレーム
401 ダイパッド部
406 Si素子
501 絶縁性フィルム
502 接着剤層
503 Cu箔
504 フォトレジスト
505 接続端子領域
601 絶縁フィルム
602 アンテナ
605 RFIDチップ
606 バンプ電極
608 アンダーフィル
609 ラミネート
701 有機基板
702 LEDチップ
703 金属線
704 リフレクタ
707 接合部
708,904,907 Agメタライズ
709 蛍光体
803 受動部品
804 LSIチップ
805,910 バンプ
807 コア
808 スルーホール
810 プリプレグ
812,903 貫通電極
813 焼結銀層
814 焼結銀粗化層
902 絶縁層
908 インターポーザ
Claims (25)
- 電気信号を入出力する電極または電気信号を接続するための接続端子を備えた電子部材であって、前記電極または接続端子の最表面が酸化銀層であることを特徴とする電子部材。
- 請求項1において、前記酸化銀層の下地が銀層であることを特徴とする電子部材。
- 請求項1において、前記酸化銀層の厚さが400nm〜5μmであることを特徴とする電子部材。
- 請求項1において、前記酸化銀層の最表面が1μmより小さい曲率半径となっていることを特徴とする電子部材。
- 請求項1において、前記酸化銀層の表面に融点が200℃以上である有機金属塩からなる層が形成されていることを特徴とする電子部材。
- 請求項1において、前記酸化銀層の表面に室温で固体であるアルコール類,カルボン酸類,アミン類からなる層が形成されていることを特徴とする電子部材。
- 請求項1において、前記酸化銀層が、曲率を有した接続端子あるいは電極上に設けられていることを特徴とする電子部材。
- 請求項1において、前記酸化銀層が接続端子あるいは電極が突起状であることを特徴とする電子部材。
- 回路基板に設けられた一つ以上の接続端子に対して、電子部材に設けられた一つ以上の電極端子が接合層を介して電気的に接合された電子部品であって、前記接合層は結晶粒径が1000nm以下の結晶粒径を有する焼結銀を主体として構成され、前記接合層と接していない電極表面の全面あるいは一部が金属銀または酸化銀の粗化層であることを特徴とする電子部品。
- 請求項9において、前記回路基板と電子部材との間に樹脂が充填されており、前記接合層と接していない前記電極の全面あるいは一部が金属銀または酸化銀の粗化層を介して樹脂と接着していることを特徴とする電子部品。
- 請求項9において、前記焼結銀が多孔質であり、焼結銀の孔内に樹脂が充填されていることを特徴とする電子部品。
- 請求項9のおいて、前記接続端子あるいは前記電極は、Ag,Au,Cu,Pt,Ni,Co,Ti,Mo,Fe,Al,Znの単体,合金あるいは混合物から選択される少なくとも1つの材料で構成されることを特徴とする電子部品。
- 請求項9において、前記接続端子あるいは電極が、Snの単体,Sn合金あるいは混合物から選択される少なくとも1つの材料で構成されることを特徴とする電子部品。
- 請求項9において、前記電極と前記接合端子の接合部にバンプが存在することを特徴とする電子部品。
- 一つ以上の電子部品が内蔵された多層配線基板であって、前記電子部品の電極間の接合層は結晶粒径が1000nm以下の結晶粒径を有する焼結銀と樹脂により構成され、前記接合層と電極表面と樹脂の全面あるいは一部が金属銀または酸化銀の粗化層を介していることを特徴とする電子部品内蔵の多層配線基板。
- 複数のLSIチップが積層チップであって、前記チップ間の電極が接合層を介して電気的に接合されており、前記接合層は結晶粒径が1000nm以下の結晶粒径を有する焼結銀を主体として構成され、前記接合層以外の電極表面の全面あるいは一部が金属銀の粗化層であることを特徴とする積層チップ。
- 電気信号を入出力する電極または電気信号を接続するための接続端子を備えた電子部材の製造方法において、前記電極または接続端子の最表面に銀層を形成し、さらに前記銀層を酸化処理し、前記銀層の全部あるいは一部を酸化銀層とすることを特徴とする電子部材の製造方法。
- 請求項17において、前記銀層を鍛造または溶着により形成することを特徴とする電子部材の製造方法。
- 請求項17において、前記銀層を蒸着またはめっきにより形成することを特徴とする電子部材の製造方法。
- 請求項17において、前記酸化銀層を陽極酸化またはオゾン酸化により形成することを特徴とする電子部材の製造方法。
- 回路基板に設けられた一つ以上の接続端子と電子部材に設けられた一つ以上の電極端子とを接合層を介して電気的に接合する電子部品の実装方法であって、
前記接続端子または前記電極端子の少なくとも一方の表面が酸化銀層で構成されており、
前記酸化銀層に還元剤を供給し、少なくとも接合面に100℃〜400℃の加熱を付与し、少なくとも酸化銀が金属銀に還元する際に接合面に0.1〜20MPaの加圧を付与することで、前記接続端子と前記電極端子間を電気的に接合することを特徴とする電子部品の実装方法。 - 請求項21において、前記還元剤がアルコール類,カルボン酸類,アミン類であることを特徴とする電子部品の実装方法。
- 請求項21において、前記還元剤を電子部材の接合面にのみ供給し、接合面以外を酸化銀層のまま残存させることを特徴とする電子部品の実装方法。
- 回路基板に設けられた一つ以上の接続端子と電子部材に設けられた一つ以上の電極端子とを接合層を介して電気的に接合する電子部品の実装方法であって、
前記接続端子または前記電極端子の少なくとも一方の表面が酸化銀層で構成されており、
還元ガス雰囲気で少なくとも接合面に100℃〜400℃の加熱を付与し、少なくとも酸化銀が金属銀に還元する際に接合面に0.1〜20MPaの加圧を付与することで、前記接続端子と前記電極端子間を電気的に接合することを特徴とする電子部品の実装方法。 - 請求項24において、還元剤を酸化銀層に供給して加熱処理することを特徴とする電子部品の実装方法。
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