JP2010062175A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP2010062175A
JP2010062175A JP2008223171A JP2008223171A JP2010062175A JP 2010062175 A JP2010062175 A JP 2010062175A JP 2008223171 A JP2008223171 A JP 2008223171A JP 2008223171 A JP2008223171 A JP 2008223171A JP 2010062175 A JP2010062175 A JP 2010062175A
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JP
Japan
Prior art keywords
wiring
oxide film
protective film
layer
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008223171A
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English (en)
Japanese (ja)
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JP2010062175A5 (enExample
Inventor
Ichiro Kono
一郎 河野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP2008223171A priority Critical patent/JP2010062175A/ja
Publication of JP2010062175A publication Critical patent/JP2010062175A/ja
Publication of JP2010062175A5 publication Critical patent/JP2010062175A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2008223171A 2008-09-01 2008-09-01 半導体装置の製造方法 Pending JP2010062175A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008223171A JP2010062175A (ja) 2008-09-01 2008-09-01 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008223171A JP2010062175A (ja) 2008-09-01 2008-09-01 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2010062175A true JP2010062175A (ja) 2010-03-18
JP2010062175A5 JP2010062175A5 (enExample) 2011-05-19

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ID=42188701

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008223171A Pending JP2010062175A (ja) 2008-09-01 2008-09-01 半導体装置の製造方法

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JP (1) JP2010062175A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012114148A (ja) * 2010-11-22 2012-06-14 Fujitsu Semiconductor Ltd 半導体装置の製造方法
CN106887422A (zh) * 2015-12-16 2017-06-23 台湾积体电路制造股份有限公司 封装件结构及其形成方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5780148A (en) * 1980-11-08 1982-05-19 Matsushita Electric Works Ltd Solar-heat absorbing element
JPH05175648A (ja) * 1991-12-24 1993-07-13 Matsushita Electric Works Ltd 回路板の銅回路の処理方法
JP2002093948A (ja) * 2000-07-13 2002-03-29 Oki Electric Ind Co Ltd ウェハー及びウェハーの製造方法
JP2004022699A (ja) * 2002-06-14 2004-01-22 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2006270031A (ja) * 2005-02-25 2006-10-05 Casio Comput Co Ltd 半導体装置およびその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5780148A (en) * 1980-11-08 1982-05-19 Matsushita Electric Works Ltd Solar-heat absorbing element
JPH05175648A (ja) * 1991-12-24 1993-07-13 Matsushita Electric Works Ltd 回路板の銅回路の処理方法
JP2002093948A (ja) * 2000-07-13 2002-03-29 Oki Electric Ind Co Ltd ウェハー及びウェハーの製造方法
JP2004022699A (ja) * 2002-06-14 2004-01-22 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2006270031A (ja) * 2005-02-25 2006-10-05 Casio Comput Co Ltd 半導体装置およびその製造方法

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012114148A (ja) * 2010-11-22 2012-06-14 Fujitsu Semiconductor Ltd 半導体装置の製造方法
CN106887422A (zh) * 2015-12-16 2017-06-23 台湾积体电路制造股份有限公司 封装件结构及其形成方法
CN107039381A (zh) * 2015-12-16 2017-08-11 台湾积体电路制造股份有限公司 半导体器件结构及其形成方法
KR20180021034A (ko) * 2015-12-16 2018-02-28 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 반도체 소자 구조체 및 이의 형성 방법
US10163817B2 (en) 2015-12-16 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same
KR101939531B1 (ko) * 2015-12-16 2019-01-16 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 반도체 소자 구조체 및 이의 형성 방법
US10224293B2 (en) 2015-12-16 2019-03-05 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for forming the same
CN107039381B (zh) * 2015-12-16 2019-11-08 台湾积体电路制造股份有限公司 半导体器件结构及其形成方法
US10636748B2 (en) 2015-12-16 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure
US10943873B2 (en) 2015-12-16 2021-03-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same

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