JP2009527928A - ソース/ドレインストレッサ、及び中間誘電体層ストレッサを統合する半導体の製造方法 - Google Patents
ソース/ドレインストレッサ、及び中間誘電体層ストレッサを統合する半導体の製造方法 Download PDFInfo
- Publication number
- JP2009527928A JP2009527928A JP2008556494A JP2008556494A JP2009527928A JP 2009527928 A JP2009527928 A JP 2009527928A JP 2008556494 A JP2008556494 A JP 2008556494A JP 2008556494 A JP2008556494 A JP 2008556494A JP 2009527928 A JP2009527928 A JP 2009527928A
- Authority
- JP
- Japan
- Prior art keywords
- source
- drain
- stressor
- semiconductor
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000000034 method Methods 0.000 claims abstract description 31
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 9
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 6
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims abstract 4
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical group [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 10
- 238000005530 etching Methods 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 230000008901 benefit Effects 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- -1 metal oxide compounds Chemical class 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000007858 starting material Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 239000013626 chemical specie Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002159 nanocrystal Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
Claims (20)
- 第1及び第2絶縁構造を、半導体層のトランジスタ領域の横方向のいずれの側にも位置するように形成する工程と、
ゲート構造をトランジスタ領域の一部分の上に形成するための、ゲート構造形成工程であって、前記ゲート構造は導電ゲート電極を、半導体層の上のゲート誘電体層の上に備えるとともに、ゲート電極の側壁によって、ゲート構造下のチャネル領域と、チャネル領域と第1及び第2絶縁構造との間に延びるソース/ドレイン領域との間の境界が、チャネル領域のいずれの側にも画定される、ゲート構造形成工程と、
半導体層の内、ソース/ドレイン領域に含まれる部分を除去してソース/ドレインリセスを形成する工程と、
第1及び第2絶縁構造の上側部分を除去して第1及び第2絶縁膜後退構造を形成する工程と、
ソース/ドレインリセスにソース/ドレインストレッサを充填する工程とからなる、半導体の製造方法。 - 第1及び第2絶縁構造を形成する工程では、第1及び第2シャロートレンチアイソレーション(STI)酸化シリコン構造を形成する、請求項1記載の半導体の製造方法。
- ソース/ドレインリセスの下側表面、及び絶縁膜後退構造の上側表面は、半導体基板の上側表面よりも下方にそれぞれ第1ずれ距離及び第2ずれ距離だけ垂直方向にずれ、第1ずれ距離は第2ずれ距離よりも長い、請求項1記載の半導体の製造方法。
- 第1ずれ距離は第2ずれ距離よりも約10〜30nmだけ長い、請求項3記載の半導体の製造方法。
- ソース/ドレインリセスに充填する工程は、第1及び第2絶縁膜後退構造を形成する前記工程の前に行なわれる、請求項3記載の半導体の製造方法。
- 第1及び第2絶縁膜後退構造を形成する前記工程は、ソース/ドレインリセスに充填する前記工程の前に行なわれる、請求項3記載の半導体の製造方法。
- 更に、中間誘電体層ストレッサを全面に堆積させ、中間誘電体層ストレッサはソース/ドレインストレッサの側壁に隣接する、請求項3記載の半導体の製造方法。
- 中間誘電体層ストレッサを堆積させる工程では、歪み窒化シリコンを堆積させる、請求項7記載の半導体の製造方法。
- 半導体基板はシリコンを含み、そしてソース/ドレインリセスに充填する工程では、半導体ソース/ドレイン構造をエピタキシャル成長させ、半導体ソース/ドレイン構造の格子定数はシリコンの格子定数とは異なる、請求項3記載の半導体の製造方法。
- 半導体ソース/ドレインストレッサは、約10〜50%の範囲のゲルマニウム含有量を有するシリコンゲルマニウム化合物を含む、請求項9記載の半導体の製造方法。
- 半導体ソース/ドレインストレッサは、約0.5〜5%の範囲の炭素含有量を有するシリコン炭素化合物を含む、請求項9記載の半導体の製造方法。
- 半導体基板のトランジスタ領域の横方向のいずれの側にも位置する第1及び第2絶縁膜後退構造と、絶縁膜後退構造の上側表面が半導体基板の上側表面の下方に位置することと、
トランジスタ領域の一部分の上に設けられたゲート構造と、前記ゲート構造は導電ゲート電極を基板の上のゲート誘電体層の上に備えることと、ゲート構造の側壁によって、ゲート構造下のチャネル領域と、チャネル領域と第1及び第2絶縁膜後退構造との間に延びるソース/ドレイン領域との間の境界が、チャネル領域のいずれの側にも画定されることと、
チャネル領域のいずれの側にも設けられたソース/ドレインストレッサと、前記ソース/ドレインストレッサの下側表面は絶縁膜後退構造の上側表面よりも下方に垂直方向にずれていることと、
前記絶縁膜後退構造の各々の上に設けられた中間誘電体層ストレッサと、前記中間誘電体層ストレッサは、それぞれのソース/ドレインストレッサの側壁に隣接することとからなる、集積回路。 - 第1及び第2絶縁膜後退構造は、第1及び第2シャロートレンチアイソレーション(STI)酸化シリコン構造を含む、請求項12記載の集積回路。
- ソース/ドレインストレッサの下側表面は、絶縁膜後退構造の上側表面よりも下方に、かつ垂直方向に約10〜30nmの範囲の距離だけずれる、請求項12記載の集積回路。
- 中間誘電体層ストレッサは窒化シリコンを含む、請求項12記載の集積回路。
- 半導体基板はシリコンを含み、そしてソース/ドレインストレッサの格子定数はシリコンの格子定数とは異なる、請求項15記載の集積回路。
- ソース/ドレインストレッサは、約10〜50%の範囲のゲルマニウム含有量を有するシリコンゲルマニウム化合物、及び約0.5〜5%の範囲の炭素含有量を有するシリコン炭素化合物から成るグループから選択される材料を含む、請求項16記載の集積回路。
- 絶縁膜後退構造の側壁はソース/ドレイン領域の側壁に隣接し、かつ絶縁膜後退構造の上側表面はソース/ドレイン領域の上側表面の下方に位置するように、絶縁膜後退構造を半導体ウェハの基板に形成する工程と、
中間誘電体層ストレッサ層はソース/ドレイン領域の側壁と接触し、そして中間誘電体層ストレッサ層はソース/ドレイン領域に対して歪みを与えるように、中間誘電体層ストレッサ層を絶縁膜後退構造、及び隣接するソース/ドレイン領域の上に堆積させる工程とからなる、半導体の製造方法。 - 絶縁膜後退構造を形成する前に、ソース/ドレイン領域の上側部分を除去してソース/ドレイン窪みを形成する工程と、ソース/ドレイン窪みに半導体材料をエピタキシャル成長によって充填する工程とをさらに備える、請求項18記載の半導体の製造方法。
- 絶縁膜後退構造は酸化シリコンからなり、中間誘電体層ストレッサ層は窒化シリコンからなり、ソース/ドレイン領域は、シリコンゲルマニウム及びシリコン炭素から成るグループから選択される材料からなる、請求項19記載の半導体の製造方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/361,171 US7538002B2 (en) | 2006-02-24 | 2006-02-24 | Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors |
US11/361,171 | 2006-02-24 | ||
PCT/US2007/061841 WO2007103609A2 (en) | 2006-02-24 | 2007-02-08 | Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009527928A true JP2009527928A (ja) | 2009-07-30 |
JP2009527928A5 JP2009527928A5 (ja) | 2010-03-11 |
JP5225108B2 JP5225108B2 (ja) | 2013-07-03 |
Family
ID=38444528
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008556494A Expired - Fee Related JP5225108B2 (ja) | 2006-02-24 | 2007-02-08 | ソース/ドレインストレッサ、及び中間誘電体層ストレッサを統合する半導体の製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7538002B2 (ja) |
EP (1) | EP1989729B1 (ja) |
JP (1) | JP5225108B2 (ja) |
KR (1) | KR101357986B1 (ja) |
CN (1) | CN101438394B (ja) |
WO (1) | WO2007103609A2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010010371A (ja) * | 2008-06-26 | 2010-01-14 | Fujitsu Microelectronics Ltd | 半導体装置及びその製造方法 |
JP2013016828A (ja) * | 2012-08-27 | 2013-01-24 | Sony Corp | 半導体装置 |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7465972B2 (en) * | 2005-01-21 | 2008-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance CMOS device design |
US7572705B1 (en) * | 2005-09-21 | 2009-08-11 | Advanced Micro Devices, Inc. | Semiconductor device and method of manufacturing a semiconductor device |
US7323392B2 (en) * | 2006-03-28 | 2008-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance transistor with a highly stressed channel |
US9209088B2 (en) * | 2007-08-01 | 2015-12-08 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US20090289280A1 (en) * | 2008-05-22 | 2009-11-26 | Da Zhang | Method for Making Transistors and the Device Thereof |
US8003454B2 (en) * | 2008-05-22 | 2011-08-23 | Freescale Semiconductor, Inc. | CMOS process with optimized PMOS and NMOS transistor devices |
US8361867B2 (en) * | 2010-03-19 | 2013-01-29 | Acorn Technologies, Inc. | Biaxial strained field effect transistor devices |
US8470674B2 (en) | 2011-01-03 | 2013-06-25 | International Business Machines Corporation | Structure, method and system for complementary strain fill for integrated circuit chips |
CN103377941B (zh) * | 2012-04-28 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Pmos晶体管及形成方法 |
US8928048B2 (en) * | 2013-01-17 | 2015-01-06 | Globalfoundries Inc. | Methods of forming semiconductor device with self-aligned contact elements and the resulting device |
KR102277398B1 (ko) * | 2014-09-17 | 2021-07-16 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
US10586866B2 (en) | 2015-12-09 | 2020-03-10 | Intel Corporation | Stressors for compressively strained GaN p-channel |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005098962A1 (en) * | 2004-03-31 | 2005-10-20 | Intel Corporation | Enhancing strained device performance by use of multi narrow section layout |
WO2006011939A2 (en) * | 2004-06-24 | 2006-02-02 | Applied Materials, Inc. | Methods for forming a transistor |
JP2006229071A (ja) * | 2005-02-18 | 2006-08-31 | Fujitsu Ltd | 半導体装置 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6297126B1 (en) | 1999-07-12 | 2001-10-02 | Chartered Semiconductor Manufacturing Ltd. | Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts |
US6649480B2 (en) | 2000-12-04 | 2003-11-18 | Amberwave Systems Corporation | Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
US6580122B1 (en) * | 2001-03-20 | 2003-06-17 | Advanced Micro Devices, Inc. | Transistor device having an enhanced width dimension and a method of making same |
EP1428262A2 (en) | 2001-09-21 | 2004-06-16 | Amberwave Systems Corporation | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same |
US6621131B2 (en) | 2001-11-01 | 2003-09-16 | Intel Corporation | Semiconductor transistor having a stressed channel |
JP2004031753A (ja) * | 2002-06-27 | 2004-01-29 | Renesas Technology Corp | 半導体装置の製造方法 |
US7101742B2 (en) * | 2003-08-12 | 2006-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel complementary field-effect transistors and methods of manufacture |
US20060022264A1 (en) * | 2004-07-30 | 2006-02-02 | Leo Mathew | Method of making a double gate semiconductor device with self-aligned gates and structure thereof |
US20060030093A1 (en) | 2004-08-06 | 2006-02-09 | Da Zhang | Strained semiconductor devices and method for forming at least a portion thereof |
US6979622B1 (en) * | 2004-08-24 | 2005-12-27 | Freescale Semiconductor, Inc. | Semiconductor transistor having structural elements of differing materials and method of formation |
WO2006111888A1 (en) * | 2005-04-20 | 2006-10-26 | Koninklijke Philips Electronics N.V. | A strained integrated circuit and a method of manufacturing the same |
-
2006
- 2006-02-24 US US11/361,171 patent/US7538002B2/en not_active Expired - Fee Related
-
2007
- 2007-02-08 CN CN2007800065911A patent/CN101438394B/zh not_active Expired - Fee Related
- 2007-02-08 KR KR1020087020579A patent/KR101357986B1/ko not_active IP Right Cessation
- 2007-02-08 EP EP07756764.2A patent/EP1989729B1/en not_active Not-in-force
- 2007-02-08 WO PCT/US2007/061841 patent/WO2007103609A2/en active Application Filing
- 2007-02-08 JP JP2008556494A patent/JP5225108B2/ja not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005098962A1 (en) * | 2004-03-31 | 2005-10-20 | Intel Corporation | Enhancing strained device performance by use of multi narrow section layout |
JP2007531323A (ja) * | 2004-03-31 | 2007-11-01 | インテル コーポレイション | 複数の狭区画レイアウトを用いたひずみデバイス |
WO2006011939A2 (en) * | 2004-06-24 | 2006-02-02 | Applied Materials, Inc. | Methods for forming a transistor |
JP2008504682A (ja) * | 2004-06-24 | 2008-02-14 | アプライド マテリアルズ インコーポレイテッド | トランジスタ形成方法 |
JP2006229071A (ja) * | 2005-02-18 | 2006-08-31 | Fujitsu Ltd | 半導体装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010010371A (ja) * | 2008-06-26 | 2010-01-14 | Fujitsu Microelectronics Ltd | 半導体装置及びその製造方法 |
JP2013016828A (ja) * | 2012-08-27 | 2013-01-24 | Sony Corp | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
CN101438394A (zh) | 2009-05-20 |
KR101357986B1 (ko) | 2014-02-03 |
EP1989729B1 (en) | 2013-04-10 |
EP1989729A2 (en) | 2008-11-12 |
JP5225108B2 (ja) | 2013-07-03 |
WO2007103609A2 (en) | 2007-09-13 |
WO2007103609A3 (en) | 2008-12-31 |
CN101438394B (zh) | 2010-09-08 |
US7538002B2 (en) | 2009-05-26 |
KR20080106910A (ko) | 2008-12-09 |
US20070202651A1 (en) | 2007-08-30 |
EP1989729A4 (en) | 2011-04-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5225108B2 (ja) | ソース/ドレインストレッサ、及び中間誘電体層ストレッサを統合する半導体の製造方法 | |
KR101622048B1 (ko) | 누설이 감소된 cmos 디바이스 및 그 형성 방법 | |
US9653574B2 (en) | Selective etching in the formation of epitaxy regions in MOS devices | |
KR101243997B1 (ko) | 응력이 가해진 mos 디바이스 제조 방법 | |
KR101369560B1 (ko) | FinFET를 위한 장치 및 방법 | |
TWI545761B (zh) | 半導體元件與其形成方法及p型金氧半電晶體 | |
TWI447815B (zh) | 使用蝕刻終止層以最佳化源極與汲極壓力層的形成之半導體製造方法 | |
TWI323944B (en) | Semiconductor device and fabrication method thereof | |
US20070023795A1 (en) | Semiconductor device and method of fabricating the same | |
US9620506B2 (en) | Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region | |
US8716076B2 (en) | Method for fabricating a semiconductor device having an epitaxial channel and transistor having same | |
US9620507B2 (en) | Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region | |
US7436005B2 (en) | Process for fabricating a heterostructure-channel insulated-gate field-effect transistor, and the corresponding transistor | |
WO2006020282A1 (en) | Strained semiconductor devices and method for forming at least a portion thereof | |
KR20120099863A (ko) | 트랜지스터 및 그 제조 방법 | |
CN105448832B (zh) | 一种半导体器件的制作方法 | |
US20100187579A1 (en) | Transistor devices and methods of making | |
KR20110123733A (ko) | 에피택셜 성장된 스트레스-유도 소오스 및 드레인 영역들을 가지는 mos 디바이스들의 제조 방법 | |
KR20080075411A (ko) | 반도체 소자 및 그 제조방법 | |
US20080173941A1 (en) | Etching method and structure in a silicon recess for subsequent epitaxial growth for strained silicon mos transistors | |
TWI585861B (zh) | 具有磊晶成長之應力引發源極與汲極區之金氧半導體裝置的製造方法 | |
US7951662B2 (en) | Method of fabricating strained silicon transistor | |
US7863130B2 (en) | Tunable stressed polycrystalline silicon on dielectrics in an integrated circuit | |
JP2008078347A (ja) | 半導体装置の製造方法および半導体装置 | |
TWI485783B (zh) | 具有封裝的壓力源區域的半導體裝置及製作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100120 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100120 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20121017 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20121023 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130123 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130219 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130312 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160322 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |