TWI447815B - 使用蝕刻終止層以最佳化源極與汲極壓力層的形成之半導體製造方法 - Google Patents
使用蝕刻終止層以最佳化源極與汲極壓力層的形成之半導體製造方法 Download PDFInfo
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Description
本發明係屬於半導體製造領域，且更特定言之為使用應變電晶體通道之半導體製造方法。
使用應變電晶體的半導體製造方法已為吾人所熟知。典型而言，沿著一或多個軸對電晶體通道施加拉伸應力或壓應力以提高通道中的載體移動率並藉此增進電晶體效能。用以對通道施加應力的一種技術包括使用源極與汲極壓力層。源極與汲極(S/D)壓力層係指使用具有晶格常數與電晶體通道材料(通常是矽)的晶格常數不同的源極與汲極材料。S/D壓力層典型而言係藉由蝕刻裝置的S/D區接著在蝕刻空穴內磊晶生長應變膜而實現。由於難以控制源極與汲極的蝕刻過程，因此形成這種源極與汲極壓力層可能會有問題。S/D蝕刻速率典型而言在晶圓各處有所不同，會因為不同裝置特徵密度的面積而改變。因此，蝕刻過程包括不想要的S/D凹入深度變化。希望實現能解決關於產生源極與汲極壓力層的習知技術之加工變異性的方法。
一方面而言，半導體製造過程包含在絕緣物上矽(SOI)晶圓之主動層與BOX層之間併入一蝕刻終止層(ESL)。此ESL有助於源極與汲極壓力層的形成。具體而言，此ESL係一種使主動層與ESL之間有高選擇率蝕刻法的材料。在一具體實施例中，主動層為矽主動層，ESL為矽鍺，而源極與汲極壓力層為半導體化合物，例如PMOS電晶體之矽鍺或NMOS電晶體之矽碳，其具有不同於矽之晶格常數的晶格常數。藉由結合ESL及高選擇性的源極與汲極蝕刻法，減少或消除與形成源極與汲極壓力層之習知方法有關的多餘變異性。本文所述的半導體製造方法之一態樣為在主動半導體層與BOX層之間形成具有ESL的SOI晶圓。
參考圖1至圖6，解說依據一項具體實施例製造此種晶圓的選取階段。所描繪的順序包括加工第一晶圓(施體晶圓donor wafer)以形成包含介電層、ESL及主動半導體層之疊層。此加工可包括裂離施體晶圓之基板以形成主動半導體層。使介電層沈積在第二晶圓(操作晶圓handle wafer)的半導體基板上。接著使施體晶圓之介電層與操作晶圓之介電層接合。接合的介電層係形成BOX層。
首先看到圖1，其係描繪製造方法中間階段之積體電路100的局部斷面圖。在此階段，已形成覆蓋於第一晶圓(本文中稱為施體晶圓90)之半導體主體104上的ESL 109。ESL 109以具有約5至30 nm範圍內之厚度之相對較薄的膜較佳，以具有小於或等於約10 nm之厚度者更佳。選擇ESL 109的組成主要是為了它的蝕刻特性。更具體而言，ESL 109宜為對半導體主體104具有蝕刻選擇性的材料。為了達到本揭示內容之目的，如果能夠發現蝕刻法對某一種材料有高度選擇性，則這一種材料相對於另一種材料而言具有蝕刻選擇性。在一較佳的具體實施例中，ESL 109與半導體主體104之間的選擇率宜為超過10：1。ESL 109的第二項考量為ESL 109對電晶體效能可能的影響。
在若干具體實施例中，半導體主體104為結晶矽，而ESL層為半導體主體104的偽形半導體化合物。在這些具體實施例中，由於矽鍺對於矽具有高蝕刻選擇性而且在電晶體通道下面存在矽鍺薄膜對電晶體特性可能會有助益，因此矽鍺化合物(Si(1－X)
GeX
)為適合ESL 109的材料。在這些具體實施例中，ESL 109的鍺含量(X)宜在約5至15%的範圍內，而在若干具體實施例中，其為後續形成之矽鍺源極與汲極壓力層(如以下關於圖9所述者)中鍺含量的函數。
參考圖2，沈積或用其他方法形成覆蓋於ESL 109上的介電層86。介電層86係作為製成積體電路中BOX層的至少一部分。介電層86的厚度較佳而言在約20至200 nm的範圍內。介電層86可為CVD氧化矽層，例如使用TEOS(四乙基正矽酸鹽)源以習知方式形成的氧化矽層。
觀看圖3，進行離子植入82，在半導體主體104內形成植入破壞層84。植入破壞層84將半導體主體104分成鄰接於ESL 109的第一區105以及與ESL 109分離的第二區107。在一項具體實施例中，植入破壞層84係使用5×1016
cm－2
或更高的植入劑量使氫植入半導體主體104內而產生。
觀看圖4，使操作晶圓94與施體晶圓90接合，如參考符號92所指示，以形成積體電路晶圓101。所描繪之操作晶圓94的製作包含覆蓋於主體部分98上的介電層96。操作晶圓94之介電層96較佳為與施體晶圓90之介電層86相同或類似的介電材料。操作晶圓94之主體部分98較佳為半導體材料，例如結晶矽。
植入破壞層84有助於圖5所示的裂離程序113，在此程序中，使植入破壞層84"下方"之半導體主體104的第二區107與施體晶圓90的其餘部分分離並且丟棄。在一項具體實施例中，離子植入82採用使破壞層84成為距ESL 109約50 nm之相對窄帶的能量和植入物種。適合的植入物種包含氫。在裂離程序113及製備用於裝置加工之第一區105的新表面後，施體晶圓90之第一區105係作為積體電路100的主動層，在此層中係形成電晶體且還可能形成其他的裝置。因此，第一區105在本文中有時稱為主動層105。
在此描繪的具體實施例中，利用熱接合或另外已知的接合技術使施體晶圓90之介電層86與操作晶圓94之介電層96接合，以在積體電路晶圓101中形成BOX層102。在此具體實施例中，如圖6所描繪的積體電路晶圓101，可稱為具有ESL 109的SOI晶圓，該ESL位於半導體主動層105與BOX層102之間。ESL 109的存在能穩定蝕刻主動層105而不會蝕刻到BOX層102，因此有助於壓力層的形成加工(詳細敘述如下)。
觀看圖7，依據一項具體實施例進行積體電路晶圓101的後續加工以形成隔離結構106和閘極結構110。隔離結構106係界定主動層105中之主動區或電晶體區103的側邊界。閘極結構110包含覆蓋於閘極介電質114上的導電閘電極112及位於閘電極112之側壁的間隔結構(間隔層)116。閘電極112之側邊界係概略界定了主動層105中之一電晶體通道115與設置在該電晶體通道115兩側之源極與汲極區117的側邊界。閘電極112為摻雜多晶矽、金屬或金屬矽化物材料、或其組合物的導電結構。閘極介電質114較佳為熱生成二氧化矽或高K介電質，例如二氧化鉿(HfO2
)。間隔層116較佳為氮化矽、氧化矽、或其組合物。源極與汲極延伸型植入可在間隔層形成之前進行。
在圖8中，實質上已移除主動層105的源極與汲極區117以產生使ESL 109上表面暴露出來的源極與汲極空隙120。在一項具體實施例中，移除源極與汲極區117包含一種對ESL 109具有高選擇性的蝕刻法。為了達到本揭示內容之目的，高選擇性蝕刻係指在最關注的兩種材料(即被蝕刻層和ESL)之間具有超過10：1的相對蝕刻速率之蝕刻法。在源極與汲極區117為矽而ESL 109為矽鍺的具體實施例中，舉例來說，移除源極與汲極區117的蝕刻法可包括使用加熱至約75℃之NH4
OH：H2
O溶液的濕式蝕刻成分。參見如Feng Wang等人之"Highly Selective Chemical Etching of Si vs.SiGe
"，J.Electrochemical Society，第144卷第3期，第L37－L39頁(1997年)(其敘述超過80：1的Si：SiGe選擇率)。
觀看圖9，再以本文中稱為源極與汲極壓力層130之源極與汲極結構填滿圖8的源極與汲極空隙120。在一具體實施例中，源極與汲極壓力層130具有與佔電晶體通道115大部分的原主動層105之晶格常數不同的晶格常數。源極與汲極壓力層130會對電晶體通道115產生應力，且最好會改善電晶體通道中相關載體的移動率。在PMOS電晶體中，舉例來說，在電晶體通道115中產生壓應力的源極與汲極壓力層130提高了電洞移動率，藉此增進PMOS電晶體的效能。在NMOS電晶體中，源極與汲極壓力層130宜在電晶體通道115中產生拉伸應力而提高電子移動率及增進NMOS電晶體的效能。適合PMOS電晶體的源極與汲極壓力層材料為矽鍺，而適合NMOS電晶體的源極與汲極壓力層材料為矽碳。在一具體實施例中，源極與汲極壓力層130為矽鍺化合物(Si(1－Y)
GeY
)，而ESL 109為矽鍺化合物(Si(1－X)
GeX
)，其中X和Y相異。在此具體實施例中，Y宜大於X以增強源極與汲極壓力層130的壓應力效應。可使此壓力膜摻雜以得到適當的導電率類型。摻雜程序可以在壓力膜磊晶生長過程中提供適當的反應物來源而就地進行，或者可以在壓力膜生長後，以植入方式實施。在摻雜程序後可以執行退火程序。
在前述說明書中，已參考特定具體實施例來說明本發明。然而，熟習此項技術者之一會明白，可在不脫離如以下申請專利範圍所提出之本發明之範疇下進行各種修改及變化。舉例來說，儘管此解說的具體實施例包括使具有Si/SiGe/氧化物疊層的施體晶圓與具有氧化物/Si疊層的操作晶圓接合以形成積體電路晶圓，但其他實施方式可使用磊晶，以超薄體(UTB)絕緣物上SiGe(SGOI)晶圓起始，生長Si主動層而產生SiGe蝕刻終止層。其他程序可以從隔離BOX之頂部上具有SiGe層的習知SGOI晶圓起始，使SiGe頂層變薄以形成ESL，然後使用磊晶生長Si主動層。因此，本說明書及附圖應視為說明性，而非限制性，且希望所有此類修改均包括於本發明之範疇內。
以上已針對特定具體實施例來說明利益、其他優點及問題解決方案。然而，此等利益、優點、問題解決方案，及引起任何利益、優點、或解決方案發生或突顯其重要性之任何(多個)元件，均不應視為任一或全部申請專利範圍之一關鍵、必要或本質特徵或元件。希望本文中所使用的術語"包括"、"包含"或其任何其他變化能涵蓋非專有內含項，以便包括元件清單的程序、方法、物品，或設備不僅包含該等元件，而且包含未明確列出或此類程序、方法、物品或設備固有的其他元件。
82．．．離子植入
84．．．(植入)破壞層
86．．．介電層
90．．．施體晶圓
94．．．操作晶圓
96．．．介電層
98．．．主體部分
100．．．積體電路
101．．．積體電路晶圓
102．．．嵌埋氧化物(BOX)層
103．．．主動區或電晶體區
104．．．半導體主體
105．．．第一區或(半導體)主動層
106．．．隔離結構
107．．．第二區
109．．．蝕刻終止層(ESL)
110．．．閘極結構
112．．．閘電極
113．．．裂離程序
114．．．閘極介電質
115．．．電晶體通道
116．．．間隔結構(間隔層)
117．．．源極與汲極區
120．．．源極與汲極空隙
130．．．源極與汲極壓力層
本發明以範例方式而加以說明，並不受限於該等附圖，其中相同參考符號指示相同元件，且其中：圖1為依據本發明之一項具體實施例於製造積體電路早期階段的半導體晶圓之局部斷面圖，強調在施體晶圓之半導體基板上形成蝕刻終止層；圖2描繪在圖1之後的加工，其中於蝕刻終止層上形成介電層；圖3描繪在圖2之後的加工，其中於施體晶圓基板中形成破壞層；圖4描繪在圖3之後的加工，其中使施體晶圓之介電層與操作晶圓之介電層接合以形成積體電路晶圓；圖5描繪在圖4之後的加工，其中使施體晶圓於圖3之破壞層處裂離，使新的上表面暴露出來；圖6描繪在圖5之後的加工，其中圖5之新的上表面係準備用於裝置加工；圖7描繪在圖6之後的加工，其中於主動半導體層上形成覆蓋於主動半導體層之電晶體通道上的閘極結構；圖8描繪在圖7之後的加工，其中於設置在電晶體通道兩側之晶圓的源極與汲極區內蝕刻源極與汲極空隙；及圖9描繪在圖8之後的加工，其中以源極與汲極壓力層填滿源極與汲極空隙。
熟知此項技術人士應瞭解，圖式中之元件係為簡單及清楚目的而顯示且無須依比例繪製。例如，圖式中某些元件的尺寸可能會相對於其它元件而誇大，以有助於增進瞭解本發明之具體實施例。
100．．．積體電路
101．．．積體電路晶圓
102．．．嵌埋氧化物(BOX)層
105．．．主動層
106．．．隔離結構
109．．．蝕刻終止層(ESL)
110．．．閘極結構
112．．．閘電極
114．．．閘極介電質
115．．．電晶體通道
116．．．間隔結構(間隔層)
130．．．源極與汲極壓力層
Claims (20)
- 一種半導體製造方法，其包含：提供一積體電路晶圓，其包含一覆蓋於一蝕刻終止層(ESL)上之主動半導體層，且該蝕刻終止層覆蓋於一嵌埋氧化物(BOX)層上，其中該蝕刻終止層與該嵌埋氧化物層接觸；形成一閘極結構，其包含一覆蓋於一閘極介電質上之閘電極，該閘極介電質覆蓋於該主動半導體層之一電晶體通道上；蝕刻設置在該電晶體通道兩側的源極與汲極區以形成源極與汲極空隙，其中該源極與汲極空隙使該ESL暴露出來；及以覆蓋於該ESL上的源極與汲極壓力層填滿該源極與汲極空隙，其中該源極與汲極壓力層的晶格常數與該主動半導體層的晶格常數不同。
- 如請求項1之半導體製造方法，其中該積體電路晶圓之該提供包含：於一施體晶圓之一半導體基板上形成該蝕刻終止層；於該蝕刻終止層上沈積一介電層；將氫植入該施體晶圓內，以於該施體晶圓之該半導體基板中形成破壞區；於一操作晶圓之一半導體基板上沈積一介電層；及使該施體晶圓之該介電層與該操作晶圓之該介電層接合；及 使該施體晶圓沿著該破壞區裂離。
- 如請求項1之半導體製造方法，其中該主動半導體層包含矽，且其中該ESL包含一半導體化合物。
- 如請求項3之方法，其中該半導體化合物為該主動半導體層的偽形半導體化合物。
- 如請求項4之半導體製造方法，其中該半導體化合物包含一矽鍺化合物Si(1-X) GeX ，該矽鍺化合物中鍺的百分率(X)在約5至15%的範圍內。
- 如請求項5之半導體製造方法，其中該源極與汲極壓力層包含一矽鍺化合物Si(1-Y) GeY ，該矽鍺化合物中鍺的百分率(Y)高於X。
- 如請求項4之半導體製造方法，其中該源極與汲極壓力層包含一矽碳化合物。
- 如請求項1之半導體製造方法，其中提供該積體電路晶圓包含形成該主動半導體層與該ESL，該主動半導體層與該ESL之間的蝕刻選擇率等於或超過10：1。
- 如請求項8之半導體製造方法，其中該主動半導體層為矽，且其中該ESL為矽鍺。
- 如請求項9之半導體製造方法，其中蝕刻該源極與汲極區包含使該積體電路晶圓浸入加熱至溫度約75℃的NH4 OH：H2 O溶液中。
- 如請求項1之半導體製造方法，其中提供該積體電路晶圓包含使用磊晶法於該ESL上生長該主動半導體層，且其中填滿該源極與汲極空隙包含使用磊晶法生長該該源 極與汲極空隙。
- 一種半導體製造方法，其包含：提供一位於一晶圓之嵌埋氧化物(BOX)層上且與該嵌埋氧化物層接觸的矽鍺蝕刻終止層(ESL)；形成一覆蓋於該矽鍺ESL上的主動半導體層；形成一覆蓋於該主動半導體層之一電晶體通道上的閘電極；使用一蝕刻法蝕刻設置在該電晶體通道兩側之主動半導體層的源極與汲極區，使該ESL暴露出來；及於該ESL上形成源極與汲極壓力層並且設置於該電晶體通道兩側，其中該源極與汲極壓力層對該電晶體通道產生應力。
- 如請求項12之半導體製造方法，其中提供該矽鍺ESL層包含磊晶生長該ESL。
- 如請求項12之半導體製造方法，其中該矽鍺ESL為該主動半導體層的偽形。
- 如請求項12之半導體製造方法，其中該主動半導體層之蝕刻速率與該ESL蝕刻速率的比率等於或超過10：1。
- 如請求項12之半導體製造方法，其中蝕刻該源極與汲極區包含在加熱至溫度約75℃的NH4 OH：H2 O溶液中濕式蝕刻該晶圓。
- 如請求項12之半導體製造方法，其中該ESL包含具有第一百分率之鍺的矽鍺，且其中該源極與汲極壓力層係由具有第二百分率之鍺的矽鍺組成，其中該第二百分率與 該第一百分率不同。
- 如請求項17之半導體製造方法，其中該第二百分率大於該第一百分率。
- 如請求項12之半導體製造方法，其中該源極與汲極壓力層係由矽碳組成。
- 一種半導體製造方法，其包含：形成一覆蓋於一嵌埋氧化物(BOX)層上的矽鍺蝕刻終止層(ESL)，其中該蝕刻終止層與該嵌埋氧化物層接觸；形成覆蓋於該ESL上且側向地設置於一矽電晶體通道兩側之矽鍺或矽碳的源極與汲極壓力層；及形成一覆蓋於該電晶體通道上的閘電極。
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- 2007-02-22 EP EP07757316A patent/EP2005477A4/en not_active Withdrawn
- 2007-02-22 KR KR1020087023819A patent/KR20080108498A/ko not_active Application Discontinuation
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Also Published As
| Publication number | Publication date |
|---|---|
| JP5203352B2 (ja) | 2013-06-05 |
| EP2005477A2 (en) | 2008-12-24 |
| KR20080108498A (ko) | 2008-12-15 |
| US7494856B2 (en) | 2009-02-24 |
| JP2009532875A (ja) | 2009-09-10 |
| EP2005477A4 (en) | 2012-06-13 |
| WO2007117775A2 (en) | 2007-10-18 |
| US20070238250A1 (en) | 2007-10-11 |
| TW200802624A (en) | 2008-01-01 |
| WO2007117775A3 (en) | 2007-12-21 |
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