CN101438394B - 集成源/漏应激体和层间电介质层应激体的半导体工艺 - Google Patents
集成源/漏应激体和层间电介质层应激体的半导体工艺 Download PDFInfo
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Abstract
一种半导体制造工艺，包括：在晶体管区的任一侧上形成隔离结构(106)；形成栅结构(110)覆盖在所述晶体管区上面，去除源/漏区(107)以形成源/漏凹陷(120)；去除所述隔离结构的一些部分以形成凹陷的隔离结构(126)；以及用源/漏应激物，诸如外延地形成的半导体，填充所述源/漏凹陷。源/漏凹陷的下表面优选地比凹陷的隔离结构的上表面深约10到30nm。填充所述源/漏凹陷可以在形成所述凹陷的隔离结构之前或之后。随后在所述晶体管区上方淀积ILD应激物(140)，因此，ILD应激物与所述源/漏结构的侧壁相邻，从而将ILD应激物连接到源/漏应激物。ILD应激物优选地为压缩或拉伸的氮化硅，且所述源/漏结构优选为硅锗或硅碳。
Description
技术领域
本发明属于半导体制造工艺领域，更具体地，属于采用应变硅的半导体制造工艺领域。
背景技术
在半导体制造工艺领域中使用应变或应力硅以增强深亚微米晶体管中的载流子迁移率。实现应变硅的提议包括与硅晶体管沟道相邻提供源/漏应激体的源/漏区的工程(参见，例如T.Ghani等人的，A 90nmhigh volume manufacturing logic technology featuring novel 45nm gatelength strained silicon CMOS transistors，IEDM Tech.Dig.p.978(2003)以及Murthy等人的美国专利No.6,621,131，Semiconductor transistorHaving a Stressed Channel)。其它提议指出在晶体管上方淀积应力感应层间介质(ILD)层(参见，例如C.H Ge等人的，Process-strained Si CMOStechnology featuring 3D strain engineering，IEDM Tech.Dig.p.73，(2003))。理想的是执行一种工艺，便于源/漏应激体和ILD应激体的最佳连接，而基本无需增加制造工艺的成本或复杂性。
发明内容
附图说明
本发明通过实例的方式示出，且不受附图的限制，在附图中，相同的附图标记表示类似的元件，在图中：
图1为处于半导体制造工艺的第一阶段的晶片的局部横截面图，其中，形成晶体管栅极结构覆盖在半导体衬底上面；
图2示出了图1之后的工艺，在该工艺中，在位于栅结构下面的沟道晶体管区的任一侧上的衬底的源/漏区中形成多个空隙(void)；
图3示出了图2之后回刻隔离结构的工艺，；
图4示出了图3之后生长源/漏半导体的工艺；
图5示出了图4之后在晶体管上方淀积电介质层的工艺；
图6示出了图2之后的工艺，作为图3和图4中示出的工艺的选择，在该工艺中，源/漏空隙由源/漏结构再填充；以及
图7示出了图6之后的工艺，在该工艺中，在形成源/漏结构之后凹陷隔离结构。
本领域的技术人员理解，图中的各元件为了简化和清楚目的而示出，不必按照比例绘制。例如，图中一些元件的尺寸可能相对于其他元件放大，以有助于提高对本发明的实施方式的理解。
具体实施方式
在一个方面中，在此公开的半导体制造工艺包括通过蚀刻半导体衬底的源/漏区中的凹陷形成具有应力源/漏结构的晶体管。回刻与源/漏凹陷相邻的隔离结构，以使得隔离结构和相邻源/漏凹陷之间的重叠小于特定的范围。随后再填充源/漏凹陷，且在整个结构上方淀积应变电介质。通过在应变源/漏区和相邻隔离结构之间具有小的重叠，以及通过淀积应力感应介质层，所描述的工艺能够实现所需的应变增强等级。
现在回到附图，图1为在由附图标记100指示的集成电路的制造中，在中间阶段处半导体晶片101的局部横截面图。如图1所示，晶片101为绝缘体(SOI)晶片上的半导体，其中，半导体层104(也被称作有源层104)设置在隐埋氧化物(BOX)层102上方。晶体管区103包括设置在一对电介质绝缘结构106之间的半导体层104的部分。半导体层104优选地为微掺杂的n型或p型单晶硅。隔离电介质结构106和BOX层为电介质，诸如适当地淀积或热成型的硅氧化物。
已经形成栅结构110覆盖在有源层104中晶体管区103的一部分上面。栅结构110包括导电性栅电极112，覆盖在栅电介质层114上面。设置栅电介质层114，覆盖在有源层104上面，且优选地在有源层104的顶部或者与有源层104接触。间隔(spacer)结构116位于栅电极112的侧壁上。
在类似的实施中，栅电极112为以诸如热分解硅烷的传统方式形成的p型或n型多晶的硅(多晶硅)。在其它实施方式中，栅电极112可以为金属栅电极或其它导电性材料。栅电极114可以为热成型硅氧化膜，诸如氮化硅的“高K”材料，诸如HfO2的各种金属氧化物中的任何一种、或者上述的组合。间隔116类似于诸如氧化硅、氮化硅等的电介质材料。间隔116可以由多层材料构成，诸如氧化硅和氮化硅的组合。
栅结构110的位置限定了有源层104中的沟道区105和一对源/漏区107的近似边界。有源层104内的沟道区105的横向边界与栅电极112的侧壁重合，而源/漏区107包括有源层104的剩余部分。换言之，源/漏区107占用沟道区105和隔离结构106之间的有源层104的部分。
现将参考图2，通过去除半导体层104的源/漏区107(参见图1)的一些部分形成源/漏凹陷120。在优选的实施方式中，通过蚀刻工艺形成源/漏凹陷120，蚀刻工艺可能包括干的或异向性成分、湿的或同向性成分，或者两者的组合。对于有源层104为单晶硅的实施方式，包括诸如Cl2的氯、诸如SF6的氟、或者两者的组合的等离子体可以用于形成源/漏凹陷120。在一个实施方式中，源/漏凹陷120的深度在约30到200nm的范围内。在所述实施方式中，源/漏凹陷120的形成导致间隔结构116的一些凹割。同样，在所述的实施方式中，源/漏凹陷蚀刻工艺相对于隔离结构106具有较高的选择性。
现转到图3，在形成源/漏凹陷120之后，蚀刻图2的隔离结构106的上部或者用其他方法去除以形成凹陷的隔离结构126。在所述的实施方式中，控制用于形成隔离结构126的蚀刻以在所需范围内生成重叠128。
在一个实施方式中，重叠128优选地在约10到30nm的范围。重叠128必须大于0以防止意外的处理，包括有源层104、BOX层102或者两者的蚀刻。
现转到图4，在图3的源/漏凹陷120中形成源/漏结构130。源/漏结构130优选为晶体半导体材料，该晶体半导体材料具有与有源层104的晶格常数不同的晶格常数。对于有源层104为硅的实施方式，当需要可压缩的应激物时，源/漏结构130可以为用于PMOS晶体管的硅锗化合物，或者当需要可拉伸的应激物时，源/漏结构130可以为用于NMOS晶体管的硅碳。在使用硅锗的情况下，硅锗应激物的化合物优选地为Si1 -xGeX，其中，X(锗的百分比)为在约10％到50％的范围内。在使用硅碳的情况下，硅碳应激物的化合物优选地为Si1-xCX，其中，X(碳的百分比)为在约0.5％到5％的范围内。在优选的实施方式中，使用有源层104作为种晶，通过外延生长，实现源/漏结构130的形成。如图4所示，凹陷的隔离结构126的上表面在源/漏结构130的下表面的上方垂直地移位，移位的量为位移或重叠138。在优选的实施方式中，在源/漏结构130形成之前，位移138基本上等于在图2中示出的重叠128。
如图4中所示的集成电路100包括源/漏结构130，具有与有源层104的晶格常数不同的晶格常数，从而向晶体管沟道区105提供压缩或拉伸应力。在这些实施方式中，源/漏结构130指源/漏应激物。那些对于源/漏结构130采用硅锗化合物且对于有源层104采用硅的实施方式在沟道区105上产生压缩应力。这种压缩应力有利地增强了PMOS器件的沟道区105中的载流子迁移率。那些对于源/漏结构130采用硅碳化合物且对于有源层104采用硅的实施方式在沟道区105上产生拉伸应力。这种应力有利地增强了NMOS器件的沟道区105中的载流子迁移率。
可以更改图2、图3和图4中示出的顺序而不会实质上改变生成的集成电路100。例如，尽管所示的顺序在形成源/漏结构130之前形成源/漏空隙120和凹陷的隔离结构126，然而其它实施方式可以在隔离结构106凹陷之前执行源/漏结构130的外延成型。在图6和图7中示出了这种顺序，该顺序为取代如上所述的图3和图4中示出的工艺的工艺顺序。
此外，尽管所示的实施方式采用高选择性的第一蚀刻来蚀刻源/漏区107以形成源/漏空隙120，以及采用高选择性的第二蚀刻来凹陷隔离结构106以形成凹陷的隔离结构126，然而其它实施方式也可以使用介于有源层104和隔离结构106之间的具有中等选择性的蚀刻工艺，其中有源层104的蚀刻率仅仅适度地超过隔离结构106的蚀刻率。在本实施方式中，可以利用单蚀刻处理工序基本上同时形成源/漏空隙120和凹陷的隔离结构126。
现转到图5，电介质层，在此称作层间介质(ILD)应激物层140，毯式地(blanket)淀积以盖住包括凹陷的隔离结构126的晶片101。如图5所示，ILD应激物层140由此接触由凹陷的隔离结构126露出的源/漏结构130的侧壁的一部分。在优选的实施方式中，ILD应激物层140为电介质材料，当淀积在硅上，或与硅相邻时，这种电介质材料固有地应变。对于ILD应激物的应变(即压缩或拉伸)的性质优选地与源/漏应激物的性质相同。因此，ILD应激物层140在集成电路的PMOS区中压缩而在NMOS区中拉伸。在本实施方式中，ILD应激物层140通过接触源/漏结构130的露出的侧壁，向沟道区105提供额外的应变增进。ILD应激物层140可以包括PMOS区中的压缩氮化硅以及NMOS区中的拉伸氮化硅。
通过使ILD应激物层接触源/漏结构130的侧壁，凹陷的隔离结构便于ILD应激物层140与源/漏结构130和晶体管沟道105的最优化的连接。对于晶片的区域，其中具有特殊应变类型的ILD应激物层140是不需要的，ILD应激物层140可以局部地用不同的ILD膜取代，或者可以通过在光刻胶图案下植入来局部地减轻应变。
在前述的说明书中，本发明已经参照具体的实施方式进行了描述。然而，本领域的技术人员理解，可以在不脱离本发明如下所提出的权利要求的范围的情况下进行各种修改和变化。例如，尽管所描述的实施方式采用SOI晶片作为初始材料，然而所描述的工艺也可应用到使用传统、块状硅初始材料的工艺。类似地，尽管所描述的实施示出了具有传统的、单一栅电极的晶体管，然而本发明的非易失性实施方式也可以使用浮栅晶体管技术、毫微晶体栅技术等。相应地，说明书和附图认为是示例性的，而不是限制性的，所有这些修改均应包括在本发明的范围内。
上面已经通过具体实施方式表述了益处、其它优势和问题的解决方案。然而，所述益处、优势、问题的解决方案以及任何可以导致任何益处、优势、或者解决方案出现或者变得更加显著的因素不被解释成任何或所有权利要求的严格的、必须的或者本质的特征或因素。如在此所使用的，术语“包括”、“包含”或者任何其它变形旨在表达“非排他”的含义，这样包括一系列因素的工艺、方法、项目或装置不仅包括这些因素，而且可以包括其它未明确地列出的，或对于这种工艺、方法、项目或装置所固有的因素。
Claims (15)
1.一种半导体制造工艺，包括：
形成第一和第二隔离结构，该第一和第二隔离结构横向设置在半导体层的晶体管区的任一侧上；
形成覆盖在一部分所述晶体管区上面的栅结构，其中，所述栅结构包括覆盖在栅电介质层上面的导电性栅电极，所述栅电介质层覆盖在所述半导体层上面，并且进一步地，其中，所述栅电极的侧壁限定沟道区与源/漏区的边界，所述沟道区位于所述栅结构下面，所述源/漏区在所述沟道区与所述第一和第二隔离结构之间延伸的所述沟道区的任一侧上；
去除所述源/漏区中部分的所述半导体层，以形成源/漏凹陷；
去除所述第一和第二隔离结构的上部，以形成第一和第二凹陷的隔离结构，其中，所述源/漏凹陷的下表面和所述第一和第二凹陷的隔离结构的上表面在所述半导体层的上表面的下方分别垂直地移位，移位的量为第一位移和第二位移，其中，所述第一位移大于所述第二位移；以及
利用源/漏应激物填充所述源/漏凹陷。
2.根据权利要求1所述的半导体制造工艺，其中，形成第一和第二隔离结构的步骤包括：形成第一和第二氧化硅浅沟槽隔离(STI)结构。
3.根据权利要求1所述的半导体制造工艺，其中，所述第一位移超过所述第二位移的位移的范围为10到30nm。
4.根据权利要求1所述的半导体制造工艺，其中，填充所述源/漏凹陷的所述步骤先于形成所述第一和第二凹陷的隔离结构的所述步骤。
5.根据权利要求1所述的半导体制造工艺，其中，形成所述第一和第二凹陷的隔离结构的所述步骤先于填充所述源/漏凹陷的所述步骤。
6.根据权利要求1所述的半导体制造工艺，进一步包括：毯式地淀积层间电介质层(ILD)应激物，其中，所述ILD应激物与所述源/漏应激物的侧壁相邻。
7.根据权利要求6所述的半导体制造工艺，其中，淀积所述ILD应激物的步骤包括：淀积应变的氮化硅。
8.根据权利要求1所述的半导体制造工艺，其中，所述半导体层包括硅，并且其中填充所述源/漏凹陷的步骤包括：外延生长半导体源/漏结构，其中，所述半导体源/漏结构的晶格常数不同于硅的晶格常数。
9.根据权利要求8所述的半导体制造工艺，其中，所述半导体源/漏应激物包括锗含量在10％到50％的范围内的硅锗化合物。
10.根据权利要求9所述的半导体制造工艺，其中，所述半导体源/漏应激物包括碳含量在0.5％到5％的范围内的硅碳化合物。
11.一种集成电路，包括：
第一和第二凹陷的隔离结构，该第一和第二凹陷的隔离结构横向设置在半导体衬底的晶体管区的任一侧上，其中，所述凹陷的隔离结构的上表面低于所述半导体衬底的上表面；
覆盖在部分的所述晶体管区上面的栅结构，其中所述栅结构包括覆盖在栅电介质层上面的导电性栅电极，所述栅电介质层覆盖在所述衬底上面，并且进一步地，其中所述栅结构的侧壁限定沟道区和源漏区的边界，所述沟道区位于所述栅结构下面，所述源漏区在所述沟道区与所述第一和第二凹陷的隔离结构之间延伸的所述沟道区的任一侧上；
位于所述沟道区任一侧上的源/漏应激物，其中，所述源/漏应激物的下表面在所述第一和第二凹陷的隔离结构的上表面下方垂直地移位，移位的量为10到30nm范围内的位移；以及
覆盖在每个所述凹陷隔离结构上面的层间电介质层(ILD)应激物，其中，所述ILD应激物与所述相应源/漏应激物的侧壁相邻。
12.根据权利要求11所述的集成电路，其中，所述第一和第二凹陷的隔离结构包括第一和第二氧化硅浅沟槽隔离(STI)结构。
13.根据权利要求11所述的集成电路，其中，所述层间电介质层(ILD)应激物包括氮化硅。
14.根据权利要求13所述的集成电路，其中，所述半导体衬底包括硅，并且其中所述源/漏凹陷的晶格常数不同于硅的晶格常数。
15.根据权利要求14所述的集成电路，其中，所述源/漏应激物包括选自下述组的材料：所述组包含具有锗含量在10％到50％的范围内的硅锗化合物，以及具有碳含量在0.5％到5％的范围内的硅碳化合物。
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| US7572705B1 (en) * | 2005-09-21 | 2009-08-11 | Advanced Micro Devices, Inc. | Semiconductor device and method of manufacturing a semiconductor device |
| US7323392B2 (en) * | 2006-03-28 | 2008-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance transistor with a highly stressed channel |
| US9209088B2 (en) * | 2007-08-01 | 2015-12-08 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
| US20090289280A1 (en) * | 2008-05-22 | 2009-11-26 | Da Zhang | Method for Making Transistors and the Device Thereof |
| US8003454B2 (en) * | 2008-05-22 | 2011-08-23 | Freescale Semiconductor, Inc. | CMOS process with optimized PMOS and NMOS transistor devices |
| JP5163311B2 (ja) * | 2008-06-26 | 2013-03-13 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
| US8361867B2 (en) * | 2010-03-19 | 2013-01-29 | Acorn Technologies, Inc. | Biaxial strained field effect transistor devices |
| US8470674B2 (en) | 2011-01-03 | 2013-06-25 | International Business Machines Corporation | Structure, method and system for complementary strain fill for integrated circuit chips |
| CN103377941B (zh) * | 2012-04-28 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Pmos晶体管及形成方法 |
| JP5712985B2 (ja) * | 2012-08-27 | 2015-05-07 | ソニー株式会社 | 半導体装置 |
| US8928048B2 (en) * | 2013-01-17 | 2015-01-06 | Globalfoundries Inc. | Methods of forming semiconductor device with self-aligned contact elements and the resulting device |
| KR102277398B1 (ko) * | 2014-09-17 | 2021-07-16 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
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| US7101765B2 (en) * | 2004-03-31 | 2006-09-05 | Intel Corporation | Enhancing strained device performance by use of multi narrow section layout |
| US7413957B2 (en) * | 2004-06-24 | 2008-08-19 | Applied Materials, Inc. | Methods for forming a transistor |
| US20060022264A1 (en) * | 2004-07-30 | 2006-02-02 | Leo Mathew | Method of making a double gate semiconductor device with self-aligned gates and structure thereof |
| US20060030093A1 (en) | 2004-08-06 | 2006-02-09 | Da Zhang | Strained semiconductor devices and method for forming at least a portion thereof |
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