JP2009525622A5 - - Google Patents

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Publication number
JP2009525622A5
JP2009525622A5 JP2008553453A JP2008553453A JP2009525622A5 JP 2009525622 A5 JP2009525622 A5 JP 2009525622A5 JP 2008553453 A JP2008553453 A JP 2008553453A JP 2008553453 A JP2008553453 A JP 2008553453A JP 2009525622 A5 JP2009525622 A5 JP 2009525622A5
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JP
Japan
Prior art keywords
carriers
protective layer
substrate
range
doped
Prior art date
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Application number
JP2008553453A
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English (en)
Japanese (ja)
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JP2009525622A (ja
JP5261194B2 (ja
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Priority claimed from PCT/US2007/061128 external-priority patent/WO2007090055A1/en
Publication of JP2009525622A publication Critical patent/JP2009525622A/ja
Publication of JP2009525622A5 publication Critical patent/JP2009525622A5/ja
Application granted granted Critical
Publication of JP5261194B2 publication Critical patent/JP5261194B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2008553453A 2006-01-31 2007-01-26 高い熱伝導率を有する半導体ウエハ Active JP5261194B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US76364306P 2006-01-31 2006-01-31
US60/763,643 2006-01-31
PCT/US2007/061128 WO2007090055A1 (en) 2006-01-31 2007-01-26 Semiconductor wafer with high thermal conductivity

Publications (3)

Publication Number Publication Date
JP2009525622A JP2009525622A (ja) 2009-07-09
JP2009525622A5 true JP2009525622A5 (enExample) 2010-11-11
JP5261194B2 JP5261194B2 (ja) 2013-08-14

Family

ID=38121741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008553453A Active JP5261194B2 (ja) 2006-01-31 2007-01-26 高い熱伝導率を有する半導体ウエハ

Country Status (8)

Country Link
US (3) US20070176238A1 (enExample)
EP (3) EP2637207A1 (enExample)
JP (1) JP5261194B2 (enExample)
KR (2) KR20080098632A (enExample)
CN (1) CN101410977A (enExample)
MY (1) MY153160A (enExample)
TW (1) TWI429793B (enExample)
WO (1) WO2007090055A1 (enExample)

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US20090050939A1 (en) * 2007-07-17 2009-02-26 Briere Michael A Iii-nitride device
KR20100077363A (ko) * 2008-12-29 2010-07-08 주식회사 동부하이텍 씨모스 이미지 센서의 제조 방법
US7985658B2 (en) * 2009-06-08 2011-07-26 Aptina Imaging Corporation Method of forming substrate for use in imager devices
EP2555244A1 (en) * 2011-08-03 2013-02-06 austriamicrosystems AG A method of producing a photodiode device and a photodiode device comprising an etch stop layer
US8748315B2 (en) * 2012-02-15 2014-06-10 Taiwan Semiconductor Manufacturing Co., Ltd. Condition before TMAH improved device performance
US8956938B2 (en) * 2012-05-16 2015-02-17 International Business Machines Corporation Epitaxial semiconductor resistor with semiconductor structures on same substrate
US9111898B2 (en) * 2013-02-19 2015-08-18 Taiwan Semiconductor Manufacturing Company. Ltd. Multiple layer substrate
CN104064688B (zh) * 2014-07-11 2016-09-21 深圳市华星光电技术有限公司 具有存储电容的tft基板的制作方法及该tft基板
CN112776003B (zh) * 2019-11-07 2022-05-06 台达电子工业股份有限公司 散热装置及其适用的机器人
CN112397570A (zh) * 2020-11-17 2021-02-23 华虹半导体(无锡)有限公司 半导体基底结构及其制作方法
EP4576168A1 (en) * 2023-12-22 2025-06-25 Nexperia B.V. Suppression of auto-doping during epitaxial growth of epitaxy layer in a semiconductor device

Family Cites Families (19)

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US4104090A (en) * 1977-02-24 1978-08-01 International Business Machines Corporation Total dielectric isolation utilizing a combination of reactive ion etching, anodic etching, and thermal oxidation
US4247862B1 (en) * 1977-08-26 1995-12-26 Intel Corp Ionzation resistant mos structure
US4506436A (en) * 1981-12-21 1985-03-26 International Business Machines Corporation Method for increasing the radiation resistance of charge storage semiconductor devices
US4628591A (en) * 1984-10-31 1986-12-16 Texas Instruments Incorporated Method for obtaining full oxide isolation of epitaxial islands in silicon utilizing selective oxidation of porous silicon
JPH0793282B2 (ja) * 1985-04-15 1995-10-09 株式会社日立製作所 半導体装置の製造方法
FR2638892B1 (fr) * 1988-11-09 1992-12-24 Sgs Thomson Microelectronics Procede de modulation de la quantite d'or diffusee dans un substrat de silicium et diode rapide obtenue par ce procede
US5023200A (en) * 1988-11-22 1991-06-11 The United States Of America As Represented By The United States Department Of Energy Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies
US5024723A (en) * 1990-05-07 1991-06-18 Goesele Ulrich M Method of producing a thin silicon on insulator layer by wafer bonding and chemical thinning
JPH07187892A (ja) * 1991-06-28 1995-07-25 Internatl Business Mach Corp <Ibm> シリコン及びその形成方法
JPH06151303A (ja) * 1992-11-11 1994-05-31 Hitachi Ltd 半導体ウエーハの形成方法
US5880010A (en) * 1994-07-12 1999-03-09 Sun Microsystems, Inc. Ultrathin electronics
US5668045A (en) * 1994-11-30 1997-09-16 Sibond, L.L.C. Process for stripping outer edge of BESOI wafers
US5789309A (en) * 1996-12-30 1998-08-04 Memc Electronic Materials, Inc. Method and system for monocrystalline epitaxial deposition
JPH10242153A (ja) * 1997-02-26 1998-09-11 Hitachi Ltd 半導体ウエハ、半導体ウエハの製造方法、半導体装置および半導体装置の製造方法
WO1998042010A1 (en) 1997-03-17 1998-09-24 Genus, Inc. Bonded soi wafers using high energy implant
EP1148544A1 (de) 2000-04-19 2001-10-24 Infineon Technologies AG Verfahren zum Dünnen eines Substrats
JP3785067B2 (ja) * 2001-08-22 2006-06-14 株式会社東芝 半導体素子の製造方法
JP4211696B2 (ja) 2004-06-30 2009-01-21 ソニー株式会社 固体撮像装置の製造方法
DE102004039197B4 (de) * 2004-08-12 2010-06-17 Siltronic Ag Verfahren zur Herstellung von dotierten Halbleiterscheiben aus Silizium

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