US20070176238A1 - Semiconductor wafer with high thermal conductivity - Google Patents

Semiconductor wafer with high thermal conductivity Download PDF

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US20070176238A1
US20070176238A1 US11/698,728 US69872807A US2007176238A1 US 20070176238 A1 US20070176238 A1 US 20070176238A1 US 69872807 A US69872807 A US 69872807A US 2007176238 A1 US2007176238 A1 US 2007176238A1
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carriers
doped
substrate
protective layer
concentration
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Michael Seacrist
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SunEdison Semiconductor Ltd
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/199—Back-illuminated image sensors
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
    • H10F77/148—Shapes of potential barriers

Definitions

  • the present invention generally relates to a semiconductor wafer and a process for making the same. More particularly, the present invention relates to a semiconductor wafer having improved thermal conductivity characteristics, offering advantages when used as a substrate for a high-speed processor device.
  • the overall scaling trend has been to increase the silicon power density by increasing transistor density and operating frequency on processor devices.
  • the power reductions gained from design and process modifications are not sufficient to offset the higher operating temperatures accompanying the increased power density.
  • the semiconductor's electrical performance and reliability is significantly degraded at higher operating temperature, reducing the semiconductor's processor speed and lifespan.
  • the heavily-doped silicon substrate below the device layer is intended to provide protection against many common device failure mechanisms, such as device latch-up failures, failures related to diffusion leakage current, or some radiation event-related failures.
  • latch-up failure refers to an electron-collection phenomenon resulting in a dead short circuit at a parasitic junction, but which can be prevented using, inter alia, strategic doping designs. Therefore, the arrangement of a lightly-doped device layer on a heavily-doped silicon substrate provides desirable latch-up and low diffusion current characteristics.
  • thermal conductivity of lightly-doped silicon has been reported to be about 20% greater than heavily-doped silicon, and possibly even higher. See, e.g., P. Komarov et al., Transient Thermo - Reflectance Measurements of the Thermal Conductivity and Interface Resistance of Metallized Natural and Isotopically - Pure Silicon, 34 Microelectronics Journal No. 12, at 1115-1118 (2003).
  • the difference in thermal conductivity is significant because the majority of heat generated in the thin device layer is transferred to the ambient environment by dissipation through the silicon substrate, and lesser thermal conductivity tends to reduce efficiency and reliability.
  • Backside autodoping i.e., the migration of dopant atoms from the back or sides of the substrate into the device layer, is another problem commonly encountered when a heavily doped substrate is integrated with a lightly doped device layer.
  • One conventional approach to limit this effect is to form a backside oxide seal on the highly doped substrate.
  • the oxide seal can not be integrated into the epitaxial silicon structure in the case of double-side polished wafers.
  • CMOS Image Sensor silicon wafer comprises a substrate that is doped to a P+ or P++ concentration and an epitaxial layer doped to a P concentration.
  • the known use of device-side illumination cannot meet the scaling trends and goals in such applications, which include reducing pixel size and increasing circuit functionality via advanced metal interconnections.
  • Backside illumination is believed to realize these goals, while also improving the device's fill factor and quantum efficiency. These terms are used as different ways to measure the net amount of light energy that is actually able to illuminate the image sensors.
  • Fill factor which refers to the percentage or fraction of the image sensor that is capable of being exposed to light
  • Fill factor is reduced in traditional device-side illumination devices by increasingly complex metallization layers and films, as well as advanced device topography.
  • the quantum efficiency which measures how efficiency projected light is able to generate active electron carriers.
  • backside illumination allows for integration of advanced device architecture and interconnections.
  • backside illumination must be performed within a few microns of the device side photodiode to efficiently convert visible light to electrical signals. This requires consistent and uniform material removal from the backside of the original, as-formed silicon structure to create a smooth backside surface, which requires thinning the silicon structure from several hundred microns to just a few microns, such as less than about 15 ⁇ m.
  • the backside surface must be capable of being passivated against recombination of photon-generated carriers at the surface, while also directing these photon-generated carriers to a collecting photodiode with an electric field within the Image Sensor device.
  • Such features are not readily ascertained using conventional mechanical or chemical means to thin the silicon structure. Mechanical means of thinning may not be feasible with such small dimensions, while controlling chemical removal rates is difficult within the tolerances of the image sensor's physical features.
  • a silicon semiconductor wafer with favorable heat transfer characteristics while providing resistance to common semiconductor failure mechanisms.
  • the present invention is directed to a semiconductor wafer comprising a silicon device layer, a substrate, and a silicon protective layer disposed between the device layer and the substrate.
  • the substrate has a central axis, a front surface, and a back surface that are generally perpendicular to the central axis, a circumferential edge, and a radius extending from the central axis to the circumferential edge.
  • the protective layer has a thickness of at least about 0.5 ⁇ m and is doped, the concentration of the dopant in the protective layer being between about 6.0 ⁇ 10 17 carriers/cm 3 and about 1.0 ⁇ 10 20 carriers/cm 3 .
  • the substrate and the device layer are also doped with the concentration of dopant in the substrate and device layer being less than about 1 ⁇ 10 17 carriers/cm 3 .
  • the present invention is further directed to a process for the preparation of this semiconductor wafer.
  • FIG. 1 is a schematic cross-section of a semiconductor wafer of the invention.
  • FIG. 2 is a schematic top-down view of a semiconductor wafer of the invention, wherein the axis in FIG. 2 is coincident with the axis in FIG. 1 .
  • FIG. 3 is a graphical representation of the carrier concentration profile for an semiconductor wafer having a highly doped protective layer and a lightly doped substrate.
  • FIG. 4 is a graphical representation of the carrier concentration profile for a semiconductor wafer having a lightly doped device layer and a highly doped substrate detailed in Example 1.
  • FIG. 5 is a thermal diagram for heat dissipation under localized heating for a 250 ⁇ m semiconductor wafer having a highly doped substrate.
  • FIG. 6 is a thermal diagram for heat dissipation under localized heating for a 250 ⁇ m semiconductor wafer having a highly doped protective layer and a lightly doped substrate.
  • FIG. 7 is a thermal diagram for heat dissipation under localized heating for a 500 ⁇ m semiconductor wafer having a highly doped substrate.
  • FIG. 8 is a thermal diagram for heat dissipation under localized heating for a 500 ⁇ m semiconductor wafer having a highly doped protective layer and a lightly doped substrate.
  • FIG. 9 is a graph showing the thermal conductivity for multiple semiconductor structures as a function of temperature detailed in Example 2.
  • FIG. 10 is a graphical representation of the carrier concentration profile for a semiconductor wafer for an image sensor application.
  • Semiconductor wafer 1 has a front surface F, a back surface B, and an imaginary central axis A, with the terms “front” and “back” being used in this context merely to distinguish the two major, generally planar surfaces of the wafer.
  • Semiconductor wafer 1 also comprises silicon device layer 3 , silicon protective layer 5 , and substrate 7 .
  • the thermal conductivity of substrate 7 is preferably at least 5% greater than the thermal conductivity of protective layer 5 (at temperatures not in excess of 125° C.). More preferably, the thermal conductivity of substrate 7 is at least 10% greater than the thermal conductivity of protective layer 5 (at temperatures not in excess of 125° C.). For example, in some embodiments, the thermal conductivity of substrate 7 will be at least 15% greater, at least 20% greater, or even at least 25% greater than the thermal conductivity of protective layer 5 at temperatures not in excess of 125° C.
  • semiconductor wafer 1 has an imaginary radius, R, extending from axis A, to edge E of semiconductor wafer 1 .
  • device layer 3 and silicon protective layer 5 extend substantially across the diameter of the wafer. That is, it is generally preferred that device layer 3 and silicon protective layer 5 incorporate and are symmetrically disposed about axis A and extend at least 90% of the length of radius R from the axis to semiconductor wafer edge E. More preferably, device layer 3 and silicon protective layer 5 incorporate and are symmetrically disposed about axis A and extend at least 99% of the length of radius R from the axis to semiconductor wafer edge E.
  • the device layer of the semiconductor wafer (the region of the wafer from a depth of 0 to about 2 ⁇ m) has a dopant concentration of about 1 ⁇ 10 16 atoms/cm 3
  • the silicon protective layer (the region of the wafer from a depth of about 3 to about 5 ⁇ m) has a dopant concentration of 1 ⁇ 10 19 atoms/cm 3
  • the substrate (the region of the wafer at depths greater than about 6 ⁇ m) has a dopant concentration of about 1 ⁇ 10 15 atoms/cm 3 .
  • either P-type or N-type dopants may be employed to dope each of the device layer 32 , the protective layer 33 , and the substrate 34 , when semiconductor materials are selected for the substrate.
  • the substrate comprises a material on which additional layers may be formed and which typically has a thermal conductivity of at least about 120 W/m ⁇ K.
  • the substrate may comprise a single stratum of material, or it may comprise multiple strata.
  • the substrate is sliced from a single crystal silicon ingot grown according to one of the known techniques, such as the Czochralski (“Cz”) or float zone methods. Accordingly, for the purposes of illustration, reference to a single crystal silicon wafer will be utilized hererin. Therefore, in one application, the starting material for the wafer of the present invention is a silicon substrate that has been sliced from a single crystal ingot grown in accordance with Cz crystal growing methods, typically having a nominal diameter of 150 mm, 200 mm, 300 mm, or more.
  • the substrate may be polished or, alternatively, lapped and etched but not polished.
  • Such methods, as well as standard silicon slicing techniques, are disclosed in, e.g., F UMIO S HIMURA , S EMICONDUCTOR S ILICON C RYSTAL T ECHNOLOGY (1989) and SILICON CHEMICAL ETCHING (Josef Grabmaier ed., 1982).
  • the substrates are polished and cleaned by standard methods known to those skilled in the art. See, e.g., H ANDBOOK OF S EMICONDUCTOR S ILICON T ECHNOLOGY (William C. O'Mara et al. eds., 1990).
  • the single crystal silicon substrate is lightly doped such that it is P- or N-silicon, as those designations are conventionally used in the art and described herein. That is, for P-type doping applications, the silicon substrate generally has less than about 1 ⁇ 10 16 carriers/cm 3 , such as less than about 5 ⁇ 10 15 carriers/cm 3 . Furthermore, the substrate typically contains at least about 5 ⁇ 10 14 carriers/cm 3 to minimize undesirable phenomena observed at lower doping levels, such as oxygen-related thermal donor generation. For example, the P-doped single crystal silicon substrate typically has between about 5 ⁇ 10 14 carriers/cm 3 and about 1 ⁇ 10 16 carriers/cm 3 . For N-type doping applications, the silicon substrate generally has less than about 5 ⁇ 10 15 carriers/cm 3 , such as less than about 1 ⁇ 10 15 carriers/cm 3 .
  • the silicon substrate has thermal conductivity of at least about 5% greater than the thermal conductivity of P++ or N++ silicon, as those terms are conventionally used in the art and described herein.
  • doped silicon's thermal conductivity is inversely related to the doping level and the atmospheric temperature; i.e., doped silicon's thermal conductivity decreases as the concentration of dopant and atmospheric temperature increase. Data collected to date suggests that at room temperature, P++ or N++ silicon exhibits a thermal conductivity of less than about 114 W/m ⁇ K. Therefore, the thermal conductivity of the silicon substrate is greater than about 120 W/m ⁇ K. More typically, the silicon substrate's thermal conductivity is greater than about 130 W/m ⁇ K, such as greater than about 135 W/m ⁇ K. In some applications, the thermal conductivity will be greater than about 140 W/m ⁇ K, or even greater than about 150 W/m ⁇ K.
  • the single crystal silicon substrate contains at least one dopant to give the substrate various desirable properties.
  • the substrate may comprise P-type dopants (i.e., elements from Group 3 of the Periodic Table, e.g., boron, aluminum, gallium and indium) or N-type dopants (i.e., elements from Group 5 of the Periodic Table, e.g., phosphorus, arsenic, antimony).
  • P-type dopants i.e., elements from Group 3 of the Periodic Table, e.g., boron, aluminum, gallium and indium
  • N-type dopants i.e., elements from Group 5 of the Periodic Table, e.g., phosphorus, arsenic, antimony.
  • P-type doping the dopant is preferably boron.
  • N-type doping is desired, the dopant is preferably phosphorus.
  • the protective layer typically comprises highly-doped silicon to provide protection against common device failure mechanisms, such as latch-up and low diffusion current failures. Depending on the application, any one of the appropriate P-type or N-type dopants noted above may be used to form the protective layer. Generally, the protective layer typically comprises greater than about 1 ⁇ 10 18 carriers/cm 3 . For example, for P-type doping applications, the highly-doped silicon protective layer comprises between about 1 ⁇ 10 18 carriers/cm 3 and about 1 ⁇ 10 20 carriers/cm 3 .
  • Common ranges include between about 8.5 ⁇ 10 18 carriers/cm 3 and about 2.0 ⁇ 10 19 carriers/cm 3 when the dopant concentration is characterized as P++, and between about 3.2 ⁇ 10 18 carriers/cm 3 and about 8.5 ⁇ 10 18 carriers/cm 3 when the dopant concentration is characterized as P+.
  • the protective layer's dopant concentration is between about 1.0 ⁇ 10 19 carriers/cm 3 and about 1.25 ⁇ 10 19 carriers/cm 3 .
  • the highly-doped silicon protective layer comprises between about 6.0 ⁇ 10 17 carriers/cm 3 and about 5 ⁇ 10 19 carriers/cm 3 .
  • Common ranges include between about 1.2 ⁇ 10 19 carriers/cm 3 and about 3.5 ⁇ 10 19 carriers/cm 3 when the dopant concentration is characterized as N++, and between about 6.0 ⁇ 10 17 carriers/cm 3 and about 4.5 ⁇ 10 18 carriers/cm 3 when the dopant concentration is characterized as N+.
  • the protective layer is characterized by a thermal conductivity lower than the substrate's thermal conductivity. That is, the protective layer is characterized by thermal conductivity of less than about 114 W/m ⁇ K at room temperature. For example, the protective layer is characterized by thermal conductivity of less than about 110 W/m ⁇ K, or even less than about 100 W/m ⁇ K at room temperature.
  • the substrate has a thermal conductivity of greater than about 120 W/m ⁇ K protective layer and the protective layer has a thermal conductivity of less than about 114 W/m ⁇ K.
  • the substrate's thermal conductivity is greater than 130 W/m ⁇ K and the protective layer's thermal conductivity is less than about 114 W/m ⁇ K.
  • the substrate's thermal conductivity is greater than 135 W/m ⁇ K and the protective layer's thermal conductivity is less than about 110 W/m ⁇ K.
  • the resistivity of the protective layer is an alternative way by which the carrier concentration can be estimated.
  • the resistivity of the protective layer is generally between about 2.5 m ⁇ cm and about 25 m ⁇ cm, with common ranges being between about 5 m ⁇ cm and about 10 m ⁇ cm and between about 10 m ⁇ cm and about 20 m ⁇ cm. In one preferred embodiment, the protective layer's resistivity is about 8 m ⁇ cm.
  • the protective layer is thick enough to provide the desired protection, yet as thin as possible to promote heat transfer from the device layer to the high thermal conductivity substrate.
  • the protective layer is at least about 1 ⁇ m thick, such as between about 1 ⁇ m and about 10 ⁇ m thick. More typically, the protective layer will be between about 1 ⁇ m and about 5 ⁇ m thick; and for some applications, the protective layer will be between about 1 ⁇ m and about 3 ⁇ m thick.
  • the protective layer may be formed by using epitaxial deposition, ion implantation, and gas phase doping plus high temperature diffusion.
  • the protective layer may be formed by using epitaxial deposition, ion implantation, and gas phase doping plus high temperature diffusion.
  • An epitaxial layer may be deposited or grown on a surface of the above-described substrate by means generally known in the art, such as the epitaxial growth process described in U.S. Pat. No. 5,789,309.
  • growth of the epitaxial layer is achieved by chemical vapor deposition, because this is one of the most flexible and cost effective methods for growing epitaxial layers on semiconductor material.
  • One advantage to forming the protective layer by epitaxial deposition is that existing epitaxial growth reactors can be used in conjunction with a direct dopant feed during epitaxial growth. For example, when doping the silicon with boron, a high concentration diborane source gas can be mixed with the carrier gas used to dope the epitaxially grown protective layer.
  • ion implantation techniques are used to force dopant atoms into the single crystal silicon substrate.
  • gas phase doping techniques are used to force the dopant atoms into the single crystal silicon substrate. When either an ion implantation or a gas phase doping technique is used, the technique is carried out at an elevated temperature or is followed by a high temperature anneal to diffuse the dopant atoms into the substrate to form the protective layer.
  • the dopant profile created by the transition between the highly-doped protective layer to the lightly-doped substrate also creates an electric field that directs excess charge carriers away from this interface into the substrate.
  • the protective layer By creating an electric field that moves charge carriers away from the protective layer, and therefore away from the device layer, the protective layer also effectively reduces the impact of radiation-induced events or failures.
  • the semiconductor wafer may undergo any suitable epitaxial deposition technique, as described above.
  • the growth is carried out for a time sufficient to form a device layer of desired thickness in an epitaxial growth reactor.
  • the device layer may be doped after the epitaxial layer is grown or in conjunction with its growth.
  • a direct dopant feed may be employed when the device layer is doped during growth; e.g., a diborane source gas can be used when doping the silicon with boron.
  • the dopant level is in accord with conventional silicon device layers, such that it is typically referred to as being P, P-, N, or N-. That is, the device layer typically comprises between about 7.5 ⁇ 10 14 carriers/cm 3 and about 2.5 ⁇ 10 16 carriers/cm 3 .
  • the present invention is utilized to form a P/P+/P ⁇ semiconductor structure; i.e., the invention can be used to form a lightly doped P ⁇ substrate with a highly doped P+ protective layer and an intermediately doped P device layer.
  • a semiconductor structure may be used in applications where backside autodoping is to be avoided, such as, e.g., heavily doped substrates with a lightly doped device layer where an oxide seal is undesirable, as with structures with a double sided polish.
  • the functional equivalent of the P to P+ transition from the device layer to the protective layer is realized, with the added benefit of avoiding the migration of dopant atoms from the backside of the structure to the device layer because of the substrate's lower doping level.
  • the substrate has a dopant level below about 1 ⁇ 10 16 carriers/cm 3
  • the protective P+ layer has a dopant level of between about 3.2 ⁇ 10 18 carriers/cm 3 and about 8.5 ⁇ 10 18 carriers/cm 3
  • the device layer has a dopant level of between about 1 ⁇ 10 14 carriers/cm 3 and about 4 ⁇ 10 16 carriers/cm 3 .
  • the protective layer may also be a P++ layer having between about 8.5 ⁇ 10 18 carriers/cm 3 and about 2.0 ⁇ 10 19 carriers/cm 3 . Furthermore, the protective P+ layer is typically between about 1 ⁇ m and about 10 ⁇ m thick, while the device layer is typically between about 2 ⁇ m and about 5 ⁇ m thick.
  • a P/P++/P ⁇ semiconductor structure formed according to the present invention is useful in the production of thin silicon structures for use in backside illumination applications, such as, e.g., improved CMOS Image Sensor devices.
  • FIG. 16 shows a typical carrier concentration profile for a typical P/P++/P ⁇ semiconductor structure in this application.
  • the back surface of the P ⁇ substrate is exposed to an alkaline etchant for a time period sufficient to remove substantially all of the substrate material and yield a uniformly thinned P/P++ silicon structure with a highly uniform thickness. That is, in this application of the present invention, the highly doped P++ (or even P+++) protective layer acts as an etch stop for alkaline etchants.
  • FIG. 10 graphically shows how the alkaline etchant may be used to remove material to at least the dashed vertical line shown at about 10 ⁇ m, and possibly to remove material to the dashed vertical line shown at about 6 ⁇ m.
  • the etching performed for this application may optionally occur in an electrochemical cell, which would increase the etching rate and facilitate an optional electrochemical passivation step after etching.
  • the P++ surface exposed by the substrate's removal is optionally exposed to an acidic etchant to further thin the P/P++ silicon structure and further smooth the P++ surface.
  • the acidic etchant comprises a solution of hydrofluoric, nitric, and acetic acids (HNA).
  • HNA hydrofluoric, nitric, and acetic acids
  • the substrate has a dopant level below about 1 ⁇ 10 16 carriers/cm 3
  • the protective layer has a dopant level of greater than about 1.0 ⁇ 10 19 carriers/cm 3 , such as between about 1.0 ⁇ 10 19 carriers/cm 3 and about 1.0 ⁇ 10 20 carriers/cm 3 .
  • the protective layer may have between about 5.0 ⁇ 10 19 carriers/cm 3 and about 1.0 ⁇ 10 20 carriers/cm 3 .
  • Silicon doped with such concentrations are commonly referred to as highly doped P++ or even P+++ silicon layers.
  • the thickness of the protective layer is limited in this application, with higher doping concentrations corresponding to thinner protective layers.
  • the protective layer acting as the etch stop is typically less than about 5 ⁇ m thick, such as less than 2 ⁇ m, less than about 1 ⁇ m thick, or even less than about 0.5 ⁇ m thick.
  • the protective layer further comprises Ge to act as a crystal lattice strain reliever, which permits the highly doped protective layer to have greater thicknesses than reported above.
  • the device layer is typically between about 2 ⁇ m and about 15 ⁇ m thick, such as between about 2 ⁇ m and about 10 ⁇ m thick. In one application, the device layer is between about 2 ⁇ m and about 5 ⁇ m thick.
  • the semiconductor wafers having P ⁇ substrates had a carrier concentration profile wherein a device layer having a concentration of about 1 ⁇ 10 16 carriers/cm 3 extended approximately 2 ⁇ m into the wafer, a protective layer having a concentration of about 1 ⁇ 10 19 carriers/cm 3 extended from a depth of about 3 to about 5 ⁇ m into the wafer, and a substrate having a concentration of about 1 ⁇ 10 15 carriers/cm 3 extended from about 6 ⁇ m through the depth of the wafer.
  • the semiconductor wafers having P++ substrates had a carrier concentration profile wherein a device layer having a concentration of about 1 ⁇ 10 16 carriers/cm 3 extended approximately 2 ⁇ m into the wafer and substrate having a concentration of about 1 ⁇ 10 19 carriers/cm 3 extended from about 3 ⁇ m through the depth of the wafer.
  • the doping profiles for each respective type of semiconductor wafer are shown in FIGS. 3 and 4 .
  • Thermal modeling was then performed on wafers depicted in FIGS. 3 and 4 under two conditions: uniform heating and localized hot spots.
  • the simulations were generated using the accepted 20% thermal conductivity difference between lightly-doped P ⁇ and heavily-doped P++ substrates.
  • the two conditions were modeled with power distributed to a 20 mm ⁇ 20 mm grid, representing a theoretical die, which was partitioned into 1 mm ⁇ 1 mm grid squares.
  • an operating power of 160 W was uniformly distributed over the 20 mm ⁇ 20 mm grid.
  • a localized power increase of 10 ⁇ i.e.
  • Table 2 shows that the semiconductor wafer having the P ⁇ substrate more effectively dissipated heat from the local hot spots.
  • the P ⁇ substrate wafer samples resulted in a maximum die temperature approximately 5° C. lower for the 250 ⁇ m sample and 4.4° C. lower for the 500 ⁇ m sample than the maximum die temperatures of the corresponding P++ substrate wafers.
  • Example 2 In addition to the two semiconductor wafers formed in Example 1, seven more semiconductor wafers were formed having different substrates, as detailed below. Apart from Sample 95 below, all the samples were formed according to the CZ growth method.
  • sample 91 the semiconductor wafer formed having a P ⁇ substrate from Example 1
  • sample 92 the semiconductor wafer having a P++ substrate
  • Sample 93 is a semiconductor wafer consisting essentially of P+ material; i.e., material that is doped at a level between that of the invention's protective layer and substrate, such as about 5 ⁇ 10 18 carriers/cm 3 .
  • Sample 94 is a semiconductor wafer consisting essentially of silicon material being doped with both P ⁇ and N ⁇ doping levels; i.e., the material comprised less than about 1 ⁇ 10 16 P-type carriers/cm 3 and less than about 1 ⁇ 10 16 N-type carriers/cm 3 , such as about 1 ⁇ 10 15 carriers/cm 3 of each dopant.
  • Sample 95 is a semiconductor wafer consisting essentially of silicon material formed according to the float zone method and being doped such that it is P ⁇ material, as defined for Sample 94 .
  • Sample 96 is a semiconductor wafer consisting essentially of silicon material being doped such that it is P ⁇ material, as defined for Sample 94 , and having a low concentration of oxygen interstitials.
  • Sample 97 is a semiconductor wafer consisting essentially of silicon material being doped such that it is P ⁇ material, as defined for Sample 94 , and having a high concentration of oxygen interstitials.
  • Sample 98 is a semiconductor wafer structure having a substrate that is doped such that it is P ⁇ material and an epitaxial layer of P ⁇ material formed thereon, as P ⁇ is defined for Sample 94 .
  • the P ⁇ epitaxial layer is about 10 ⁇ m thick.
  • Sample 99 is a semiconductor wafer structure having a substrate that is doped such that it is P ⁇ material and an epitaxial layer of P ⁇ material formed thereon, as P ⁇ is defined for Sample 94 .
  • the P ⁇ epitaxial layer is about 50 ⁇ m thick.
  • Samples 91 - 99 were subjected to thermal conductivity measurements at 25° C., 50° C., 75° C., 100° C., and 125° C. The results are graphically represented in FIG. 15 , which shows the lowest thermal conductivity for Sample 92 and the highest thermal conductivity for Samples 91 and 94 - 99 , regardless of temperature. The fact that Samples 91 and 94 - 99 all displayed substantially similar thermal conductivity profiles indicates that the variables changed between these samples has little impact on their thermal conductivity. Further, Sample 93 displays a thermal conductivity between Sample 92 and the group of Samples 91 and 94 - 99 . This confirms that a silicon structure's doping concentration is the variable with the greatest influence on the thermal conductivity.
  • the data shows about a 23% increase in thermal conductivity at about 25° C. from Sample 92 to Samples 91 and 94 - 99 , while an increase of about 13% corresponds to about 125° C.
  • dopant When the terms “dopant,” “lightly-doped,” “heavily-doped,” or other terms and phrases referring to dopants are used herein, it is to be understood that either P-type or N-type dopants are being referenced, unless explicitly stated otherwise.

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