JP2009260313A - Ｓｏｉ基板の作製方法及び半導体装置の作製方法 - Google Patents

Ｓｏｉ基板の作製方法及び半導体装置の作製方法 Download PDF

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JP2009260313A
JP2009260313A JP2009069508A JP2009069508A JP2009260313A JP 2009260313 A JP2009260313 A JP 2009260313A JP 2009069508 A JP2009069508 A JP 2009069508A JP 2009069508 A JP2009069508 A JP 2009069508A JP 2009260313 A JP2009260313 A JP 2009260313A
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single crystal
semiconductor substrate
crystal semiconductor
substrate
oxide film
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JP2009260313A5 (enExample
Inventor
Shunpei Yamazaki
舜平 山崎
Eriko Nishida
恵里子 西田
Takashi Shimazu
貴志 島津
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Electroluminescent Light Sources (AREA)
JP2009069508A 2008-03-26 2009-03-23 Ｓｏｉ基板の作製方法及び半導体装置の作製方法 Withdrawn JP2009260313A (ja)

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JP2009069508A JP2009260313A (ja) 2008-03-26 2009-03-23 Ｓｏｉ基板の作製方法及び半導体装置の作製方法

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012199762A (ja) * 2011-03-22 2012-10-18 Murata Mfg Co Ltd 圧電デバイスの製造方法
KR20210156817A (ko) * 2018-11-30 2021-12-27 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 무금속 soi 웨이퍼의 제조 방법
JP2022148013A (ja) * 2021-03-24 2022-10-06 株式会社東京精密 シリコンウエハの表面改質方法

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JP2009260315A (ja) * 2008-03-26 2009-11-05 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法及び半導体装置の作製方法
JP5654206B2 (ja) * 2008-03-26 2015-01-14 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法及び該ｓｏｉ基板を用いた半導体装置
US9190294B2 (en) * 2012-08-23 2015-11-17 Michael Xiaoxuan Yang Methods and apparatus for separating a substrate
CN106409650B (zh) * 2015-08-03 2019-01-29 沈阳硅基科技有限公司 一种硅片直接键合方法
DE102016112139B3 (de) * 2016-07-01 2018-01-04 Infineon Technologies Ag Verfahren zum Reduzieren einer Verunreinigungskonzentration in einem Halbleiterkörper
US11232976B2 (en) 2017-07-20 2022-01-25 National Research Council Of Canada Treating a silicon on insulator wafer in preparation for manufacturing an atomistic electronic device interfaced with a CMOS electronic device

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KR101440930B1 (ko) * 2007-04-20 2014-09-15 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Ｓｏｉ 기판의 제작방법
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JPS56103425A (en) * 1980-01-21 1981-08-18 Nippon Telegr & Teleph Corp <Ntt> Improving method for semiconductor substrate
JPH0254532A (ja) * 1988-08-17 1990-02-23 Sony Corp Ｓｏｉ基板の製造方法
JPH0456223A (ja) * 1990-06-25 1992-02-24 Matsushita Electron Corp シリコン酸化膜の形成方法および薄膜形成装置
JP2000036583A (ja) * 1998-05-15 2000-02-02 Canon Inc 半導体基板、半導体薄膜の作製方法および多層構造体
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WO2007142852A2 (en) * 2006-05-31 2007-12-13 Corning Incorporated Producing soi structure using ion shower

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012199762A (ja) * 2011-03-22 2012-10-18 Murata Mfg Co Ltd 圧電デバイスの製造方法
KR20210156817A (ko) * 2018-11-30 2021-12-27 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 무금속 soi 웨이퍼의 제조 방법
KR102407399B1 (ko) 2018-11-30 2022-06-10 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 무금속 soi 웨이퍼의 제조 방법
JP2022148013A (ja) * 2021-03-24 2022-10-06 株式会社東京精密 シリコンウエハの表面改質方法
JP7596191B2 (ja) 2021-03-24 2024-12-09 株式会社東京精密 シリコンウエハの表面改質方法

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Publication number Publication date
US9633892B2 (en) 2017-04-25
JP2014179643A (ja) 2014-09-25
JP2016119490A (ja) 2016-06-30
JP6154926B2 (ja) 2017-06-28
US20090246936A1 (en) 2009-10-01

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