JP5063066B2 - 半導体装置の作製方法 - Google Patents
半導体装置の作製方法 Download PDFInfo
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- JP5063066B2 JP5063066B2 JP2006262010A JP2006262010A JP5063066B2 JP 5063066 B2 JP5063066 B2 JP 5063066B2 JP 2006262010 A JP2006262010 A JP 2006262010A JP 2006262010 A JP2006262010 A JP 2006262010A JP 5063066 B2 JP5063066 B2 JP 5063066B2
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Description
本実施の形態では、本発明の半導体装置の作製方法の一例に関して図面を参照して説明する。
本実施の形態では、上記実施の形態とは異なる半導体装置の作製方法に関して図面を参照して説明する。具体的には、薄膜トランジスタ、記憶素子およびアンテナを含む本発明の半導体装置の作製方法について、図面を参照して説明する。
本実施の形態では、上記実施の形態で示した作製方法を用いて得られた半導体装置の使用形態の一例について説明する。具体的には、非接触でデータのやりとりが可能である半導体装置の適用例に関して図面を参照して以下に説明する。非接触でデータのやりとりが可能である半導体装置は利用の形態によっては、RFID(Radio Frequency Identification)タグ、IDタグ、ICタグ、ICチップ、RFタグ(Radio Frequency)、無線タグ、電子タグまたは無線チップともよばれる。
本実施の形態では、上記実施の形態で示した作製方法を用いて得られた半導体装置の使用形態の一例について説明する。具体的には、表示手段を有する半導体装置に関して図面を参照して説明する。
102 素子群
103 絶縁膜
104 開口部
105 フィルム
106 基板
107 薄膜手段
108 薬液
109 フィルム
110 素子形成層
111 クラック
201 基板
202 絶縁膜
203 半導体膜
203a 半導体膜
203b 半導体膜
203c 半導体膜
203d 半導体膜
203e 半導体膜
203f 半導体膜
204 ゲート絶縁膜
205 ゲート電極
206 N型不純物領域
207 P型不純物領域
208 絶縁膜
209a 第1のN型不純物領域
209b 第2のN型不純物領域
210 絶縁膜
211 絶縁膜
212 絶縁膜
213 絶縁膜
214 導電膜
215 絶縁膜
216a 導電膜
216b 導電膜
216c 導電膜
216d 導電膜
217 絶縁膜
218 導電膜
219 有機化合物層
220 導電膜
221 絶縁膜
222 フィルム
224 基板
225 フィルム
230a 薄膜トランジスタ
230b 薄膜トランジスタ
230c 薄膜トランジスタ
230d 薄膜トランジスタ
230e 薄膜トランジスタ
230f 薄膜トランジスタ
231a 記憶素子部
231b 記憶素子部
233 素子形成層
241 ステージ
243 ローラー
80 半導体装置
81 高周波回路
82 電源回路
83 リセット回路
84 クロック発生回路
85 データ復調回路
86 データ変調回路
87 制御回路
88 記憶回路
89 アンテナ
91 コード抽出回路
92 コード判定回路
93 CRC判定回路
94 出力ユニット回路
3210 表示部
3200 リーダ/ライタ
3220 品物
3230 半導体装置
3250 半導体装置
3260 商品
502 走査線駆動回路
503 信号線駆動回路
504 画素部
510a 薄膜トランジスタ
510b 薄膜トランジスタ
511 薄膜トランジスタ
513 第1の電極
514 発光層
515 第2の電極
516 発光素子
521 配向膜
522 液晶
523 配向膜
524 第2の電極
525 スペーサ
4101 本体
4102 支持台
4103 表示部
4201 本体
4202 表示部
4401 本体
4402 表示部
4403 キーボード
4404 タッチパッド
4405 外部接続ポート
4406 電源プラグ
4300 本体
4301 キーボード
4302 表示部
4303 スピーカー
4501 本体
4502 表示部
4503 操作キー
4601 本体
4602 表示部
4603 接続端子
Claims (11)
- 基板の一方の面上に複数の素子群を形成し、
前記複数の素子群を覆うように絶縁膜を形成し、
前記複数の素子群において隣り合う2つの素子群間の領域に設けられた前記絶縁膜に開口部を選択的に形成して前記基板を露出させ、
前記絶縁膜および前記開口部を覆うように第1のフィルムを設け、
前記基板を除去して前記素子群を露出させ、
前記露出した素子群の表面を覆うように第2のフィルムを設け、
前記絶縁膜が露出しないように前記複数の素子群の間を切断することを特徴とする半導体装置の作製方法。 - 基板の一方の面上に下地膜を形成し、
前記下地膜上に複数の素子群を形成し、
前記複数の素子群を覆うように絶縁膜を形成し、
前記複数の素子群において隣り合う2つの素子群間の領域に設けられた前記絶縁膜に開口部を選択的に形成して前記基板または前記下地膜を露出させ、
前記絶縁膜および前記開口部を覆うように第1のフィルムを設け、
前記基板を除去して前記下地膜を露出させ、
前記露出した下地膜の表面を覆うように第2のフィルムを設け、
前記絶縁膜が露出しないように前記複数の素子群の間を切断することを特徴とする半導体装置の作製方法。 - 基板の一方の面上に複数の素子群を形成し、
前記複数の素子群を覆うように絶縁膜を形成し、
前記複数の素子群において隣り合う2つの素子群間の領域に設けられた前記絶縁膜に開口部を選択的に形成して前記基板を露出させ、
前記絶縁膜および前記開口部を覆うように第1のフィルムを設け、
前記基板の他方の面から前記基板を薄膜化し、
前記薄膜化した基板を化学反応処理により除去して前記素子群を露出させ、
前記露出した素子群の表面を覆うように第2のフィルムを設け、
前記絶縁膜が露出しないように前記複数の素子群の間を切断することを特徴とする半導体装置の作製方法。 - 基板の一方の面上に下地膜を形成し、
前記下地膜上に複数の素子群を形成し、
前記複数の素子群を覆うように絶縁膜を形成し、
前記複数の素子群において隣り合う2つの素子群間の領域に設けられた前記絶縁膜に開口部を選択的に形成して前記基板または前記下地膜を露出させ、
前記絶縁膜および前記開口部を覆うように第1のフィルムを設け、
前記基板の他方の面から前記基板を薄膜化し、
前記薄膜化した基板を化学反応処理により除去して前記下地膜を露出させ、
前記露出した下地膜の表面を覆うように第2のフィルムを設け、
前記絶縁膜が露出しないように前記複数の素子群の間を切断することを特徴とする半導体装置の作製方法。 - 請求項3または請求項4において、
前記基板の薄膜化は、研削処理、研磨処理の一方または両方により行うことを特徴とする半導体装置の作製方法。 - 請求項3乃至請求項5のいずれか一項において、
前記化学反応処理は、前記薄膜化した基板を薬液に浸すことにより行うことを特徴とする半導体装置の作製方法。 - 請求項2または請求項4において、
前記下地膜を、窒化物で形成することを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項7のいずれか一項において、
前記開口部は、レーザ光を照射することにより形成することを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項8のいずれか一項において、
前記基板として、ガラス基板を用いることを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項9のいずれか一項において、
前記第1のフィルムの材料として、前記絶縁膜の材料より弾性率が低い材料を用いることを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項10のいずれか一項において、
前記第1のフィルムの材料として、ポリプロピレン、ポリエステル、ビニル、ポリフッ化ビニル、又はポリ塩化ビニルを用い、
前記第2のフィルムの材料として、ポリプロピレン、ポリエステル、ビニル、ポリフッ化ビニル、又はポリ塩化ビニルを用いることを特徴とする半導体装置の作製方法。
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