JP2009176978A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2009176978A
JP2009176978A JP2008014441A JP2008014441A JP2009176978A JP 2009176978 A JP2009176978 A JP 2009176978A JP 2008014441 A JP2008014441 A JP 2008014441A JP 2008014441 A JP2008014441 A JP 2008014441A JP 2009176978 A JP2009176978 A JP 2009176978A
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Japan
Prior art keywords
semiconductor chip
integrated circuit
semiconductor
semiconductor device
main surface
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JP2008014441A
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English (en)
Japanese (ja)
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JP2009176978A5 (https=
Inventor
Hiroyuki Shinkai
寛之 新開
Hiromori Okumura
弘守 奥村
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2008014441A priority Critical patent/JP2009176978A/ja
Priority to US12/357,516 priority patent/US20090206466A1/en
Publication of JP2009176978A publication Critical patent/JP2009176978A/ja
Publication of JP2009176978A5 publication Critical patent/JP2009176978A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/656—Fan-in layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01223—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in liquid form, e.g. by dispensing droplets or by screen printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01257—Changing the shapes of bumps by reflowing
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01931—Manufacture or treatment of bond pads using blanket deposition
    • H10W72/01933—Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01935—Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01951—Changing the shapes of bond pads
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
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    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
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    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/733—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between laterally-adjacent chips

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2008014441A 2008-01-25 2008-01-25 半導体装置 Pending JP2009176978A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008014441A JP2009176978A (ja) 2008-01-25 2008-01-25 半導体装置
US12/357,516 US20090206466A1 (en) 2008-01-25 2009-01-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008014441A JP2009176978A (ja) 2008-01-25 2008-01-25 半導体装置

Publications (2)

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JP2009176978A true JP2009176978A (ja) 2009-08-06
JP2009176978A5 JP2009176978A5 (https=) 2011-01-27

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JP2008014441A Pending JP2009176978A (ja) 2008-01-25 2008-01-25 半導体装置

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US (1) US20090206466A1 (https=)
JP (1) JP2009176978A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017504212A (ja) * 2014-01-21 2017-02-02 クアルコム，インコーポレイテッド 集積デバイスの再配線層内の環状インダクタ

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103545226B (zh) * 2012-07-09 2016-01-13 万国半导体(开曼)股份有限公司 一种晶圆级半导体器件及其封装方法
TWI470688B (zh) * 2012-07-18 2015-01-21 Alpha & Omega Semiconductor Cayman Ltd 晶圓級半導體裝置及其封裝方法
US8846452B2 (en) 2012-08-21 2014-09-30 Infineon Technologies Ag Semiconductor device package and methods of packaging thereof
CN107768317A (zh) * 2016-08-18 2018-03-06 苏州迈瑞微电子有限公司 一种低剖面多芯片封装结构及其制造方法
CN109761186A (zh) * 2018-12-29 2019-05-17 华进半导体封装先导技术研发中心有限公司 一种薄型三维集成封装方法及结构
CN109795976A (zh) * 2018-12-29 2019-05-24 华进半导体封装先导技术研发中心有限公司 超薄型三维集成封装方法及结构
CN111048503A (zh) * 2019-12-27 2020-04-21 华天科技（昆山）电子有限公司 一种内埋芯片的扇出型封装方法以及封装结构

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02229454A (ja) * 1989-03-02 1990-09-12 Nippon Soken Inc 半導体装置
JPH11121507A (ja) * 1997-10-08 1999-04-30 Oki Electric Ind Co Ltd 半導体装置およびその製造方法
JP2001144213A (ja) * 1999-11-16 2001-05-25 Hitachi Ltd 半導体装置の製造方法および半導体装置
JP2006054310A (ja) * 2004-08-11 2006-02-23 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004214258A (ja) * 2002-12-27 2004-07-29 Renesas Technology Corp 半導体モジュール
TWI278947B (en) * 2004-01-13 2007-04-11 Samsung Electronics Co Ltd A multi-chip package, a semiconductor device used therein and manufacturing method thereof
JP2006210402A (ja) * 2005-01-25 2006-08-10 Matsushita Electric Ind Co Ltd 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02229454A (ja) * 1989-03-02 1990-09-12 Nippon Soken Inc 半導体装置
JPH11121507A (ja) * 1997-10-08 1999-04-30 Oki Electric Ind Co Ltd 半導体装置およびその製造方法
JP2001144213A (ja) * 1999-11-16 2001-05-25 Hitachi Ltd 半導体装置の製造方法および半導体装置
JP2006054310A (ja) * 2004-08-11 2006-02-23 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017504212A (ja) * 2014-01-21 2017-02-02 クアルコム，インコーポレイテッド 集積デバイスの再配線層内の環状インダクタ

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