JP2009105405A - 電界緩和プレートを有する高電子移動度トランジスタ半導体デバイスおよびその製造方法 - Google Patents
電界緩和プレートを有する高電子移動度トランジスタ半導体デバイスおよびその製造方法 Download PDFInfo
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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Abstract
【解決手段】 半導体デバイスは、チャネル層及びショットキーコンタクトを形成するため、バリア層上においてドレイン領域とソース領域との間に配設されるTゲートを含む。第1の不活性電界緩和プレートは、Tゲートの一部の上に配設され、第2の活性フィールドプレートは、バリア層上においてTゲートの近傍に配設される。
【選択図】 図2
Description
Claims (15)
- ソース領域とドレイン領域とTゲートとを含む半導体基板上に半導体デバイスを形成する方法であって、
前記半導体基板上にレジスト層を形成するステップと、
前記レジスト層に窓を形成するステップと、
指向性堆積技術によって、前記窓内および前記レジスト層上に金属膜を堆積するステップと、
前記レジスト層をリフトオフすることにより、前記Tゲートの一部の上に配設される第1フィールドプレートと、前記半導体基板上において前記Tゲートの近傍に配設される第2フィールドプレートとを形成するステップと
を含む方法。 - 請求項1記載の方法は、更に、
前記半導体基板上に前記レジスト層を形成する前に、前記Tゲート上、ならびに前記Tゲートと前記ソース領域との間および前記Tゲートと前記ドレイン領域との間の表面領域上に、誘電体層を形成するステップを含む方法。 - 請求項1記載の方法は、更に、
指向性堆積技術によって前記窓内に前記金属膜を堆積するステップが、前記第2フィールドプレートと前記第1フィールドプレートとを不連続にすべく前記Tゲートの翼を遮断点として利用するステップを含む方法。 - 請求項1記載の方法は、更に、
前記レジスト層に前記窓を形成するステップが、電子ビームリソグラフィ(EBL)またはステッパリソグラフィのいずれかによって前記窓を形成するステップを含む方法。 - 請求項1記載の方法は、更に、
前記金属膜を堆積しかつ前記レジスト層をリフトオフして前記第1および第2のフィールドプレートを形成するステップが、前記第2フィールドプレートをその側長が約0.10〜0.20ミクロンの範囲になるように形成するステップを含む方法。 - 請求項1記載の方法は、更に、
前記金属膜を堆積しかつ前記レジスト層をリフトオフして前記第1および第2のフィールドプレートを形成するステップが、前記第1フィールドプレートを電気的に不活性にするように形成するステップと、前記第2フィールドプレートを前記ソース領域及び前記Tゲートのいずれかに電気的に接続するように形成するステップとを含む方法。 - 請求項1記載の方法は、更に、
前記金属膜を堆積しかつ前記レジスト層をリフトオフして前記第1および第2のフィールドプレートを形成するステップが、前記半導体デバイスのピーク電界を小さくするように前記第2フィールドプレートを構成するステップを含む方法。 - 半絶縁性基板と、
前記半絶縁性基板上に配設されるチャネル層と、
前記チャネル層上に配設され、前記チャネル層との間の界面に2DEG層を含むバリア層と、
前記バリア層を介して前記2DEG層との低抵抗接続を形成するため前記バリア層上に配設されるソース領域およびドレイン領域と、
前記2DEG層とのショットキーコンタクトを形成するため前記バリア層上において前記ソース領域と前記ドレイン領域との間に配設されるTゲートと、
前記Tゲートの一部の上に配設される第1フィールドプレートと、
前記バリア層上において前記Tゲートの近傍に配設される第2フィールドプレートと
を備える半導体デバイス。 - 請求項8記載の半導体デバイスにおいて、
前記第2フィールドプレートは、前記ソース領域及び前記Tゲートのいずれかに接続されている半導体デバイス。 - 請求項8記載の半導体デバイスは、更に、
前記ソース領域と前記Tゲートとの間および前記ドレイン領域と前記Tゲートとの間の前記バリア層の部分と、前記Tゲートとを覆う誘電体層を備え、
前記第1および第2のフィールドプレートが前記誘電体層上に配設されている半導体デバイス。 - 請求項10記載の半導体デバイスにおいて、
前記誘電体層が窒化珪素(SiN)からなる半導体デバイス。 - 請求項8記載の半導体デバイスにおいて、
前記第2フィールドプレートの側長が0.15μm〜0.20μmである半導体デバイス。 - 半導体基板上に半導体デバイスを形成する方法であって、
前記半導体基板は、半絶縁性基板と、前記半絶縁性基板上に配設されるチャネル層と、前記チャネル層上に配設され、前記チャネル層との間の界面に2DEG層を含むバリア層と、前記バリア層上配設され、開口部分を含むように全部または一部がエッチングされる第1誘電体層とを含み、前記開口部分では前記バリア層上にソース領域およびドレイン領域が配設され、前記ソース領域と前記ドレイン領域との間にはTゲートが配設される方法において、
前記第1誘電体層および前記Tゲートを第2誘電体材料により覆うことにより、第2誘電体層を形成するステップと、
前記第2誘電体層上にレジスト層を形成するステップと、
前記レジスト層に窓を形成するステップと、
指向性堆積技術によって、前記窓および前記レジスト層に金属膜を堆積するステップと、
前記レジスト層をリフトオフして、前記Tゲートの一部の上に配設される第1フィールドプレートと、前記第2誘電体層上において前記Tゲートの近傍に配設される第2フィールドプレートとを形成するステップと
を含む方法。 - 請求項13記載の方法は、更に、
前記第1誘電体層を形成するステップが、分子ビームエピタキシーによって、前記第1誘電体材料を3nm〜25nmの厚さにまで成長させるステップを含む方法。 - 請求項13記載の方法は、更に、
前記第2誘電体層を形成するステップが、プラズマ化学気相成長法(PECVD)により、前記第2誘電体材料として窒化珪素(SiN)を堆積するステップを含む方法。
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Cited By (2)
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JP2011210754A (ja) * | 2010-03-27 | 2011-10-20 | Nec Corp | 電界効果トランジスタ、電界効果トランジスタの製造方法、および電子装置 |
JP7156586B1 (ja) * | 2022-03-17 | 2022-10-19 | 三菱電機株式会社 | 半導体装置の製造方法 |
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US8431962B2 (en) * | 2007-12-07 | 2013-04-30 | Northrop Grumman Systems Corporation | Composite passivation process for nitride FET |
US8754496B2 (en) * | 2009-04-14 | 2014-06-17 | Triquint Semiconductor, Inc. | Field effect transistor having a plurality of field plates |
KR101632314B1 (ko) | 2009-09-11 | 2016-06-22 | 삼성전자주식회사 | 전계 효과형 반도체 소자 및 그 제조 방법 |
US8541817B2 (en) * | 2009-11-06 | 2013-09-24 | Nitek, Inc. | Multilayer barrier III-nitride transistor for high voltage electronics |
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