WO2023205936A1 - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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Publication number
WO2023205936A1
WO2023205936A1 PCT/CN2022/088735 CN2022088735W WO2023205936A1 WO 2023205936 A1 WO2023205936 A1 WO 2023205936A1 CN 2022088735 W CN2022088735 W CN 2022088735W WO 2023205936 A1 WO2023205936 A1 WO 2023205936A1
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dielectric layer
region
substrate
gate electrode
area
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PCT/CN2022/088735
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English (en)
French (fr)
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汤岑
饶进
刘涛
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华为技术有限公司
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Priority to PCT/CN2022/088735 priority Critical patent/WO2023205936A1/zh
Publication of WO2023205936A1 publication Critical patent/WO2023205936A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor

Definitions

  • the present disclosure relates to the field of semiconductor device preparation, and in particular to a semiconductor device with high gain and a preparation method thereof.
  • the first generation of semiconductor materials refers to silicon (Si) and germanium (Ge);
  • the second generation of semiconductor materials refers to compound semiconductor materials, such as gallium arsenide (GaAs) and indium antimonide (InSb) et al.
  • GaAs gallium arsenide
  • InSb indium antimonide
  • third-generation compound semiconductor materials represented by gallium nitride (GaN) and silicon carbide (SiC) have received widespread attention due to their excellent material properties.
  • gallium nitride-based devices are widely used in the field of radio frequency devices due to their advantages such as high mobility, strong breakdown resistance and good heat dissipation characteristics.
  • Common RF gallium nitride devices use source short-circuit field plate technology to modulate the electric field and capacitance distribution between gate and drain, thereby achieving specific high-frequency gain indicators.
  • source short-circuit field plate technology to modulate the electric field and capacitance distribution between gate and drain, thereby achieving specific high-frequency gain indicators.
  • gallium nitride semiconductor devices based on the traditional structure of gallium nitride semiconductor devices in the current industry, there is a problem of insufficient room for gain improvement.
  • the present disclosure relates to technical solutions related to semiconductor devices, and specifically provides a semiconductor device and a manufacturing method thereof.
  • a semiconductor device in a first aspect of the present disclosure, includes a substrate having a first region, a second region and a third region on a surface thereof; a first dielectric layer applied to the first region and the third region of the substrate; a gate electrode, coupled to the substrate, including a gate cap region spaced from the first region of the substrate via the first dielectric layer and a contact region in contact with the second region of the substrate open a first spacing; a second dielectric layer is applied outside the gate electrode and the first dielectric layer; in the third region, the second dielectric layer is spaced apart from the substrate by a second spacing; the third dielectric layer is spaced apart from the substrate by a second spacing.
  • the second distance is smaller than the first distance.
  • the capacitance of the parasitic capacitance can be reduced without changing other design structures, thereby improving the Gain characteristics of semiconductor devices at high frequencies.
  • the difference between the first spacing and the second spacing is between 20 nm and 500 nm.
  • the above range provides flexibility in semiconductor device preparation according to different needs.
  • the heating component further includes: the first dielectric layer includes: a uniform thickness layer arranged in the first area and the third area; and a thickened dielectric layer arranged in the uniform thickness layer. between the thickness layer and the first region or between the uniform thickness layer and the gate cap region, and the thickness of the thickened dielectric layer is between 20 nm and 500 nm.
  • the uniform thickness layer and the thickened dielectric layer can be made of the same or different materials. On the one hand, this can improve the flexibility of fabricating semiconductor devices. On the other hand, cost and reliability can also be taken into consideration in the process of preparing semiconductor devices.
  • the semiconductor device further includes a field plate that is locally applied outside the second dielectric layer, a spacing between the field plate and the gate electrode and a distance between the field plate and the third dielectric layer.
  • the spacing between dielectric layers is basically the same.
  • the substrate includes one of the following materials: silicon carbide, gallium nitride, gallium nitride on silicon carbide, gallium nitride on sapphire, gallium nitride on silicon, aluminum indium nitride, aluminum nitride.
  • silicon carbide gallium nitride, gallium nitride on silicon carbide, gallium nitride on sapphire, gallium nitride on silicon, aluminum indium nitride, aluminum nitride.
  • the first dielectric layer or the second dielectric layer includes at least one of the following materials: silicon nitride, silicon oxynitride, silicon dioxide, aluminum nitride, aluminum oxide, and titanium dioxide.
  • silicon nitride silicon oxynitride
  • silicon dioxide silicon dioxide
  • aluminum nitride aluminum oxide
  • titanium dioxide titanium dioxide
  • a method of manufacturing a semiconductor device includes providing a substrate, a surface of which includes a first region corresponding to a gate cap region of a gate electrode of the semiconductor device, a second region corresponding to a contact region of the gate electrode, and a surface other than the first region and a third area outside the second area; applying a first dielectric layer in the first area and the third area; applying a gate electrode so that the contact area contacts the substrate, and the gate a cap region spaced apart from the substrate by a first spacing; and applying a second dielectric layer outside the gate electrode and the first dielectric layer, the second dielectric layer being spaced apart from the substrate in the third region A second distance is smaller than the first distance.
  • the method further includes locally applying a field plate outside the second dielectric layer, with a spacing between the field plate and the gate electrode and a distance between the field plate and the first dielectric layer.
  • the spacing between them is basically the same. In this way, the prepared semiconductor device can have the required high-frequency gain index.
  • applying the first dielectric layer includes applying a thickened dielectric layer in the first region and the second region; applying a uniform thickness layer outside the third region and the thickened dielectric layer. ; and removing the blanket layer and the thickened dielectric layer outside the second area to expose the second area of the substrate.
  • applying the thickened dielectric layer includes applying the thickened dielectric layer over the entire substrate; removing the thickened dielectric layer outside the third region to expose the third region of the substrate .
  • applying a thickened dielectric layer includes applying a photoresist on the third region of the substrate; and on the first and second regions of the substrate and outside the photoresist. A thickened dielectric layer is applied; photoresist is removed to expose the third region of the substrate.
  • applying the first dielectric layer and applying the gate electrode includes applying the uniform thickness layer outside the entire substrate; applying the thickened dielectric layer outside the uniform thickness layer; and removing the the blanket layer and the thickened dielectric layer outside the second area to expose the second area of the substrate; apply a gate electrode; and remove the third area using the gate electrode as a self-aligned mask The thickened dielectric layer outside.
  • applying the first dielectric layer and applying the gate electrode includes applying the first dielectric layer over the entire substrate, the first dielectric layer having a first thickness equal to the first spacing; removing the first dielectric layer outside the second area to expose the second area of the substrate; applying a gate electrode; and using the gate electrode as a self-aligned mask to remove the A portion of the first dielectric layer outside the third area in the thickness direction, so that the first dielectric layer at the third area has a second thickness smaller than the first thickness, and the second thickness is equal to the second spacing.
  • Figure 1 shows a schematic structural diagram of a semiconductor device in a traditional solution in an exemplary manner
  • FIG. 2 shows a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure
  • FIG. 3 shows a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.
  • the term “includes” and similar expressions shall be understood to be open-ended, ie, “including, but not limited to.”
  • the term “based on” should be understood to mean “based at least in part on.”
  • the terms “one embodiment” or “the embodiment” should be understood to mean “at least one embodiment”.
  • the terms “first”, “second”, etc. may refer to different or the same objects and are used only to distinguish the objects referred to and do not imply a specific spatial order, temporal order, importance of the objects referred to. Sexual order, etc.
  • circuit refers to one or more of: (a) a hardware circuit implementation only (such as an implementation of analog and/or digital circuits only); and (b) a combination of hardware circuitry and software, Such as, if applicable: (i) a combination of analog and/or digital hardware circuitry with software/firmware, and (ii) any part of a hardware processor with software (including working together to enable a device, such as a communications device or other electronic device etc., digital signal processors, software and memory that perform various functions); and (c) hardware circuitry and/or processors, such as microprocessors or portions of microprocessors that require software (e.g., firmware) for operation , but can be without software when it is not required for operation.
  • software e.g., firmware
  • circuitry as used herein also covers implementations of only a hardware circuit or processor (or processors), or a portion of a hardware circuit or processor, or accompanying software or firmware.
  • circuit also covers baseband integrated circuits or similar integrated circuits in processor integrated circuits, network equipment, terminal equipment or other equipment.
  • gallium nitride semiconductor devices For some semiconductor devices, such as gallium nitride semiconductor devices, they are widely used in the field of radio frequency devices due to their advantages such as high mobility, strong breakdown resistance and good heat dissipation characteristics.
  • this kind of semiconductor device there are high requirements for gain characteristics at high frequencies.
  • the gain characteristics at high frequencies mainly depend on whether the parasitic capacitance can follow the signal for efficient and fast charging and discharging under high-frequency conditions.
  • the industry usually modulates the channel capacitance under the bias voltage by changing the passivation layer under the field plate metal, thereby reducing the output capacitance value.
  • a radio frequency gallium nitride device is taken as an example of a semiconductor device mentioned in this application to describe some problems in the traditional solution. It should be understood that, in addition to radio frequency gallium nitride devices, the semiconductor devices mentioned in this article can also be any other appropriate semiconductor devices, which will not be described separately below.
  • Figure 1 shows a common common radio frequency gallium nitride semiconductor device. This semiconductor device uses source short-circuit field plate technology. In the traditional solution, the electric field and capacitance distribution between gate and drain are modulated to achieve specific high-frequency gain indicators. As shown in FIG.
  • a traditional semiconductor device generally includes a substrate 501 , a first dielectric layer 502 , a gate electrode 503 , a second dielectric layer 504 and a short field plate 505 .
  • the gate electrode 503 and the field plate 505 are formed of metallic materials. In this semiconductor device, it is usually necessary to adjust the three capacitors C1, C2 and C3 to optimize the gain index.
  • C1 represents the intrinsic capacitance of the gate-drain electrode, and its determining factor is the length of the gate electrode.
  • C2 represents the gate cap-drain parasitic capacitance, which is determined by the gate cap length of the gate electrode 503, the thickness of the first dielectric layer 502 (ie, the distance between the gate cap and the substrate 501), and the thickness of the first dielectric layer 502. Dielectric constant.
  • C3 represents the capacitance under the field plate, and its determining factors include the length of the field plate, the position of the field plate, and the thickness and dielectric constant of the first dielectric layer 502 and the second dielectric layer 504 .
  • the capacitance values of the C1, C2 and C3 capacitors are usually affected by adjusting the dielectric constant and thickness parameters of the materials of the first dielectric layer 502 and the second dielectric layer 504. Further optimize the gain index. Specifically, for the semiconductor device shown in Figure 1, in order to obtain a lower output capacitance and thus achieve an increase in gain, it is usually necessary to reduce the capacitance of C1 and C2 and increase the capacitance of C3.
  • the capacitance of the capacitor C2 can also be reduced by reducing the dielectric constant of the first dielectric layer 502, but the capacitance of the capacitor C3 will also be weakened. Therefore, there is a bottleneck in improving the device gain simply by adjusting the physical properties of the first dielectric layer 502, such as the thickness and dielectric constant.
  • the capacitance of the capacitor C1 is simply adjusted, it needs to be achieved by adjusting the size of the gate electrode 503 .
  • the size of the gate electrode 503 is limited by the exposure limit of the photolithography machine and cannot be adjusted significantly. Therefore, the capacitance adjustment of capacitor C1 and even the improvement of device gain are extremely limited.
  • by reducing the thickness of the second dielectric layer 504 it is beneficial to increase the capacitance value of the capacitor C3, thereby achieving an increase in gain.
  • reducing the thickness of the second dielectric layer 504 will also reduce the distance between the gate electrode 503 and the field plate 505, thereby causing a problem of poor voltage resistance characteristics between the gate electrode 503 and the field plate 505.
  • a semiconductor device 100 In order to solve or at least partially solve the above or other potential problems existing in semiconductor devices, embodiments of the present disclosure provide a semiconductor device 100 and a manufacturing method thereof.
  • a schematic structural diagram of a semiconductor device 100 according to an embodiment of the present disclosure is shown in FIG. 2 .
  • a semiconductor device 100 according to an embodiment of the present disclosure generally includes a substrate 101 , a first dielectric layer 102 , a gate electrode 103 , and a second dielectric layer 104 .
  • the gate electrode 103 includes a portion in direct contact with the substrate 101 (hereinafter referred to as a contact region 1031 ) and a portion spaced apart from the substrate 101 by the first dielectric layer 102 (hereinafter referred to as a gate cap region 1032 ).
  • these regions include the first region 1011 corresponding to the gate cap region 1032 of the gate electrode 103, the second region 1012 corresponding to the contact region 1031 of the gate electrode 103, and other regions except the first region. 1011 and the third area 1013 outside the second area 1012.
  • “Corresponding” here means the area covered by the projection of each corresponding area (contact area 1031 and gate cap area 1032) of the gate electrode 103 in the vertical direction shown in Figure 2.
  • the first dielectric layer 102 is applied to the first region 1011 and the third region 1013 of the substrate 101 .
  • “Applying” here may refer to disposing it on the corresponding area through any suitable one or more process steps such as deposition, which will be further elaborated below.
  • the gate electrode 103 is coupled to the substrate 101, wherein the contact region 1031 of the gate electrode 103 contacts the second region 1012 of the substrate 101, and the gate cap region 1032 is spaced apart from the first region 1011 of the substrate 101 by a certain distance ( For convenience of description, it will be referred to as the first distance D1) in the following.
  • the second dielectric layer 104 is applied outside the gate electrode 103 and the first dielectric layer 102 . The outside here means that the second dielectric layer 104 covers the gate electrode 103 and the first dielectric layer 102 . In the third region 1013, the second dielectric layer 104 and the substrate 101 are spaced apart by a second distance D2.
  • the second pitch D2 in the semiconductor device 100 is smaller than the first pitch D1.
  • This additionally increases the thickness between the gate cap and the substrate that affects the C2 parasitic capacitance mentioned earlier. In this way, C2 parasitic capacitance is reduced.
  • the increase in the thickness of the first dielectric layer 102 since the increase in the thickness of the first dielectric layer 102 only remains in the gate cap region 1032 of the gate and does not extend to other regions, the capacitance value of the capacitor C3 can still be maintained at a high level, thereby eliminating the aforementioned problems.
  • the potential and electric field distribution on the side of the gate electrode 103 close to the drain end can be re-adjusted, making it easier for TDDB strikes to occur.
  • the electric field stress at the penetration position is effectively weakened, thereby improving the overall reliability of the semiconductor device 100 .
  • the semiconductor device 100 further includes a field plate 105 .
  • the field plate 105 is locally applied outside the second dielectric layer 104, thereby forming a short field plate 105 structure. Since the second dielectric layer 104 has a substantially consistent thickness, the vertical spacing between the field plate 105 and the gate electrode 103 and the vertical spacing between the field plate 105 and the first dielectric layer 102 are substantially the same. In this way, combined with the above increase in the thickness of the first dielectric layer 102 corresponding to the gate cap region 1032, on the one hand, the parasitic capacitance of the gate region is reduced, and on the other hand, the capacitance value from the metal of the field plate 105 to the channel is increased. , so that the gain of the semiconductor device 100 can be further effectively improved.
  • the difference between the first spacing D1 and the second spacing D2 may be in the range of 20 nm to 500 nm, including endpoint values of 20 nm and 500 nm. That is to say, the thickness of the first dielectric layer 102 corresponding to the first region 1011 or the gate cap region 1032 of the substrate 101 is increased to a thickness between 20 nm and 500 nm.
  • the specific thickness here can be appropriately selected from this range based on the required stability, cost, and other aspects of the semiconductor device 100, thereby improving the flexibility and cost-effectiveness of the semiconductor device 100 preparation.
  • the difference between the first distance D1 and the second distance D2 may be realized by the thickened dielectric layer 1021 of the first dielectric layer 102 .
  • the thickened dielectric layer 1021 is a portion of the first dielectric layer 102 arranged corresponding to the first region 1011 .
  • the first dielectric layer 102 also includes a uniform thickness layer 1022.
  • the uniform thickness layer 1022 is arranged in the first region 1011 and the third region 1013 of the substrate 101 .
  • the uniform thickness layer 1022 and the thickened dielectric layer 1021 may be formed from the same dielectric material in the same or different preparation steps.
  • the uniform thickness layer 1022 and the thickened dielectric layer 1021 may also be formed using different materials and in different preparation processes. This is explained further below.
  • the substrate 101 may be made of one of the following materials: silicon carbide, gallium nitride, gallium nitride on silicon carbide, gallium nitride on sapphire, gallium nitride on silicon, aluminum indium nitride, Aluminum nitride.
  • the first dielectric layer 102 or the second dielectric layer 104 may be made of at least one of the following materials: silicon nitride, silicon oxynitride, silicon dioxide, nitrogen Aluminum oxide, aluminum oxide and titanium dioxide.
  • gate electrode 103 and field plate 105 may include at least one of the following metals or metal compounds: nickel, titanium, lead, platinum, gold, titanium nitride, tantalum nitride, and copper. It can be seen that the substrate 101 , the first dielectric layer 102 and the second dielectric layer 104 as well as the gate electrode 103 and the field plate 105 can be realized by a variety of materials, thereby improving the flexibility and cost-effectiveness of the preparation of the semiconductor device 100 .
  • the above-mentioned materials for the substrate 101, the first dielectric layer 102 and the second dielectric layer 104, the gate electrode 103 and the field plate 105 are not exhaustive, and there may be other possible materials to prepare the corresponding ones. part.
  • Embodiments of the present disclosure also provide a method of preparing a semiconductor device 100 to prepare the semiconductor device 100 mentioned above.
  • FIG. 3 shows a flow chart of a method of manufacturing the semiconductor device 100 .
  • FIG. 4 shows a schematic structural diagram of the semiconductor device 100 corresponding to various steps of preparation in FIG. 3 .
  • a substrate 101 having a first region 1011 , a second region 1012 and a third region 1013 on its surface is provided.
  • the substrate 101 may be, for example, a wafer commonly mentioned in the art.
  • the first dielectric layer 102 is applied to the first region 1011 and the third region 1013 of the substrate 101.
  • the gate electrode 103 is applied such that the contact region 1031 of the gate electrode 103 contacts the substrate 101 in the second region 1012, and the gate cap region 1032 It is spaced apart from the substrate 101 by a first distance D1.
  • a second dielectric layer 104 is applied outside the gate electrode 103 and the first dielectric layer 102, such that the second dielectric layer 104 and the substrate 101 are spaced apart by a second distance D2 in the second region 1012, and the second distance D2 is smaller than the first distance D1.
  • the semiconductor device 100 formed in this manner can have reduced parasitic capacitance C2 and increased capacitance C3 between the field plate 105 and the substrate 101, thereby improving the gain and reliability of the semiconductor device 100.
  • the method may further include locally applying the field plate 105 outside the second dielectric layer 104 to form the short field plate 105 .
  • This can be achieved by any suitable process and method such as photolithographic patterning, etching, etc. This disclosure does not limit this.
  • the step of forming the first dielectric layer 102 in the first region 1011 and the third region 1013 can be implemented in any appropriate manner, and several example embodiments will be described below with reference to FIGS. 5 to 9 . It should be understood that these example embodiments are only examples, and are not intended to be exhaustive or limit the scope of the present disclosure. There may also be any other suitable ways to form the first dielectric layer 102, which will not be described in detail herein.
  • the thickened dielectric layer 1021 in the first dielectric layer 102 may be formed first.
  • the foregoing application of the first dielectric layer 102 may include applying a thickened dielectric layer 1021 in the first region 1011 and the second region 1012, as shown in (2) in FIG. 5 .
  • applying the thickened dielectric layer 1021 in the first region 1011 and the second region 1012 can be achieved through the following steps. Step 1: Deposit a layer of dielectric layer material with a thickness ranging from 20 nm to 500 nm (endpoint values included) on the entire substrate 101, as shown in (1) in Figure 6 .
  • the substrate 101 may include one of the following: silicon carbide, gallium nitride, gallium nitride on silicon carbide, gallium nitride on sapphire, gallium nitride on silicon, aluminum indium nitride, aluminum nitride , where silicon carbide includes but is not limited to 4H-silicon carbide, 6H-silicon carbide, 3C-silicon carbide, etc.
  • Materials used to prepare the thickened dielectric layer 1021 include single-layer or multi-layer stack structures of dielectric materials such as silicon nitride, silicon oxynitride, silicon dioxide, aluminum nitride, aluminum oxide, or titanium dioxide.
  • Step 2 Perform photolithography patterning to define a photoresist pattern covering the first area 1011 and the second area 1012, as shown in (2) in Figure 6 .
  • the dielectric layer under the pattern defined by the photoresist is etched by dry/wet etching method, as shown in (3) in Figure 6.
  • Etching is the process of removing material from its surface.
  • the two main types of etching are the aforementioned wet etching and dry etching (e.g., plasma etching).
  • An etching process that involves the use of liquid chemicals or etchants to remove material is called wet etching.
  • a plasma or etching gas is used to remove substrate material. Dry etching produces gaseous products that should diffuse into the bulk gas and be exhausted through the vacuum system.
  • Step 4 Further etch the pattern defined by the photoresist through a dry/wet etching scheme, so that the dielectric layer in the area not covered by the photoresist pattern (ie, the third area 1013) is completely etched until the substrate is exposed. 101, as shown in (4) in Figure 6.
  • Step 5 Remove the photoresist by dry/wet method, as shown in (5) in Figure 6. In this way, the state shown in step (2) in Figure 5 is formed.
  • applying the thickened dielectric layer 1021 may include applying the thickened dielectric layer 1021 on the entire substrate 101; and removing the thickened dielectric layer 1021 outside the third region 1013 (for example, by the above means) The third region 1013 of the substrate 101 is exposed, thereby forming the state shown in step (2) in FIG. 5 .
  • applying the thickened dielectric layer 1021 may also be implemented in the following manner.
  • the first step perform pattern definition of a double-layer photoresist on the surface of the substrate 101, as shown in (1) in Figure 7, which includes applying the first layer of photoresist 1061 and the second layer in the third area 1013 Photoresist 1062.
  • the second step is to deposit a first layer of dielectric layer material with a thickness ranging from 20 nm to 500 nm on the entire surface of the substrate 101 .
  • the dielectric layer material will cover the first area 1011 and the second area 1012 of the substrate 101 and the third area 1013 covered with a double-layer photoresist, as shown in (2) in FIG. 7 .
  • Step 3 Remove the double-layer photoresist by dry/wet method.
  • Wet glue removal is divided into organic solvent glue removal and inorganic solvent glue removal.
  • Organic solvent stripping mainly removes the photoresist by dissolving it in an organic solvent; inorganic solvent stripping uses the characteristic that the photoresist itself is an organic matter, and uses some inorganic solvents to oxidize the carbon element in the photoresist into carbon dioxide. And remove it; dry glue removal uses plasma to strip off the photoresist. Subsequently, in order to further remove the remaining dielectric material, the remaining dielectric layer material can be processed by dry processing and wet processing respectively, to finally achieve the situation shown in (3) in Figure 7 or (2) in Figure 5 .
  • applying the thickened dielectric layer 1021 may include applying the thickened dielectric layer 1021 including: applying a photoresist (including the first layer of photoresist 1061 and the second layer of photoresist 1061 in the third region 1013 of the substrate 101 layer photoresist 1062); apply a thickening dielectric layer 1021 on the first region 1011 and the second region 1012 of the substrate 101 and outside the photoresist; remove the photoresist to expose the third region 1013 of the substrate 101.
  • the process of first forming the thickened dielectric layer 1021 of the first dielectric layer 102 is introduced above. After the thickened dielectric layer 1021 is formed in the first region 1011 and the second region 1012, as shown in (3) in Figure 7 or (2) in Figure 5, next, a second layer of thickness is deposited on the wafer surface. Dielectric layer materials in the range of 20nm to 500nm are shown in (3) in Figure 5 and (4) in Figure 7. The second layer of dielectric layer material will eventually form the uniform thickness layer 1022 of the first dielectric layer 102.
  • the material may include a single layer of dielectric materials such as silicon nitride, silicon oxynitride, silicon dioxide, aluminum nitride, aluminum oxide, or titanium dioxide. Or multi-layer stacked structure.
  • the uniform thickness layer 1022 and the thickened dielectric layer 1021 of the first dielectric layer 102 may be formed using the same or different materials. Subsequently, the dielectric layer 1021 and the uniform thickness layer 1022 are thickened through photolithography and etching processes and patterned and etched until the first region 1011 of the substrate 101 is completely exposed, as shown in (2) in Figure 4 and Figure 5 (4) and (5) in FIG. 7 , thereby forming the first dielectric layer 102 in the first region 1011 and the third region 1013 .
  • the process of applying the gate electrode 103 can be performed next.
  • a first layer of metal stack material with a thickness ranging from 20 nm to 1500 nm may be deposited outside the first region 1011 and the second region 1012 of the substrate 101 to form the gate electrode 103 . Since the first region 1011 has been covered by the uniform thickness layer 1022 and the thickened dielectric layer 1021 of the first dielectric layer 102, the metal layer deposited in this region will form a gate cap region 1032, as shown in (3) in Figure 4 Show. A second dielectric layer 104 is then formed.
  • a third layer of dielectric layer material with a thickness ranging from 20 nm to 500 nm is deposited outside the gate electrode 103 and the first dielectric layer 102 to finally form the second dielectric layer 104, as shown in (4) in Figure 4 .
  • a metal stack material with a thickness ranging from 20 nm to 500 nm is locally deposited outside the second dielectric layer 104 to form the field plate 105, as shown in (5) in FIG. 4 .
  • the different processes of first forming the thickened dielectric layer 1021 of the first dielectric layer 102, then forming the uniform thickness layer 1022 of the first dielectric layer 102, and finally forming the entire semiconductor device 100 are described above with reference to FIGS. 4 to 7 .
  • the thickened dielectric layer 1021 of the first dielectric layer 102 may be disposed between the uniform thickness layer 1022 and the substrate 101 .
  • the first dielectric layer 102 can also be implemented in any other appropriate manner.
  • the uniform thickness layer 1022 may be formed first, and then the thickened dielectric layer 1021 may be formed.
  • a layer of dielectric layer material with a thickness ranging from 20 nm to 500 nm is deposited on the entire substrate 101 .
  • the dielectric layer material will eventually form a uniform thickness layer 1022 of the first dielectric layer 102, as shown in (1) in FIG. 8 .
  • the materials used for the substrate 101 and the materials used for the uniform thickness layer 1022 of the first dielectric layer 102 are similar to the materials used in the previously mentioned embodiments, and will not be described in detail here, and the uniform thickness layer 1022 It is also a single layer or stacked structure formed of one of silicon nitride, silicon oxynitride, silicon dioxide, aluminum nitride, aluminum oxide or titanium oxide.
  • the second step deposit a second layer of dielectric layer material with a thickness ranging from 20 nm to 500 nm on the entire substrate 101, as shown in (2) in Figure 8.
  • the second layer of dielectric layer material will eventually form the thickened dielectric layer 1021.
  • the second dielectric layer and the first dielectric layer are different in refractive index, deposition temperature, density and etching resistance.
  • the third step is to pattern-etch the applied two dielectric layers through photolithography and etching processes until the second region 1012 of the substrate 101 is completely exposed, as shown in (3) in FIG. 8 .
  • the gate electrode 103 is formed. Specifically, as shown in (4) in FIG. 8 , a first layer of metal laminate material with a thickness ranging from 20 nm to 1500 nm is deposited outside the regions corresponding to the first region 1011 and the second region 1012 of the substrate 101 . This metal stack material will ultimately form gate electrode 103 .
  • the first layer of patterned metal as a hard self-aligned mask, and use dry/wet methods to etch the second dielectric layer to a depth of 20nm to 500nm, so that the etched surface stays at The interface position between the second layer and the first dielectric layer, thereby retaining the second dielectric layer under the gate cap region 1032 of the gate electrode 103 (ie, thickening the dielectric layer 1021), as shown in (5) in Figure 8 .
  • the subsequent process is similar to the process of applying the second dielectric layer 104 and the field plate 105 described previously.
  • a third layer of dielectric layer material with a thickness ranging from 20 nm to 500 nm is deposited outside the gate electrode 103 and the first dielectric layer 102 to finally form the second dielectric layer 104, as shown in (4) in FIG. 4 .
  • a metal stack material with a thickness ranging from 20 nm to 500 nm is locally deposited outside the second dielectric layer 104 to form the field plate 105, as shown in (5) in FIG. 4 .
  • the thickened dielectric layer 1021 of the first dielectric layer 102 is located between the gate cap region 1032 of the gate electrode 103 and the first dielectric layer 102, and in order to facilitate etching, the thickened dielectric layer 1021 and the uniform thickness layer 1022 are made of different materials. In some embodiments, the thickened dielectric layer 1021 and the uniform thickness layer 1022 in the first dielectric layer 102 can also be formed using the same material and in the same step.
  • a layer of dielectric layer material with a thickness ranging from 20 nm to 500 nm is deposited on the entire substrate 101 , as shown in (1) in FIG. 9 .
  • the dielectric layer has a first thickness, and the first thickness is substantially equal to the first distance D1 mentioned above.
  • the dielectric layer area is then patterned and etched through photolithography and etching processes until the second area 1012 of the substrate 101 is completely exposed, as shown in (2) in FIG. 9 .
  • a first layer of metal laminate material with a thickness ranging from 20 nm to 1500 nm is deposited outside the first region 1011 and the second region 1012 of the substrate 101 to form the gate electrode 103.
  • the first layer of patterned metal as a hard self-aligned mask, and use dry/wet methods to etch the first dielectric layer to a depth ranging from 20nm to 500nm.
  • the third area after etching corresponds to 1013
  • the dielectric layer has a second thickness, and the second thickness is equal to the second distance D2 mentioned above.
  • the subsequent process is similar to the process of applying the second dielectric layer 104 and the field plate 105 described previously. That is, a third layer of dielectric layer material with a thickness ranging from 20 nm to 500 nm is deposited outside the gate electrode 103 and the first dielectric layer 102 to finally form the second dielectric layer 104, as shown in (4) in FIG. 4 . Finally, in some embodiments, a metal stack material with a thickness ranging from 20 nm to 500 nm is locally deposited outside the second dielectric layer 104 to form the field plate 105, as shown in (5) in FIG. 4 .
  • the semiconductor device 100 fabricated by the above-mentioned various fabrication processes additionally increases the thickness between the gate cap and the substrate that affects the C2 parasitic capacitance mentioned above. In this way, C2 parasitic capacitance is reduced.
  • the increase in the thickness of the first dielectric layer 102 since the increase in the thickness of the first dielectric layer 102 only remains in the gate cap region 1032 of the gate and does not extend to other regions, the capacitance value of the capacitor C3 can still be maintained at a high level, thereby eliminating the aforementioned problems.
  • the potential and electric field distribution on the side of the gate electrode 103 close to the drain end can be re-adjusted, making it easier for TDDB strikes to occur.
  • the electric field stress at the penetration position is effectively weakened, thereby improving the overall reliability of the device.

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Abstract

本公开的实施例提供了一种半导体器件及其制备方法。该该半导体器件包括基底，基底的表面具有第一区域、第二区域和第三区域；第一介质层，施加在基底的第一区域和第三区域；栅电极，耦合至基底，包括栅帽区以及与基底的第二区域接触的接触区，栅帽区经由第一介质层而与基底的第一区域间隔开第一间距；第二介质层，施加在栅电极和第一介质层的外部，在第三区域，第二介质层与基底间隔开第二间距，第二间距小于第一间距。通过将栅帽区与基底间隔开的第一间距设置为比第二介质层与基底间隔开的第二间距大，能够在不改变其他设计结构的前提下降低寄生电容的容值，从而能够提高半导体器件在高频下的增益特性。

Description

半导体器件及其制备方法 技术领域
本公开涉及半导体器件制备领域，并且具体地涉及一种具有高增益的半导体器件及其制备方法。
背景技术
半导体行业发展至今已经经历了三代材料变更：第一代半导体材料指硅(Si)、锗(Ge)；第二代半导体材料指的是化合物半导体材料，比如砷化镓(GaAs)和锑化铟(InSb)等。近年来，以氮化镓(GaN)和碳化硅(SiC)为代表的第三代化合物半导体材料，由于其具有的优异的材料特性而受到广泛的关注。其中氮化镓基的器件由于其迁移率高，耐击穿能力强和散热特性好等优势而在射频器件领域被广泛应用。
常见的射频氮化镓器件采用源极短接场板技术，调制栅漏间的电场和电容分布，从而实现特定的高频增益指标。然而，基于当前业界氮化镓半导体器件的传统结构，存在增益提升空间不足的问题。
发明内容
本公开涉及关于半导体器件的技术方案，并且具体提供了一种半导体器件及其制备方法。
在本公开的第一方面，提供了一种半导体器件。该半导体器件包括基底，所述基底的表面具有第一区域、第二区域和第三区域；第一介质层，施加在所述基底的所述第一区域和所述第三区域；栅电极，耦合至所述基底，包括栅帽区以及与所述基底的所述第二区域接触的接触区，所述栅帽区经由所述第一介质层而与所述基底的所述第一区域间隔开第一间距；第二介质层，施加在所述栅电极和第一介质层的外部，在所述第三区域，所述第二介质层与所述基底间隔开第二间距，所述第二间距小于所述第一间距。
通过将栅帽区与基底间隔开的第一间距设置为比第二介质层与基底间隔开的第二间距大，能够在不改变其他设计结构的前提下降低寄生电容的容值，从而能够提高半导体器件在高频下的增益特性。
在一些实现方式中，所述第一间距与所述第二间距的差在20nm～500nm之间。根据不同的需求，上述范围提供了半导体器件制备的灵活性。
在一种实现方式中，加热部件还包括：所述第一介质层包括：均厚层，布置在所述第一区域和所述第三区域；以及增厚介质层，布置在所述均厚层和所述第一区域之间或者在所述均厚层和所述栅帽区之间，并且所述增厚介质层的厚度在20nm～500nm之间。均厚层和增厚介质层可以采用相同或者不同的材质制成。一方面，这能够提高制备半导体器件的灵活性。另一方面，还可以在制备半导体器件的过程中兼顾成本和可靠性。
在一种实现方式中，半导体器件还包括场板，被局部地施加在所述第二介质层的外部，所述场板与所述栅电极之间的间距和所述场板与所述第一介质层之间的间距基本相同。通过采用短场板技术，并进而调制栅极和漏极之间的电场和电容分布，能够实现所需的高频增益指标。
在一些实现方式中，基底包括以下材料中的一种：碳化硅、氮化镓、碳化硅基氮化 镓、蓝宝石基氮化镓、硅基氮化镓、氮化铝铟、氮化铝。多种材料都可以用来制备基底，这使得半导体器件的制备更加灵活。
在一种实现方式中，所述第一介质层或所述第二介质层包括以下材料中的至少一种：氮化硅、氮氧化硅、二氧化硅、氮化铝、氧化铝和二氧化钛。类似地，多种材料都可以用来制备第一介质层或第二介质层，这使得半导体器件的制备更加灵活。
根据本公开的第二方面，提供了一种制备半导体器件的方法。所述方法包括提供基底，所述基底的表面包括与所述半导体器件的栅电极的栅帽区对应的第一区域、与所述栅电极的接触区对应的第二区域以及除第一区域和所述第二区域外的第三区域；在所述第一区域以及所述第三区域施加第一介质层；施加栅电极，以使得所述所述接触区接触所述基底，并且所述栅帽区与所述基底间隔开第一间距；以及在所述栅电极和第一介质层的外部施加第二介质层，在所述第三区域，所述第二介质层与所述基底间隔开第二间距，所述第二间距小于所述第一间距。通过该制备方法，能够以可靠的方式制备在高频下具有高增益特性的半导体器件。
在一些实现方式中，方法还包括在所述第二介质层的外部局部地施加场板，所述场板与所述栅电极之间的间距和所述场板与所述第一介质层之间的间距基本相同。以此方式，所制备的半导体器件能够具有所需的高频增益指标。
在一些实现方式中，施加所述第一介质层包括在所述第一区域和所述第二区域施加增厚介质层；在所述第三区域和所述增厚介质层外施加均厚层；以及移除所述第二区域外的所述均厚层和所述增厚介质层以暴露所述基底的所述第二区域。
在一些实现方式中，施加增厚介质层包括在整个所述基底上施加所述增厚介质层；移除所述第三区域外的增厚介质层以暴露所述基底的所述第三区域。
在一些实现方式中，施加增厚介质层包括在所述基底的所述第三区域施加光刻胶；在所述基底的所述第一区域和所述第二区域以及所述光刻胶外施加增厚介质层；移除光刻胶以暴露所述基底的所述第三区域。
在一些实现方式中，施加所述第一介质层和施加栅电极包括在整个所述基底外施加所述均厚层；在所述均厚层外施加所述增厚介质层；移除所述第二区域外的所述均厚层和所述增厚介质层以暴露所述基底的所述第二区域；施加栅电极；以及利用栅电极作为自对准掩膜移除所述第三区域外的所述增厚介质层。
在一些实现方式中，施加所述第一介质层和施加栅电极包括在整个所述基底外施加所述第一介质层，所述第一介质层具有第一厚度，所述第一厚度等于所述第一间距；移除所述第二区域外的所述第一介质层以暴露所述基底的所述第二区域；施加栅电极；以及利用栅电极作为自对准掩膜移除所述第三区域外的所述第一介质层在厚度方向上的一部分，以使得在所述第三区域处的所述第一介质层具有小于第一厚度的第二厚度，所述第二厚度等于所述第二间距。
应当理解，发明内容部分中所描述的内容并非旨在限定本公开的关键或重要特征，亦非用于限制本公开的范围。本公开的其他特征通过以下的描述将变得容易理解。
附图说明
通过参考附图阅读下文的详细描述，本公开的实施例的上述以及其他目的、特征和优点将变得容易理解。在附图中，以示例性而非限制性的方式示出了本公开的若干实施 例。
图1以示例性的方式示出了传统方案中半导体器件的结构示意图；
图2示出了根据本公开实施例的半导体器件的结构示意图；
图3示出了根据本公开实施例的半导体器件的制备方法的流程图；以及
图4至图9示出了根据本公开不同实施例的半导体器件的制备过程中各个阶段的示意图。
贯穿所有附图，相同或者相似的参考标号被用来表示相同或者相似的组件。
具体实施方式
下文将参考附图中示出的若干示例性实施例来描述本公开的原理和精神。应当理解，描述这些具体的实施例仅是为了使本领域的技术人员能够更好地理解并实现本公开，而并非以任何方式限制本公开的范围。在以下描述和权利要求中，除非另有定义，否则本文中使用的所有技术和科学术语具有与所属领域的普通技术人员通常所理解的含义。
如本文所使用的，术语“包括”及其类似用语应当理解为开放性包含，即“包括但不限于”。术语“基于”应当理解为“至少部分地基于”。术语“一个实施例”或“该实施例”应当理解为“至少一个实施例”。术语“第一”、“第二”等等可以指代不同的或相同的对象，并且仅用于区分所指代的对象，而不暗示所指代的对象的特定空间顺序、时间顺序、重要性顺序，等等。
本文使用的术语“电路”是指以下的一项或多项：(a)仅硬件电路实现方式(诸如仅模拟和/或数字电路的实现方式)；以及(b)硬件电路和软件的组合，诸如(如果适用)：(i)模拟和/或数字硬件电路与软件/固件的组合，以及(ii)硬件处理器的任何部分与软件(包括一起工作以使装置，诸如通信设备或其他电子设备等，执行各种功能的数字信号处理器、软件和存储器)；以及(c)硬件电路和/或处理器，诸如微处理器或者微处理器的一部分，其要求软件(例如固件)用于操作，但是在不需要软件用于操作时可以没有软件。电路的定义适用于此术语在本申请中(包括权利要求中)的所有使用场景。作为另一示例，在此使用的术语“电路”也覆盖仅硬件电路或处理器(或多个处理器)、或者硬件电路或处理器的一部分、或者随附软件或固件的实现方式。例如，如果适用于特定权利要求元素，术语“电路”还覆盖基带集成电路或处理器集成电路、网络设备、终端设备或其他设备中的类似集成电路。
对于一些半导体器件，例如氮化镓半导体器件，由于其迁移率高，耐击穿能力强和散热特性好等优势而在射频器件领域被广泛应用。对于这种半导体器件而言，在高频下对增益特性具有较高的指标要求。高频下的增益特性主要取决于高频工况下，寄生电容能否跟随信号进行高效快速的充放动作。目前业界通常通过改变场板金属下方的钝化层，调制偏置电压下的沟道电容，从而实现输出电容容值的降低。但仅通过钝化层的参数调整，容易诱发其他的负面作用，包括：静电放电(Electrical Static Discharge，ESD)击穿，金属-绝缘层-金属(Metal-insulator-Metal，MIM)电容击穿以及击穿特性退化等。
具体而言，现以射频氮化镓器件作为本申请中提到的半导体器件为例来描述传统的方案中的一些问题。应当理解的是，本文中所提到的半导体器件除了射频氮化镓器件外还可以是任意其他的适当的半导体器件，在这下文中将不再分别赘述。图1示出了常见的常见的射频氮化镓半导体器件。该半导体器件采用源极短接场板技术，传统方案中通 过调制栅漏间的电场和电容分布，从而实现特定的高频增益指标。如图1所示，传统的半导体器件通常包括基底501、第一介质层502、栅电极503、第二介质层504和短场板505。栅电极503和场板505由金属材料形成。在该半导体器件中，通常需要对三个电容C1、C2和C3进行调整，来优化增益指标。
其中C1表示栅极-漏极的本征电容，其决定因素为栅电极的长度。C2表示栅帽-漏极的寄生电容，其决定因素包括栅电极503的栅帽长度、第一介质层502的厚度(即，栅帽和基底501之间的距离)以及第一介质层502的介电常数。C3表示场板下方电容，其决定因素包括场板的长度，场板的位置以及第一介质层502和第二介质层504的厚度和介电常数。
通常，在基底501的材料固定的前提下，通常通过对第一介质层502和第二介质层504的材料的介电常数和厚度参数的调整，来影响C1、C2和C3电容的容值，进一步来优化增益指标。具体而言，对于图1所示的半导体器件而言，为了获得更低的输出电容，从而实现增益的提升，通常需要降低C1和C2的电容，并增加C3的电容。
但是很显然，在不改变介质材料的情况下，降低C2电容需要增加第一介质层502的厚度。但是第一介质层502厚度的增加会导致场板505下方的钝化厚度增加，导致电容C3的容值降低。因此单纯增加第一介质层502厚度与预期的结果不服，无法实现增益控制。
同样道理，还可以通过降低第一介质层502的介电常数来降低电容C2的容值，但是也同样存在着对电容C3的容值的削弱。因而单纯通过对第一介质层502的诸如厚度和介电常数的物理特性的调整来实现器件增益的提升，存在瓶颈。
如果单纯对电容C1的容值进行调整，需要通过调整栅电极503的尺寸来实现。但栅电极503的尺寸受制于光刻机的曝光极限，无法大幅度调整。因而对电容C1的容值调整乃至器件增益的提升极为有限。此外，通过减少第二介质层504的厚度，有利于增加电容C3的容值，来实现增益的提升。但减少第二介质层504的厚度又会减少栅电极503和场板505之间的距离，从而带来栅电极503和场板505之间的耐压特性差的问题。
此外，在图1所示的半导体器件结构中，在高压反偏的应力状态下，存在着横向电场应力分布。横向电场易在栅电极503的栅帽以及场板505对应的位置出现较高的电场尖峰。在持续的高电场应力下，该电场尖峰对应位置的栅帽下方的介质层容易产生时间相关电介质击穿(time dependent dielectric breakdown,TDDB)击穿现象，从而存在较高的可靠性风险。
为了解决或者至少部分地解决半导体器件中存在的上述或者其他潜在问题，本公开的实施例提供了一种半导体器件100及其制备方法。图2中示出了根据本公开实施例的半导体器件100的结构示意图。如图2所示，根据本公开实施例的半导体器件100总体上包括基底101、第一介质层102、栅电极103、第二介质层104。栅电极103包括与基底101直接接触的部分(在后文中将被称为接触区1031)以及通过第一介质层102而与基底101间隔开的部分(在后文中将被称为栅帽区1032)。基底101的表面存在着分别与第一介质层102、栅电极103的接触区1031和栅帽区1032对应的多个不同区域。为了便于后文的描述，下面的描述中将这些区域包括与栅电极103的栅帽区1032对应的第一区域1011、与栅电极103的接触区1031对应的第二区域1012和除第一区域1011以及第二区域1012外的第三区域1013。此处的“对应”表示栅电极103对应的各区(接 触区1031和栅帽区1032)在图2所示的竖直方向上上的投影所覆盖的区域。
从图2可以看出，第一介质层102是施加在基底101的第一区域1011和第三区域1013。这里的“施加”可以是指通过诸如沉积等任意适当的一个或多个流程步骤来使之布置在对应的区域上，这将在后文中做进一步阐述。栅电极103耦合至基底101，其中栅电极103的接触区1031接触基底101的第二区域1012，并且栅帽区1032经由第一介质层102而与基底101的第一区域1011间隔开一定间距(为了便于描述，后文中将被称为第一间距D1)。第二介质层104，施加在栅电极103和第一介质层102的外部。这里的外部是指第二介质层104覆盖栅电极103和第一介质层102。在第三区域1013，第二介质层104和基底101间隔开第二间距D2。
不同于传统的半导体器件，根据本申请实施例的半导体器件100中的第二间距D2小于第一间距D1。这就额外地增加了前文中所提到的影响C2寄生电容的栅帽和基板之间的厚度。以此方式，C2寄生电容减小。同时，由于第一介质层102厚度的增加仅保留在栅极的栅帽区1032，未拓展到其他区域，使得电容C3的容值依旧可以保持在较高水平，从而可以消除前文中所提到的调整电容C1、C2和C3的容值所带来的矛盾。以此方式，半导体器件100的增益能够被有效提升。
此外，通过单独增加栅帽区1032(即，第一区域1011)对应的第一介质层102的厚度，能够重新调整栅电极103靠近漏端一侧的电势和电场分布，使原本容易出现TDDB击穿位置的电场应力获得有效削弱，从而提升半导体器件100的整体可靠性。
在一些实施例中，如图2所示，半导体器件100还包括场板105。场板105被局部地施加在第二介质层104的外部，从而形成短场板105结构。由于第二介质层104具有基本一致的厚度，因此，场板105与栅电极103之间在竖直方向上的间距以及场板105与第一介质层102在竖直方向上的间距基本相同。以此方式，结合上文中对栅帽区1032对应的第一介质层102的厚度的增加，一方面降低栅极区域的寄生电容，另一方面提高了场板105金属到沟道的电容容值，从而能够进一步有效地提升半导体器件100的增益。
在一些实施例中，第一间距D1和第二间距D2的差可以在20nm～500nm的范围内，并且包括20nm和500nm的端点值。也就是说，在于基底101的第一区域1011或者栅帽区1032对应的第一介质层102的厚度提升了20nm～500nm之间的厚度。此处的具体厚度可以通过所需的半导体器件100的稳定性、成本等各方面来从该范围中适当地选择，从而提高了半导体器件100制备的灵活性和成本效益。
第一间距D1和第二间距D2的差可以通过第一介质层102的增厚介质层1021来实现。增厚介质层1021是第一介质层102中布置在第一区域1011对应的部分。除了增厚介质层1021外，第一介质层102还包括均厚层1022。均厚层1022布置在基底101的第一区域1011和第三区域1013。在一些实施例中，均厚层1022和增厚介质层1021可以通过同一种介质材料在相同或者不同的制备步骤中形成。在一些替代的实施例中，均厚层1022和增厚介质层1021也可以使用不同的材料在不同的制备过程中形成。这将在下文中做进一步阐述。
在一些实施例中，基底101可以由以下材料中的一种制成：碳化硅、氮化镓、碳化硅基氮化镓、蓝宝石基氮化镓、硅基氮化镓、氮化铝铟、氮化铝。替代地或者附加地，在一些实施例中，第一介质层102或所述第二介质层104可以由以下材料中的至少一种制成：氮化硅、氮氧化硅、二氧化硅、氮化铝、氧化铝和二氧化钛。此外，在一些实施 例中，栅电极103和场板105可以包括以下金属或金属化合物中的至少一种：镍、钛、铅、铂、金、氮化钛、氮化钽和铜。可以看出，基底101、第一介质层102和第二介质层104以及栅电极103和场板105都可以通过多种材料来实现，从而提高了半导体器件100制备的灵活度以及成本效益。当然，应当理解的是，上述提到的基底101、第一介质层102和第二介质层104以及栅电极103和场板105的材料并非穷举，还可能存在其他可能的材料来制备对应的部分。
本公开的实施例还提供了一种制备半导体器件100的方法，以制备前文中所提到的半导体器件100。图3示出了该半导体器件100的制备方法的流程图。图4示出了图3制备的各个步骤所对应的半导体器件100的结构示意图。如图3和图4所示，在框410，提供表面具有第一区域1011、第二区域1012和第三区域1013的基底101。基底101例如可以是本领域通常所提到的晶圆。接下来，在框420，在基底101的第一区域1011和第三区域1013施加第一介质层102。这可以通过任意适当的方式来实现，后文中结合附图做进一步阐述。在第一区域1011和第三区域1013形成第一介质层102后，在框430，施加栅电极103，以使得栅电极103的接触区1031在第二区域1012接触基底101，并且栅帽区1032与基底101间隔开第一间距D1。然后，在440，在栅电极103和第一介质层102的外部施加第二介质层104，使得第二介质层104和基底101在第二区域1012间隔开第二间距D2，并且第二间距D2小于第一间距D1。以此方式形成的半导体器件100能够具有减小的寄生电容C2和增大的场板105和基底101之间的电容C3，从而提高了半导体器件100的增益和可靠性。
在一些实施例中，如图4所示，方法还可以包括在第二介质层104的外部局部地施加场板105以形成短场板105。这可以通过任意适当的诸如光刻图形法、刻蚀等任意适当的工艺和方式来实现。本公开对此并不做限制。
此外，对于在第一区域1011和第三区域1013形成第一介质层102的步骤，可以通过多种任意适当的方式来实现，下面将结合图5至图9来描述几种示例实施例。应当理解的是，这些示例实施例只是示例，并非穷举也并非限制本公开的保护范围。还可能存在其他任意适当的方式来形成第一介质层102，在本文中将不再分别赘述。
在一些实施例中，可以先形成第一介质层102中的增厚介质层1021。前文中的施加第一介质层102可以包括在第一区域1011和第二区域1012施加增厚介质层1021，如图5中的(2)所示。在一些实施例中，在第一区域1011和第二区域1012施加增厚介质层1021可以通过以下步骤来实现。第一步：在整个基底101上沉积一层厚度在20nm～500nm范围(包括端点值)的介质层材料，如图6中的(1)所示。如前文中提到的基底101可以包括以下中的一种：碳化硅、氮化镓、碳化硅基氮化镓、蓝宝石基氮化镓、硅基氮化镓、氮化铝铟、氮化铝，其中碳化硅包括但不限于4H-碳化硅、6H-碳化硅、3C-碳化硅等。用于制备增厚介质层1021的材料包括氮化硅、氮氧化硅、二氧化硅、氮化铝、氧化铝或二氧化钛等介质材料的单层或多层堆叠结构。第二步：进行光刻图形化，定义覆盖第一区域1011和第二区域1012的光刻胶图形，如图6中的(2)所示。
然后第三步，通过干法/湿法刻蚀方法对光刻胶定义的图形下方的介质层进行刻蚀，如图6中的(3)所示。刻蚀是从材料表面去除材料的过程。刻蚀的两种主要类型是前面提到的湿法刻蚀和干法刻蚀(例如，等离子体刻蚀)。涉及使用液体化学药品或刻蚀剂去除材料的刻蚀工艺称为湿法刻蚀。在等离子体刻蚀工艺中，也称为干法刻蚀，使用等 离子体或刻蚀气体来去除衬底材料。干法刻蚀会产生气态产物，这些产物应扩散到大量气体中并通过真空系统排出。干法刻蚀有三种类型(例如等离子刻蚀)：化学反应(通过使用反应性等离子体或气体)、物理去除(通常通过动量传递)以及化学反应和物理去除的组合。另一方面，湿法刻蚀仅是化学过程。第四步：通过干法/湿法刻蚀方案对光刻胶定义的图形进行进一步刻蚀，使光刻胶图形未覆盖区域(即，第三区域1013)的介质层完全刻蚀直到露出基底101，如图6中的(4)所示。第五步：通过干法/湿法的方式去除光刻胶，如图6中的(5)所示。以此方式，形成了图5中第(2)步所示的状态。也就是说，在一些实施例中，施加增厚介质层1021可以包括在整个基底101上施加增厚介质层1021；并移除第三区域1013外的增厚介质层1021(例如通过上述手段)以暴露基底101的第三区域1013，从而形成图5中第(2)步所示的状态。
在一些替代的实施例中，施加增厚介质层1021也可以通过以下方式来实现。第一步：在基底101的表面进行双层光刻胶的图形化定义，如图7中的(1)所示，其中包括在第三区域1013施加第一层光刻胶1061和第二层光刻胶1062。然后，第二步：在整个基底101的表面沉积第一层厚度在20nm～500nm范围的介质层材料。该介质层材料会覆盖基底101的第一区域1011和第二区域1012以及覆盖有双层光刻胶的第三区域1013，如图7中的(2)所示。第三步：将双层光刻胶进行干法/湿法去除。湿法去胶又分有机溶剂去胶和无机溶剂去胶。有机溶剂去胶，主要是使光刻胶溶于有机溶剂而除去；无机溶剂去胶则是利用光刻胶本身也是有机物的特点，通过一些无机溶剂，将光刻胶中的碳元素氧化为二氧化碳而将其除去；干法去胶，则是用等离子体将光刻胶剥除。随后，为了进一步清除剩余的介质材料，可以分别通过干法处理和湿法处理剩余的介质层材料，以最终实现如图7中(3)所示或图5中(2)所示的情形。也就是说，在一些实施例中，施加增厚介质层1021可以包括施加增厚介质层1021包括：在基底101的第三区域1013施加光刻胶(包括第一层光刻胶1061和第二层光刻胶1062)；在基底101的第一区域1011和第二区域1012以及光刻胶外施加增厚介质层1021；移除光刻胶以暴露基底101的第三区域1013。
上面介绍了先形成第一介质层102的增厚介质层1021的过程。在第一区域1011和第二区域1012形成了增厚介质层1021后，如图7中(3)所示或图5中(2)所示，接下来，在晶圆表面沉积第二层厚度在20nm～500nm范围的介质层材料，如图5中的(3)和图7中的(4)所示。该第二层介质层材料将最终形成第一介质层102的均厚层1022，材料可以包括氮化硅、氮氧化硅、二氧化硅、氮化铝、氧化铝或二氧化钛等介质材料的单层或多层堆叠结构。如前文中所提到的，第一介质层102的均厚层1022和增厚介质层1021可以使用相同的或者不同的材料形成。随后，通过光刻和刻蚀工艺增厚介质层1021和均厚层1022进行图形化刻蚀，直到彻底暴露出基底101的第一区域1011，如图4中的(2)、图5中的(4)和图7中的(5)所示，从而在第一区域1011和第三区域1013形成了第一介质层102。
再按如上方法在基底101的第一区域1011和第三区域1013形成第一介质层102后，接下来可以进行施加栅电极103的过程。具体而言，在一些实施例中，可以在基底101的第一区域1011和第二区域1012的外部沉积第一层厚度范围在20nm～1500nm范围的金属层叠材料以形成栅电极103。由于第一区域1011已被第一介质层102的均厚层1022和增厚介质层1021所覆盖，所以在此区域沉积的金属层会形成栅帽区1032，如图4中 的(3)所示。随后形成第二介质层104。具体而言，在栅电极103和第一介质层102的外部沉积第三层厚度在20nm～500nm范围的介质层材料，以最终形成第二介质层104，如图4中的(4)所示。最后，在一些实施例中，在第二介质层104的外部局部地沉积厚度在20nm～500nm范围的金属层叠材料以形成场板105，如图4中的(5)所示。
上面通过结合图4至图7描述了先形成第一介质层102的增厚介质层1021，再形成第一介质层102的均厚层1022直至最后形成整个半导体器件100的不同工艺过程。可以看出，在一些实施例中，在最终形成的半导体结构中，第一介质层102的增厚介质层1021可以布置在均厚层1022和基底101之间。当然，应当理解的是，这只是示意性的，并不旨在限制本公开的保护范围。第一介质层102也可以以其他任意适当的方式来实现。例如，在一些替代的制备工艺中，也可以先形成均厚层1022，再形成增厚介质层1021。
具体而言，如图8所示，在一些实施例中，在整个基底101上沉积一层厚度在20nm～500nm范围的介质层材料。该介质层材料将最终形成第一介质层102的均厚层1022，如图8中的(1)所示。基底101所使用的材料和第一介质层102的均厚层1022所使用的材料均和前文中提到的实施例中所采用的材料类似，在这里就不再分别赘述，并且均厚层1022也是氮化硅、氮氧化硅、二氧化硅、氮化铝、氧化铝或氧化钛中的一种所形成的单层或者叠层结构。随后，第二步：在整个基底101上沉积第二层厚度在20nm～500nm范围的介质层材料，如图8中的(2)所示。该第二层介质层材料将最终形成增厚介质层1021。为了便于后续的刻蚀工艺，第二层介质层与第一层介质层在折射率、沉积温度、致密度以及耐刻蚀程度上存在差异。随后，第三步：通过光刻和刻蚀工艺对所施加的两层介质层进行图形化刻蚀，直到彻底暴露出基底101的第二区域1012，如图8中的(3)所示。
接着形成栅电极103。具体而言，如图8中的(4)所示，在基底101的第一区域1011和第二区域1012对应的区域外部沉积第一层厚度在20nm～1500nm范围的金属层叠材料。该金属层叠材料将最终形成栅电极103。然后，采用第一层图形化的金属作为硬质自对准掩膜，使用干法/湿法方式对第二层介质层进行深度在20nm～500nm的刻蚀，使刻蚀后的表面停留在第二层和第一层介质层的界面位置，从而保留栅电极103的栅帽区1032下的第二层介质层(即，增厚介质层1021)，如图8中的(5)所示。接下来的过程就和之前描述的施加第二介质层104和场板105的过程类似了。即，在栅电极103和第一介质层102的外部沉积第三层厚度在20nm～500nm范围的介质层材料，以最终形成第二介质层104，如图4中的(4)所示。最后，在一些实施例中，在第二介质层104的外部局部地沉积厚度在20nm～500nm范围的金属层叠材料以形成场板105，如图4中的(5)所示。
以此方式形成的半导体器件100中第一介质层102的增厚介质层1021是位于栅电极103的栅帽区1032和第一介质层102之间，并且为了便于刻蚀，增厚介质层1021和均厚层1022采用不同的材料制成。在一些实施例中，第一介质层102中的增厚介质层1021和均厚层1022也可以采用相同的材料在相同的步骤中形成。
如图9所述，在一些实施例中，在整个基底101上沉积一层厚度在20nm～500nm范围的介质层材料，如图9中的(1)所示。该介质层具有第一厚度，第一厚度基本等于前文中提到的第一间距D1。随后通过光刻和刻蚀工艺对介质层区域进行图形化刻蚀，直到彻底暴露出基底101的第二区域1012，如图9中的(2)所示。在基底101的第一区域 1011和第二区域1012外侧沉积第一层厚度在20nm～1500nm范围的金属层叠材料，以形成栅电极103。采用第一层图形化的金属作为硬质自对准掩膜，使用干法/湿法方式对第一层介质层进行深度在20nm～500nm范围的刻蚀，刻蚀后的第三区域1013对应的介质层具有第二厚度，该第二厚度等于前文中所提到的第二间距D2。接下来的过程就和之前描述的施加第二介质层104和场板105的过程类似了。即，在栅电极103和第一介质层102的外部沉积第三层厚度在20nm～500nm范围的介质层材料，以最终形成第二介质层104，如图4中的(4)所示。最后，在一些实施例中，在第二介质层104的外部局部地沉积厚度在20nm～500nm范围的金属层叠材料以形成场板105，如图4中的(5)所示。
以上述各种不同的制备工艺制备的半导体器件100额外地增加了前文中所提到的影响C2寄生电容的栅帽和基板之间的厚度。以此方式，C2寄生电容减小。同时，由于第一介质层102厚度的增加仅保留在栅极的栅帽区1032，未拓展到其他区域，使得电容C3的容值依旧可以保持在较高水平，从而可以消除前文中所提到的调整电容C1、C2和C3的容值所带来的矛盾。以此方式，半导体器件100的增益能够被有效提升。
此外，通过单独增加栅帽区1032(即，第一区域1011)对应的第一介质层102的厚度，能够重新调整栅电极103靠近漏端一侧的电势和电场分布，使原本容易出现TDDB击穿位置的电场应力获得有效削弱，从而提升器件的整体可靠性。
尽管已经以特定于结构特征和/或方法动作的语言描述了本申请，但是应当理解，所附权利要求中限定的主题并不限于上文描述的特定特征或动作。相反，上文描述的特定特征和动作是作为实现权利要求的示例而被公开的。

Claims (14)

  1. 一种半导体器件，包括：
    基底(101)，所述基底(101)的表面具有第一区域(1011)、第二区域(1012)和第三区域(1013)；
    第一介质层(102)，施加在所述基底(101)的所述第一区域(1011)和所述第三区域(1013)；
    栅电极(103)，耦合至所述基底(101)，包括栅帽区(1032)以及与所述基底(101)的所述第二区域(1012)接触的接触区(1031)，所述栅帽区(1032)经由所述第一介质层(102)而与所述基底(101)的所述第一区域(1011)间隔开第一间距(D1)；
    第二介质层(104)，施加在所述栅电极(103)和第一介质层(102)的外部，在所述第三区域(1013)，所述第二介质层(104)与所述基底(101)间隔开第二间距(D2)，所述第二间距(D2)小于所述第一间距(D1)。
  2. 根据权利要求1所述的半导体器件，其中所述第一间距(D1)与所述第二间距(D2)的差在20nm～500nm之间。
  3. 根据权利要求1或2所述的半导体器件，其中所述第一介质层(102)包括：
    均厚层(1022)，布置在所述第一区域(1011)和所述第三区域(1013)；以及
    增厚介质层(1021)，布置在所述均厚层(1022)和所述第一区域(1011)之间或者在所述均厚层(1022)和所述栅帽区(1032)之间，并且所述增厚介质层(1021)的厚度在20nm～500nm之间。
  4. 根据权利要求1-3中任一项所述的半导体器件，还包括：
    场板(105)，被局部地施加在所述第二介质层(104)的外部，所述场板(105)与所述栅电极(103)之间的间距和所述场板(105)与所述第一介质层(102)之间的间距基本相同。
  5. 根据权利要求1-4中任一项所述的半导体器件，其中所述基底(101)包括以下材料中的一种：碳化硅、氮化镓、碳化硅基氮化镓、蓝宝石基氮化镓、硅基氮化镓、氮化铝铟、氮化铝。
  6. 根据权利要求1-5中的任一项所述的半导体器件，其中所述第一介质层(102)或所述第二介质层(104)包括以下材料中的至少一种：氮化硅、氮氧化硅、二氧化硅、氮化铝、氧化铝和二氧化钛。
  7. 根据权利要求4-6中的任一项所述的半导体器件，其中所述栅电极和所述场板包括以下材料中的至少一种：镍、钛、铅、铂、金、氮化钛、氮化钽和铜。
  8. 一种制备半导体器件的方法，包括：
    提供基底(101)，所述基底(101)的表面包括与所述半导体器件的栅电极(103)的栅帽区(1032)对应的第一区域(1011)、与所述栅电极(103)的接触区(1031)对应的第二 区域(1012)以及除第一区域(1011)和所述第二区域(1012)外的第三区域(1013)；
    在所述第一区域(1011)以及所述第三区域(1013)施加第一介质层(102)；
    施加栅电极(103)，以使得所述所述接触区(1031)接触所述基底(101)，并且所述栅帽区(1032)与所述基底(101)间隔开第一间距(D1)；以及
    在所述栅电极(103)和第一介质层(102)的外部施加第二介质层(104)，在所述第三区域，所述第二介质层(104)与所述基底(101)间隔开第二间距(D2)，所述第二间距(D2)小于所述第一间距(D1)。
  9. 根据权利要求8所述的方法，还包括：
    在所述第二介质层(104)的外部局部地施加场板(105)，所述场板(105)与所述栅电极(103)之间的间距和所述场板(105)与所述第一介质层(102)之间的间距基本相同。
  10. 根据权利要求8或9所述的方法，其中施加所述第一介质层(102)包括：
    在所述第一区域(1011)和所述第二区域(1012)施加增厚介质层(1021)；
    在所述第三区域(1013)和所述增厚介质层(1021)外施加均厚层(1022)；以及
    移除所述第二区域(1012)外的所述均厚层(1022)和所述增厚介质层(1021)以暴露所述基底(101)的所述第二区域(1012)。
  11. 根据权利要求10所述的方法，其中施加增厚介质层(1021)包括：
    在整个所述基底(101)上施加所述增厚介质层(1021)；
    移除所述第三区域(1013)外的增厚介质层(1021)以暴露所述基底(101)的所述第三区域(1013)。
  12. 根据权利要求10所述的方法，其中施加增厚介质层(1021)包括：
    在所述基底(101)的所述第三区域(1013)施加光刻胶(106)；
    在所述基底(101)的所述第一区域(1011)和所述第二区域(1012)以及所述光刻胶(106)外施加增厚介质层(1021)；
    移除光刻胶(106)以暴露所述基底(101)的所述第三区域(1013)。
  13. 根据权利要求8或9所述的方法，其中施加所述第一介质层(102)和施加栅电极(103)包括：
    在整个所述基底(101)外施加所述均厚层(1022)；
    在所述均厚层(1022)外施加所述增厚介质层(1021)；
    移除所述第二区域(1012)外的所述均厚层(1022)和所述增厚介质层(1021)以暴露所述基底(101)的所述第二区域(1012)；
    施加栅电极(103)；以及
    利用栅电极(103)作为自对准掩膜移除所述第三区域(1013)外的所述增厚介质层(1021)。
  14. 根据权利要求8或9所述的方法，其中施加所述第一介质层(102)和施加栅电极(103)包括：
    在整个所述基底(101)外施加所述第一介质层(102)，所述第一介质层(102)具有第一厚度，所述第一厚度等于所述第一间距(D1)；
    移除所述第二区域(1012)外的所述第一介质层(102)以暴露所述基底(101)的所述第二区域(1012)；
    施加栅电极(103)；以及
    利用栅电极(103)作为自对准掩膜移除所述第三区域(1013)外的所述第一介质层(102)在厚度方向上的一部分，以使得在所述第三区域(1013)处的所述第一介质层(102)具有小于第一厚度的第二厚度，所述第二厚度等于所述第二间距(D2)。
PCT/CN2022/088735 2022-04-24 2022-04-24 半导体器件及其制备方法 WO2023205936A1 (zh)

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