CN117995877A - 晶体管结构及其制造方法 - Google Patents
晶体管结构及其制造方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 32
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000010410 layer Substances 0.000 claims abstract description 222
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 78
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 78
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 76
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 239000011241 protective layer Substances 0.000 claims abstract description 35
- 229910002601 GaN Inorganic materials 0.000 claims description 22
- 238000001039 wet etching Methods 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 238000000059 patterning Methods 0.000 claims description 18
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 16
- 238000001312 dry etching Methods 0.000 claims description 16
- 229910004205 SiNX Inorganic materials 0.000 claims description 2
- 238000002161 passivation Methods 0.000 claims 4
- 238000000151 deposition Methods 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 description 12
- 238000005530 etching Methods 0.000 description 11
- 230000003071 parasitic effect Effects 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910002704 AlGaN Inorganic materials 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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Abstract
本发明提供一种晶体管结构,包含基板、漏极、源极、保护层以及栅极。漏极和源极设置于基板上。保护层设置于基板上,且保护层介于漏极与源极之间。保护层包含氮化硅层以及氧化硅层,氧化硅层位于基板上,且氮化硅层位于氧化硅层上。保护层具有通孔延伸通过氮化硅层和氧化硅层。栅极设置于通孔内,且栅极与氧化硅层的至少一部分相分离而形成有空气间隙。
Description
技术领域
本发明关于一种晶体管结构及其制造方法。
背景技术
可作为宽带隙半导体材料的三族氮化物由于其高电子迁移率、高速度饱和大临界电场等优异特性,是次世代高速和高功率开关元件的优选半导体材料。现今,在四英寸至六英寸的硅晶圆上形成氮化铝镓/氮化镓(AlGaN/GaN)高电子移动率晶体管(HEMT)的制造技术已趋近成熟,且也证实使用AlGaN/GaN高电子移动率晶体管的射频功率开关元件展现能突破硅材料限制的优异性能。
然而,用在4英寸至6英寸晶圆的制造技术若转用于8英寸硅晶圆可能会产生问题。由于制程兼容性的限制,传统的掀离(Lift-off)制程不适用于8英寸至12英寸晶圆,所以会藉由干式蚀刻进行在8英寸晶圆上的金属沉积制程。然而,由于8英寸至12英寸晶圆容易弯曲和受限于蚀刻技术等因素,藉由干式蚀刻形成的栅极外型难以像掀离制程那样精确,而容易导致寄生电容产生。寄生电容会降低电流增益截止频率(Gaincut-offfrequency,fT),从而抑制功率增益截止频率率(powergaincut-offfrequency,fmax)。
为了能精确控制栅极的外型,一种解决方案为以干式蚀刻将作为保护层的氧化物或氮化物图案化以形成符合栅极外型的通孔,且随后可藉由金属沉积制程于通孔中形成栅极。然而,干式蚀刻容易损害作为基板的AlGaN/GaN基底层。
发明内容
鉴于上述问题,本发明提供一种晶体管结构及其制造方法,有助于解决寄生电容以及干式蚀刻容易损害AlGaN/GaN基底层的问题。
本发明一实施例所揭露的晶体管结构包含一基板、一漏极、一源极、一保护层以及一栅极。漏极和源极设置于基板上。保护层设置于基板上,且保护层介于漏极与源极之间。保护层包含氮化硅层以及氧化硅层,氧化硅层位于基板上,且氮化硅层位于氧化硅层上。保护层具有一通孔延伸通过氮化硅层和氧化硅层。栅极设置于通孔内,且栅极与氧化硅层的至少一部分相分离而形成有一空气间隙。
本发明另一实施例所揭露的晶体管结构的制造方法包含:形成一漏极和一源极于一基板上;形成一保护层于基板上且介于漏极与源极之间,保护层包含一氧化硅层以及至少一氮化硅层,且氧化硅层介于氮化硅层与基板之间;藉由干式蚀刻图案化氮化硅层且藉由湿式蚀刻图案化氧化硅层,以于保护层中形成一通孔以及一底切;以及形成一栅极于通孔内,且底切使栅极与氧化硅层的至少一部分相分离。
根据本发明揭露的内容,藉由藉由湿式蚀刻图案化的氧化硅层能形成底切。底切使栅极与氧化硅层的至少一部分相分离而形成空气间隙。空气间隙作为位于栅极周围的电介质层,能够有效降低栅极和漏极、源极之间的寄生电容,并且提升高频元件特性。
另外,在传统制程中,由于保护层的图案化如果采用干式蚀刻会损害基板的AlGaN层或GaN层而影响漏电流大小,因此会改采用较不会伤害到基板的湿式蚀刻,然而湿式蚀刻的等向性蚀刻性质无法让保护层在图案化后形成底切,且湿式蚀刻的时刻速率较难控制因而最后形成的栅极形状可能不符合预期。为了兼顾不伤害基板、精确控制栅极形状以及提供能降低寄生电容的空气间隙的多样需求,本发明的保护层包含位于基板上的氧化硅层以及位于氧化硅层上的氮化硅层,其中氮化硅层藉由干式蚀刻图案化以形成能精确定义栅极形状的通孔,且氧化硅层藉由湿式蚀刻图案化以形成上述的底切。
以下结合附图和具体实施例对本发明进行详细描述,但不作为对本发明的限定。
附图说明
图1为根据本发明一实施例的晶体管结构的示意图。
图2为图1的晶体管结构的局部放大示意图。
图3至图10为根据本发明一实施例的制造晶体管结构的流程示意图。
图11为根据本发明另一实施例的晶体管结构的示意图。
其中,附图标记:
1、2:晶体管结构
10:基板
110:硅层
120:氮化镓层
20:源极
30:漏极
40、40”:保护层
410:氧化硅层
411:侧面
412:开口
420:氮化硅层
421:第一氮化硅层
422:第二氮化硅层
430:通孔
440:底切
50、50”:栅极
510:脚部
520:头部
C1、C2:中心轴
D:延伸方向
G:空气间隙
W1、W2:宽度
S1、S2:距离
具体实施方式
下面结合附图对本发明的结构原理和工作原理作具体的描述:
请参照图1和图2,其中图1为根据本发明一实施例的晶体管结构的示意图,以及图2为图1的晶体管结构的局部放大示意图。在本实施例中,晶体管结构1例如但不限于是射频(RF)元件,其可包含基板10、源极20、漏极30、保护层40以及栅极50。
基板10可包含硅层110以及氮化镓层120,并且氮化镓层120设置于硅层110上。源极20和漏极30例如为金属电极,其可设置于基板10的氮化镓层120上。本实施例以氮化镓层120形成于硅层110上作为举例,但在其他实施例中可以是氮化铝镓层形成于硅层上。
保护层40可设置于基板10上,并且保护层40可介于源极20与漏极30之间。进一步来说,保护层40可包含氧化硅(SiOx)层410以及氮化硅(SiNx)层420。氧化硅层410位于基板10的氮化镓层120上,且氮化硅层420位于氧化硅层410上,也就是说氧化硅层410介于氮化硅层420与基板10的氮化镓层120之间。保护层40可具有通孔430延伸通过氮化硅层420和氧化硅层410。具体来说,可藉由干式蚀刻图案化氮化硅层420以及藉由湿式蚀刻图案化氧化硅层410,以形成保护层40的通孔430,并且经过湿式蚀刻处理的氧化硅层410的侧面411具有导角,例如具有圆滑导角。关于保护层40的蚀刻将于后续作进一步描述。
栅极50为金属电极,其至少一部分可设置于保护层40的通孔430内。进一步来说,栅极50为T型栅极(T-gate),其可包含脚部510以及头部520,并且头部520的宽度W2大于脚部510的宽度W1。脚部510位于保护层40的通孔430内,且头部520位于保护层40的氮化硅层420上。如图2所示,栅极50与氧化硅层410的至少一部分相分离而形成有空气间隙G。由于空气间隙G的形成,保护层40与源极20和漏极30相分离,且保护层40与栅极50实体接触。此外如图1所示,在基板10的延伸方向D上,栅极50与源极20的距离S1小于栅极50与漏极30的距离S2。关于空气间隙G的形成将于后续作进一步描述。
图1的晶体管结构1的制造方法可参照图3至图10,为根据本发明一实施例的制造晶体管结构的流程示意图。如图3和图4所示,在基板10上形成氧化硅层410。具体来说,可藉由例如等离子体增强化学气相沉积系统(Plasma-enhancedchemicalvapordeposition,PECVD)沉积氧化硅层410于基板10的氮化镓层120上,并且可进一步藉由例如PECVD形成第一氮化硅层421于氧化硅层410上。可藉由蚀刻制程图案化氧化硅层410和第一氮化硅层421以形成显露基板10的氮化镓层120的开口412。
接着,形成源极20和漏极30于基板10上。如图5所示,沉积金属层于开口412内以及氧化硅层410上,并且图案化位于第一氮化硅层421上的金属层,以形成源极20和漏极30。具体来说,可藉由溅镀制程形成填充开口412以及遍布第一氮化硅层421的上表面的金属层。所述金属层可选自由钛、铝、氮化钛和其组合所组成的群组。接着,可藉由蚀刻制程和微影制程图案化位于第一氮化硅层421的上表面的金属层,从而形成源极20和漏极30。
接着,形成保护层40于基板10上。如图6所示,可藉由例如PECVD形成第二氮化硅层422于第一氮化硅层421上,并且第二氮化硅层422可覆盖源极20和漏极30。第一氮化硅层421和第二氮化硅层422可被共同称作为氮化硅层420,并且氮化硅层420与氧化硅层410共同形成位于氮化镓层120上的保护层40。
接着,于保护层40中形成通孔430和底切(Undercut)440。如图7和图8所示,藉由干式蚀刻图案化第一氮化硅层421和第二氮化硅层422,并且藉由湿式蚀刻图案化氧化硅层410,从而形成通孔430以及底切440。在一实施方案中,可用缓冲氧化物蚀刻液(Bufferoxideetch,BOE)浸润氧化硅层410,以形成通孔430和底切440。在采用干式蚀刻的情况下,由于氮化硅相较于氧化硅具有较佳的非等向性蚀刻特性,因此经过干式蚀刻处理的氮化硅层420能形成有高深宽比的通孔430。另外,在采用湿式蚀刻的情况下,由于氧化硅相较于氮化硅具有较佳的等向性蚀刻特性,并且氮化硅的湿式蚀刻速率较慢,因此经过湿式蚀刻处理的氧化硅层410能形成有形状对称的底切440,并且通孔430的外型也不会有明显的变化。由于湿式蚀刻的特性,形成底切440的氧化硅层410的侧面呈现弧形且会具有圆滑的导角。
接着,形成栅极50于保护层40的通孔430内。如图9所示,可藉由溅镀制程沉积位于通孔430内以及遍布氮化硅层420的上表面的金属层。所述金属层可选自由钛、铝、氮化钛和其组合所组成的群组。接着,可藉由蚀刻制程和微影制程图案化位于氮化硅层420的上表面的金属层,从而形成栅极50。更进一步来说,位于通孔430内的金属层形成栅极50的脚部510,并且经图案化的位于氮化硅层420上的金属层形成栅极50的头部520。图8所示的底切440使栅极50的脚部510与氧化硅层410相分离而形成空气间隙G。空气间隙G作为位于栅极50周围的电介质层,能够有效降低栅极50和源极20、漏极30之间的寄生电容并且提升高频元件特性。
如图10所示,可藉由蚀刻制程和微影制程进一步图案化保护层40,以移除覆盖源极20和漏极30的氮化硅层420以及位于栅极50和源极20、漏极30之间的氧化硅层410和氮化硅层420,使得剩余的保护层40介于源极20与漏极30之间,并且使得保护层40与源极20和漏极30相分离。
在本实施例中,图3中氧化硅层410和第一氮化硅层421的形成、图4中氧化硅层410和第一氮化硅层421的图案化、图6中第二氮化硅层422的形成、图7中第一氮化硅层421和第二氮化硅层422的图案化、图8中氧化硅层410的图案化以及图10中氧化硅层410、第一氮化硅层421和第二氮化硅层422的图案化所组成的一连串步骤为本方法的保护层40的形成,其中在形成源极20和漏极30之前就已经形成氧化硅层410和第一氮化硅层421。然而,本发明并不限于以上述步骤形成保护层。
在一实施例中,不同于图3和图6中分别形成第一氮化硅层421和第二氮化硅层422,氮化硅层的形成可不需要分成两步骤。举例来说,可以在形成漏极和源极之前就形成氧化硅层和单一氮化硅层,并且在形成漏极和源极之后的步骤不需要再额外形成氮化硅层。
在一实施例中,不同于形成图4中的氧化硅层410和第一氮化硅层421之后再形成图5中的源极20和漏极30,保护层的各个层的形成可以在源极20和漏极30的形成之后。举例来说,可以直接沉积金属层于基板上并且图案化形成漏极和源极之后,再形成氧化硅层和氮化硅层。
在一实施例中,不同于形成栅极50之后还要再次对保护层40图案化以形成图10的构造,位于栅极50和源极20、漏极30之间的保护层40可以被保留。举例来说,形成栅极后的保护层的图案化可仅移除覆盖漏极、源极的顶部的部分氮化硅层。
图11为根据本发明另一实施例的晶体管结构的示意图。在本实施例中,晶体管结构2可包含基板10、源极20、漏极30、保护层40”以及栅极50”。关于基板10、源极20、漏极30的具体特征可参照图1至图2以及对应的前述内容,以下不再重复描述。
保护层40”可介于源极20与漏极30之间且可包含氧化硅层410以及氮化硅层420。保护层40可具有通孔430延伸通过氮化硅层420和氧化硅层410。此外,氮化硅层420和氧化硅层410与源极20、漏极30的侧面实体接触。
栅极50”可包含脚部510以及头部520。脚部510位于保护层40”的通孔430内,且头部520位于保护层40”的氮化硅层420上。栅极50与氧化硅层410的至少一部分相分离而形成有空气间隙G。此外,脚部510的中心轴C1可偏离头部520的中心轴C2,也就是说栅极50”可为L型栅极或是形状非对称的T型栅极。
综上所述,根据本发明揭露的晶体管结构及其制造方法,藉由藉由湿式蚀刻图案化的氧化硅层能形成底切。底切使栅极与氧化硅层的至少一部分相分离而形成空气间隙。空气间隙作为位于栅极周围的电介质层,能够有效降低栅极和漏极、源极之间的寄生电容,并且提升高频元件特性。
另外,在传统制程中,由于保护层的图案化如果采用干式蚀刻会损害基板的AlGaN层或GaN层而影响漏电流大小,因此会改采用对基板伤害性较低的湿式蚀刻进行保护层的图案化,然而湿式蚀刻的等向性蚀刻特性无法让保护层在图案化后形成底切,且湿式蚀刻的蚀刻速率较难控制因而最后形成的栅极外型可能不符合预期。为了兼顾不伤害基板、精确控制栅极形状以及提供能降低寄生电容的空气间隙的多种需求,本发明的保护层包含位于基板上的氧化硅层以及位于氧化硅层上的氮化硅层,其中氮化硅层藉由干式蚀刻图案化以形成能精确定义栅极形状的通孔,且氧化硅层藉由湿式蚀刻图案化以形成上述的底切。
当然,本发明还可有其它多种实施例,在不背离本发明精神及其实质的情况下,熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形,但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。
Claims (16)
1.一种晶体管结构,其特征在于,包含:
一基板;
一漏极和一源极,设置于该基板上;
一保护层,设置于该基板上,该保护层介于该漏极与该源极之间,该保护层包含一氮化硅层以及一氧化硅层,该氧化硅层位于该基板上,该氮化硅层位于该氧化硅层上,该保护层具有一通孔延伸通过该氮化硅层和该氧化硅层;以及
一栅极,设置于该通孔内,且该栅极与该氧化硅层的至少一部分相分离而形成有一空气间隙。
2.如权利要求1所述的晶体管结构,其特征在于,其中该基板包含一氮化镓层,且该漏极、该源极和该保护层皆设置于该氮化镓层上。
3.如权利要求1所述的晶体管结构,其特征在于,其中该保护层与该漏极和该源极相分离,且该保护层与该栅极实体接触。
4.如权利要求1所述的晶体管结构,其特征在于,其中藉由干式蚀刻图案化该氮化硅(SiNx)层以形成该通孔。
5.如权利要求1所述的晶体管结构,其特征在于,其中藉由湿式蚀刻图案化该氧化硅(SiOx)层以形成该通孔。
6.如权利要求1所述的晶体管结构,其特征在于,其中形成该空气间隙的该氧化硅层的侧面具有圆滑的导角。
7.如权利要求1所述的晶体管结构,其特征在于,其中在该基板的延伸方向上该栅极与该源极的距离小于该栅极与该漏极的距离。
8.如权利要求1所述的晶体管结构,其特征在于,其中该栅极包含一头部以及一脚部,该头部的宽度大于该脚部的宽度,该脚部位于该保护层的该通孔内,且该头部位于该氮化硅层上。
9.如权利要求8所述的晶体管结构,其特征在于,其中该脚部的中心轴偏离该头部的中心轴。
10.一种晶体管结构的制造方法,其特征在于,包含:
形成一漏极和一源极于一基板上;
形成一保护层于该基板上且介于该漏极与该源极之间,该保护层包含一氧化硅层以及至少一氮化硅层,且该氧化硅层介于该至少一氮化硅层与该基板之间;
藉由干式蚀刻图案化该至少一氮化硅层且藉由湿式蚀刻图案化该氧化硅层,以于该保护层中形成一通孔以及一底切;以及
形成一栅极于该通孔内,且该底切使该栅极与该氧化硅层的至少一部分相分离。
11.如权利要求10所述的晶体管结构的制造方法,其特征在于,其中该基板包含一氮化镓层,且该漏极、该源极和该保护层皆形成于该氮化镓层上。
12.如权利要求10所述的晶体管结构的制造方法,其特征在于,其中该保护层的形成包含:
形成该氧化硅层于该基板上;
形成一第一氮化硅层于该氧化硅层上;以及
于形成该漏极和该源极后,形成一第二氮化硅层于该第一氮化硅层上。
13.如权利要求12所述的晶体管结构的制造方法,其特征在于,其中于形成该漏极和该源极前形成该氧化硅层。
14.如权利要求10所述的晶体管结构的制造方法,其特征在于,其中藉由湿式蚀刻图案化该氧化硅层以形成该底切。
15.如权利要求10所述的晶体管结构的制造方法,其特征在于,其中该栅极的形成包含:
沉积一金属层于该通孔内以及该保护层上,且位于该通孔内的该金属层形成该栅极的一脚部;以及
图案化位于该保护层上的该金属层,以形成宽度大于该脚部的该栅极的一头部。
16.如权利要求10所述的晶体管结构的制造方法,其特征在于,其中该漏极和该源极的形成包含:
图案化该氧化硅层的部分以形成显露该基板的一开口;以及
沉积一金属层于该开口内以及该氧化硅层上;以及
图案化该金属层,以形成该漏极和该源极。
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