JP2009099956A5 - - Google Patents

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Publication number
JP2009099956A5
JP2009099956A5 JP2008231438A JP2008231438A JP2009099956A5 JP 2009099956 A5 JP2009099956 A5 JP 2009099956A5 JP 2008231438 A JP2008231438 A JP 2008231438A JP 2008231438 A JP2008231438 A JP 2008231438A JP 2009099956 A5 JP2009099956 A5 JP 2009099956A5
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JP
Japan
Prior art keywords
layer
cmos device
deformed
semiconductor
capping
Prior art date
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Pending
Application number
JP2008231438A
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English (en)
Japanese (ja)
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JP2009099956A (ja
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Publication date
Priority claimed from KR1020070104062A external-priority patent/KR20090038653A/ko
Application filed filed Critical
Publication of JP2009099956A publication Critical patent/JP2009099956A/ja
Publication of JP2009099956A5 publication Critical patent/JP2009099956A5/ja
Pending legal-status Critical Current

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JP2008231438A 2007-10-16 2008-09-09 Ｃｍｏｓ素子及びその製造方法 Pending JP2009099956A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070104062A KR20090038653A (ko) 2007-10-16 2007-10-16 Ｃｍｏｓ 소자 및 그 제조방법

Publications (2)

Publication Number Publication Date
JP2009099956A JP2009099956A (ja) 2009-05-07
JP2009099956A5 true JP2009099956A5 (enExample) 2011-09-22

Family

ID=40533314

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008231438A Pending JP2009099956A (ja) 2007-10-16 2008-09-09 Ｃｍｏｓ素子及びその製造方法

Country Status (4)

Country Link
US (1) US20090095981A1 (enExample)
JP (1) JP2009099956A (enExample)
KR (1) KR20090038653A (enExample)
CN (1) CN101414608A (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7790542B2 (en) * 2008-06-18 2010-09-07 International Business Machines Corporation CMOS devices having reduced threshold voltage variations and methods of manufacture thereof
US8395216B2 (en) * 2009-10-16 2013-03-12 Texas Instruments Incorporated Method for using hybrid orientation technology (HOT) in conjunction with selective epitaxy to form semiconductor devices with regions of different electron and hole mobilities and related apparatus
JP2011114160A (ja) * 2009-11-26 2011-06-09 Sumitomo Chemical Co Ltd 半導体基板、電子デバイスおよび半導体基板の製造方法
JP2011146691A (ja) * 2009-12-15 2011-07-28 Sumitomo Chemical Co Ltd 半導体基板、半導体デバイスおよび半導体基板の製造方法
KR101576203B1 (ko) 2010-01-18 2015-12-11 삼성전자주식회사 최적화된 채널 영역을 갖는 모스 트랜지스터들을 구비하는 반도체 소자들 및 그 제조방법들
CN102664166B (zh) * 2012-05-31 2013-11-27 中国科学院上海微系统与信息技术研究所 一种cmos器件及其制作方法
KR102083495B1 (ko) * 2013-01-07 2020-03-02 삼성전자 주식회사 Ｃｍｏｓ 소자와 이를 포함하는 광학장치와 그 제조방법
KR102069275B1 (ko) * 2013-06-07 2020-01-22 삼성전자주식회사 변형된 채널층을 갖는 반도체 소자 및 그 제조 방법
KR102210325B1 (ko) 2013-09-06 2021-02-01 삼성전자주식회사 Ｃｍｏｓ 소자 및 그 제조 방법
KR102104062B1 (ko) * 2013-10-31 2020-04-23 삼성전자 주식회사 기판 구조체, 이를 포함한 ｃｍｏｓ 소자 및 ｃｍｏｓ 소자 제조 방법
US9418841B2 (en) * 2014-12-30 2016-08-16 International Business Machines Corporation Type III-V and type IV semiconductor device formation
CN104992930A (zh) * 2015-07-07 2015-10-21 西安电子科技大学 应变Ge CMOS集成器件的制备方法及其CMOS集成器件
US9613871B2 (en) 2015-07-16 2017-04-04 Samsung Electronics Co., Ltd. Semiconductor device and fabricating method thereof
CN105244320A (zh) * 2015-08-28 2016-01-13 西安电子科技大学 基于SOI的应变Ge沟道倒梯形栅CMOS集成器件及制备方法
CN105118809A (zh) * 2015-08-28 2015-12-02 西安电子科技大学 应变Ge槽型栅CMOS集成器件制备方法及其CMOS集成器件
US10062693B2 (en) * 2016-02-24 2018-08-28 International Business Machines Corporation Patterned gate dielectrics for III-V-based CMOS circuits
US10593600B2 (en) 2016-02-24 2020-03-17 International Business Machines Corporation Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap
CN108257916B (zh) * 2016-12-28 2020-07-10 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6254459A (ja) * 1985-09-02 1987-03-10 Seiko Epson Corp 相補型電界効果トランジスタ
JP2000216347A (ja) * 1999-01-20 2000-08-04 Toshiba Corp Ｃｍｏｓ半導体装置
JP4521542B2 (ja) * 1999-03-30 2010-08-11 ルネサスエレクトロニクス株式会社 半導体装置および半導体基板
US7662689B2 (en) * 2003-12-23 2010-02-16 Intel Corporation Strained transistor integration for CMOS
US7244958B2 (en) * 2004-06-24 2007-07-17 International Business Machines Corporation Integration of strained Ge into advanced CMOS technology
JP4604637B2 (ja) * 2004-10-07 2011-01-05 ソニー株式会社 半導体装置および半導体装置の製造方法
US7282402B2 (en) * 2005-03-30 2007-10-16 Freescale Semiconductor, Inc. Method of making a dual strained channel semiconductor device
TWI258172B (en) * 2005-08-24 2006-07-11 Ind Tech Res Inst Transistor device with strained Ge layer by selectively grown and fabricating method thereof

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