JP2008529302A5 - - Google Patents

Download PDF

Info

Publication number
JP2008529302A5
JP2008529302A5 JP2007553101A JP2007553101A JP2008529302A5 JP 2008529302 A5 JP2008529302 A5 JP 2008529302A5 JP 2007553101 A JP2007553101 A JP 2007553101A JP 2007553101 A JP2007553101 A JP 2007553101A JP 2008529302 A5 JP2008529302 A5 JP 2008529302A5
Authority
JP
Japan
Prior art keywords
strain
substrate
type
region
device region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007553101A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008529302A (ja
Filing date
Publication date
Priority claimed from US10/905,945 external-priority patent/US20060163670A1/en
Application filed filed Critical
Publication of JP2008529302A publication Critical patent/JP2008529302A/ja
Publication of JP2008529302A5 publication Critical patent/JP2008529302A5/ja
Pending legal-status Critical Current

Links

JP2007553101A 2005-01-27 2005-12-21 デバイス性能を改善するためのデュアル・シリサイド・プロセス Pending JP2008529302A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/905,945 US20060163670A1 (en) 2005-01-27 2005-01-27 Dual silicide process to improve device performance
PCT/US2005/046097 WO2006081012A1 (en) 2005-01-27 2005-12-21 Dual silicide process to improve device performance

Publications (2)

Publication Number Publication Date
JP2008529302A JP2008529302A (ja) 2008-07-31
JP2008529302A5 true JP2008529302A5 (enExample) 2008-10-16

Family

ID=36695883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007553101A Pending JP2008529302A (ja) 2005-01-27 2005-12-21 デバイス性能を改善するためのデュアル・シリサイド・プロセス

Country Status (6)

Country Link
US (1) US20060163670A1 (enExample)
EP (1) EP1842235A4 (enExample)
JP (1) JP2008529302A (enExample)
CN (1) CN100533709C (enExample)
TW (1) TW200627528A (enExample)
WO (1) WO2006081012A1 (enExample)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006344713A (ja) * 2005-06-08 2006-12-21 Renesas Technology Corp 半導体装置およびその製造方法
DE102005030583B4 (de) * 2005-06-30 2010-09-30 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung von Kontaktisolationsschichten und Silizidgebieten mit unterschiedlichen Eigenschaften eines Halbleiterbauelements und Halbleiterbauelement
JP4880958B2 (ja) * 2005-09-16 2012-02-22 株式会社東芝 半導体装置及びその製造方法
JP2007101213A (ja) * 2005-09-30 2007-04-19 Ricoh Co Ltd 半導体装置、赤外線センサ、及び半導体装置の製造方法
JP4247257B2 (ja) * 2006-08-29 2009-04-02 株式会社東芝 半導体装置の製造方法
US20080070360A1 (en) * 2006-09-19 2008-03-20 International Business Machines Corporation Method and structure for forming silicide contacts on embedded silicon germanium regions of cmos devices
DE102006051494B4 (de) * 2006-10-31 2009-02-05 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Ausbilden einer Halbleiterstruktur, die einen Feldeffekt-Transistor mit verspanntem Kanalgebiet umfasst
WO2008061258A2 (en) * 2006-11-17 2008-05-22 Sachem, Inc. Selective metal wet etch composition and process
US8039284B2 (en) * 2006-12-18 2011-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Dual metal silicides for lowering contact resistance
TW200910526A (en) * 2007-07-03 2009-03-01 Renesas Tech Corp Method of manufacturing semiconductor device
US8263466B2 (en) * 2007-10-17 2012-09-11 Acorn Technologies, Inc. Channel strain induced by strained metal in FET source or drain
US7615831B2 (en) * 2007-10-26 2009-11-10 International Business Machines Corporation Structure and method for fabricating self-aligned metal contacts
US7964923B2 (en) 2008-01-07 2011-06-21 International Business Machines Corporation Structure and method of creating entirely self-aligned metallic contacts
US7749847B2 (en) * 2008-02-14 2010-07-06 International Business Machines Corporation CMOS integration scheme employing a silicide electrode and a silicide-germanide alloy electrode
JP4770885B2 (ja) * 2008-06-30 2011-09-14 ソニー株式会社 半導体装置
JP5769160B2 (ja) * 2008-10-30 2015-08-26 国立大学法人東北大学 コンタクト形成方法、半導体装置の製造方法、および半導体装置
DE102010004230A1 (de) 2009-01-23 2010-10-14 Qimonda Ag Integrierter Schaltkreis mit Kontaktstrukturen für P- und N-Dotierte Gebiete und Verfahren zu dessen Herstellung
JP5493849B2 (ja) * 2009-12-28 2014-05-14 株式会社リコー 温度センサーとそれを用いた生体検知装置
US8278200B2 (en) 2011-01-24 2012-10-02 International Business Machines Corpration Metal-semiconductor intermixed regions
JP4771024B2 (ja) * 2011-04-15 2011-09-14 ソニー株式会社 半導体装置の製造方法
WO2013150571A1 (ja) * 2012-04-06 2013-10-10 国立大学法人東北大学 半導体装置
US8866195B2 (en) * 2012-07-06 2014-10-21 Taiwan Semiconductor Manufacturing Co., Ltd. III-V compound semiconductor device having metal contacts and method of making the same
US20140048888A1 (en) * 2012-08-17 2014-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained Structure of a Semiconductor Device
US9601630B2 (en) 2012-09-25 2017-03-21 Stmicroelectronics, Inc. Transistors incorporating metal quantum dots into doped source and drain regions
US9748356B2 (en) 2012-09-25 2017-08-29 Stmicroelectronics, Inc. Threshold adjustment for quantum dot array devices with metal source and drain
KR20140101218A (ko) 2013-02-08 2014-08-19 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9508716B2 (en) * 2013-03-14 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing a semiconductor device
US10002938B2 (en) 2013-08-20 2018-06-19 Stmicroelectronics, Inc. Atomic layer deposition of selected molecular clusters
US9093424B2 (en) 2013-12-18 2015-07-28 International Business Machines Corporation Dual silicide integration with laser annealing
US9177810B2 (en) 2014-01-29 2015-11-03 International Business Machines Corporation Dual silicide regions and method for forming the same
KR102236555B1 (ko) 2014-11-11 2021-04-06 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9390981B1 (en) 2015-02-05 2016-07-12 Globalfoundries Inc. Method of forming a complementary metal oxide semiconductor structure with N-type and P-type field effect transistors having symmetric source/drain junctions and optional dual silicides
US9564372B2 (en) 2015-06-16 2017-02-07 International Business Machines Corporation Dual liner silicide
US9520363B1 (en) 2015-08-19 2016-12-13 International Business Machines Corporation Forming CMOSFET structures with different contact liners
US9768077B1 (en) 2016-06-02 2017-09-19 International Business Machines Corporation Low resistance dual liner contacts for Fin Field-Effect Transistors (FinFETs)
US10388576B2 (en) 2016-06-30 2019-08-20 International Business Machines Corporation Semiconductor device including dual trench epitaxial dual-liner contacts
US11158543B2 (en) 2019-07-09 2021-10-26 International Business Machines Corporation Silicide formation for source/drain contact in a vertical transport field-effect transistor
US11348839B2 (en) 2019-07-31 2022-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor devices with multiple silicide regions
US11164947B2 (en) 2020-02-29 2021-11-02 International Business Machines Corporation Wrap around contact formation for VTFET
US11615990B2 (en) 2020-03-24 2023-03-28 International Business Machines Corporation CMOS top source/drain region doping and epitaxial growth for a vertical field effect transistor
TW202335094A (zh) * 2022-02-22 2023-09-01 美商應用材料股份有限公司 用於可靠低接觸電阻之導電氧矽化物

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3095564B2 (ja) * 1992-05-29 2000-10-03 株式会社東芝 半導体装置及び半導体装置の製造方法
US5668024A (en) * 1996-07-17 1997-09-16 Taiwan Semiconductor Manufacturing Company CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation process
US5952701A (en) * 1997-08-18 1999-09-14 National Semiconductor Corporation Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value
US6087225A (en) * 1998-02-05 2000-07-11 International Business Machines Corporation Method for dual gate oxide dual workfunction CMOS
US6130123A (en) * 1998-06-30 2000-10-10 Intel Corporation Method for making a complementary metal gate electrode technology
US6204103B1 (en) * 1998-09-18 2001-03-20 Intel Corporation Process to make complementary silicide metal gates for CMOS technology
JP2000286411A (ja) * 1999-03-29 2000-10-13 Toshiba Corp 半導体装置とその製造方法
JP2000349169A (ja) * 1999-06-09 2000-12-15 Toshiba Corp 半導体装置及びその製造方法
US20030235936A1 (en) * 1999-12-16 2003-12-25 Snyder John P. Schottky barrier CMOS device and method
US6380024B1 (en) * 2000-02-07 2002-04-30 Taiwan Semiconductor Manufacturing Company Method of fabricating an SRAM cell featuring dual silicide gates and four buried contact regions
US6391767B1 (en) * 2000-02-11 2002-05-21 Advanced Micro Devices, Inc. Dual silicide process to reduce gate resistance
US6548842B1 (en) * 2000-03-31 2003-04-15 National Semiconductor Corporation Field-effect transistor for alleviating short-channel effects
JP3833903B2 (ja) * 2000-07-11 2006-10-18 株式会社東芝 半導体装置の製造方法
JP3906020B2 (ja) * 2000-09-27 2007-04-18 株式会社東芝 半導体装置及びその製造方法
US6468900B1 (en) * 2000-12-06 2002-10-22 Advanced Micro Devices, Inc. Dual layer nickel deposition using a cobalt barrier to reduce surface roughness at silicide/junction interface
JP2002289697A (ja) * 2001-03-27 2002-10-04 Toshiba Corp 相補型絶縁ゲート型トランジスタ
US6509609B1 (en) * 2001-06-18 2003-01-21 Motorola, Inc. Grooved channel schottky MOSFET
JP2003168740A (ja) * 2001-09-18 2003-06-13 Sanyo Electric Co Ltd 半導体装置および半導体装置の製造方法
EP1479102B1 (en) * 2002-02-28 2010-08-11 Advanced Micro Devices, Inc. Method of forming different silicide portions on different silicon-containing regions in a semiconductor device
DE10208904B4 (de) * 2002-02-28 2007-03-01 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung unterschiedlicher Silicidbereiche auf verschiedenen Silicium enthaltenden Gebieten in einem Halbleiterelement
DE10209059B4 (de) * 2002-03-01 2007-04-05 Advanced Micro Devices, Inc., Sunnyvale Ein Halbleiterelement mit unterschiedlichen Metall-Halbleiterbereichen, die auf einem Halbleitergebiet gebildet sind, und Verfahren zur Herstellung des Halbleiterelements
US6787864B2 (en) * 2002-09-30 2004-09-07 Advanced Micro Devices, Inc. Mosfets incorporating nickel germanosilicided gate and methods for their formation
JP4197607B2 (ja) * 2002-11-06 2008-12-17 株式会社東芝 絶縁ゲート型電界効果トランジスタを含む半導体装置の製造方法
US6869866B1 (en) * 2003-09-22 2005-03-22 International Business Machines Corporation Silicide proximity structures for CMOS device performance improvements
US20050156208A1 (en) * 2003-09-30 2005-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Device having multiple silicide types and a method for its fabrication
US6977194B2 (en) * 2003-10-30 2005-12-20 International Business Machines Corporation Structure and method to improve channel mobility by gate electrode stress modification
JP2005209782A (ja) * 2004-01-21 2005-08-04 Toshiba Corp 半導体装置

Similar Documents

Publication Publication Date Title
JP2008529302A5 (enExample)
JP2008504680A5 (enExample)
TW200627528A (en) Dual silicide process to improve device performance
SG139657A1 (en) Structure and method to implement dual stressor layers with improved silicide control
JP2009060096A5 (enExample)
TW200629477A (en) Single metal gate CMOS device
TW200618122A (en) MOSFET structure with multiple self-aligned silicide contacts
JP2010171243A5 (enExample)
WO2010051133A3 (en) Semiconductor devices having faceted silicide contacts, and related fabrication methods
WO2009012295A3 (en) Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure
JP2009267021A5 (enExample)
TW200802803A (en) Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions
WO2008127643A3 (en) Strain enhanced semiconductor devices and methods for their fabrication
WO2005101515A3 (en) Process to improve transistor drive current through the use of strain
JP2009158853A5 (enExample)
WO2007092867A3 (en) Semiconductor device fabricated using a raised layer to silicide the gate
TW200509259A (en) Highly integrated semiconductor device with silicide layer that secures contact margin and method of manufacturing the same
JP2004214673A5 (enExample)
TW200631065A (en) Strained transistor with hybrid-strain inducing layer
TW200725756A (en) Method for forming a semiconductor structure and structure thereof
TW200642080A (en) A novel semiconductor device with improved channel strain effect
TW200633209A (en) Semiconductor device having transistor with vertical gate electrode and method of fabricating the same
JP2005072566A5 (enExample)
JP2011142190A5 (enExample)
EP3945597A3 (en) Contact structures in semiconductor devices