JP2008529302A - デバイス性能を改善するためのデュアル・シリサイド・プロセス - Google Patents

デバイス性能を改善するためのデュアル・シリサイド・プロセス Download PDF

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Publication number
JP2008529302A
JP2008529302A JP2007553101A JP2007553101A JP2008529302A JP 2008529302 A JP2008529302 A JP 2008529302A JP 2007553101 A JP2007553101 A JP 2007553101A JP 2007553101 A JP2007553101 A JP 2007553101A JP 2008529302 A JP2008529302 A JP 2008529302A
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Prior art keywords
silicide
substrate
device region
metal
type
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Pending
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JP2007553101A
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Japanese (ja)
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JP2008529302A5 (enExample
Inventor
エリス−モナハン、ジョン、ジェイ
マーティン、デイル、ダブリュー
マーフィー、ウィリアム、ジェイ
ナコス、ジェームズ・エス
ピーターソン、カーク
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International Business Machines Corp
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International Business Machines Corp
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Publication of JP2008529302A publication Critical patent/JP2008529302A/ja
Publication of JP2008529302A5 publication Critical patent/JP2008529302A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/794—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising conductive materials, e.g. silicided source, drain or gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0174—Manufacturing their gate conductors the gate conductors being silicided
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2007553101A 2005-01-27 2005-12-21 デバイス性能を改善するためのデュアル・シリサイド・プロセス Pending JP2008529302A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/905,945 US20060163670A1 (en) 2005-01-27 2005-01-27 Dual silicide process to improve device performance
PCT/US2005/046097 WO2006081012A1 (en) 2005-01-27 2005-12-21 Dual silicide process to improve device performance

Publications (2)

Publication Number Publication Date
JP2008529302A true JP2008529302A (ja) 2008-07-31
JP2008529302A5 JP2008529302A5 (enExample) 2008-10-16

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JP2007553101A Pending JP2008529302A (ja) 2005-01-27 2005-12-21 デバイス性能を改善するためのデュアル・シリサイド・プロセス

Country Status (6)

Country Link
US (1) US20060163670A1 (enExample)
EP (1) EP1842235A4 (enExample)
JP (1) JP2008529302A (enExample)
CN (1) CN100533709C (enExample)
TW (1) TW200627528A (enExample)
WO (1) WO2006081012A1 (enExample)

Cited By (2)

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WO2010050405A1 (ja) * 2008-10-30 2010-05-06 国立大学法人東北大学 コンタクト形成方法、半導体装置の製造方法、および半導体装置
WO2013150571A1 (ja) * 2012-04-06 2013-10-10 国立大学法人東北大学 半導体装置

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US8039284B2 (en) * 2006-12-18 2011-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Dual metal silicides for lowering contact resistance
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US7615831B2 (en) * 2007-10-26 2009-11-10 International Business Machines Corporation Structure and method for fabricating self-aligned metal contacts
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US7749847B2 (en) * 2008-02-14 2010-07-06 International Business Machines Corporation CMOS integration scheme employing a silicide electrode and a silicide-germanide alloy electrode
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JP4771024B2 (ja) * 2011-04-15 2011-09-14 ソニー株式会社 半導体装置の製造方法
US8866195B2 (en) * 2012-07-06 2014-10-21 Taiwan Semiconductor Manufacturing Co., Ltd. III-V compound semiconductor device having metal contacts and method of making the same
US20140048888A1 (en) * 2012-08-17 2014-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained Structure of a Semiconductor Device
US9601630B2 (en) 2012-09-25 2017-03-21 Stmicroelectronics, Inc. Transistors incorporating metal quantum dots into doped source and drain regions
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US9520363B1 (en) 2015-08-19 2016-12-13 International Business Machines Corporation Forming CMOSFET structures with different contact liners
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Publication number Priority date Publication date Assignee Title
WO2010050405A1 (ja) * 2008-10-30 2010-05-06 国立大学法人東北大学 コンタクト形成方法、半導体装置の製造方法、および半導体装置
JP2010109143A (ja) * 2008-10-30 2010-05-13 Tohoku Univ コンタクト形成方法、半導体装置の製造方法、および半導体装置
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WO2013150571A1 (ja) * 2012-04-06 2013-10-10 国立大学法人東北大学 半導体装置
JPWO2013150571A1 (ja) * 2012-04-06 2015-12-14 国立大学法人東北大学 半導体装置

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Publication number Publication date
TW200627528A (en) 2006-08-01
EP1842235A4 (en) 2009-03-25
EP1842235A1 (en) 2007-10-10
US20060163670A1 (en) 2006-07-27
WO2006081012A1 (en) 2006-08-03
CN100533709C (zh) 2009-08-26
CN101124671A (zh) 2008-02-13

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