JP2008538859A - 集積回路に関する応力下でのインターレイヤー誘電体 - Google Patents
集積回路に関する応力下でのインターレイヤー誘電体 Download PDFInfo
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- 239000011229 interlayer Substances 0.000 title abstract description 6
- 230000003068 static effect Effects 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims description 65
- 238000000151 deposition Methods 0.000 claims description 14
- 230000006835 compression Effects 0.000 claims description 10
- 238000007906 compression Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims 4
- 238000003491 array Methods 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 62
- 239000007943 implant Substances 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- 238000005530 etching Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
Claims (20)
- 第1のNチャネルトランジスタおよび第1のPチャネルトランジスタを包含する論理部分と、
第2のNチャネルトランジスタおよび第2のPチャネルトランジスタを包含する静的ランダムアクセスメモリ(SRAM)アレイ部分と、
圧縮応力を備えた第1のPチャネルトランジスタの上に第1のILDと、
前記第1のILDの圧縮応力よりも少なくとも小さい圧縮である応力を備えた前記第2のPチャネルトランジスタの上に第2のILDと、
を有することを特徴とする半導体デバイス。 - 前記第1のILDおよび第2のILDが、異なる応力の窒化シリコンからなることを特徴とする請求項1に記載の半導体デバイス。
- 前記第2のPチャネルトランジスタが、SRAMアレイにおいてプルトランジスタとして昨日することを特徴とする請求項1に記載の半導体デバイス。
- 前記第2のILDが、前記第1および第2のNチャネルトランジスタの上にあることを特徴とする請求項1に記載の半導体デバイス。
- 引っ張り応力を備えた前記第1および第2のNチャネルトランジスタの上に第3のILDを更に有することを特徴とする請求項1に記載の半導体デバイス。
- 前記第2のILDの応力が、圧縮であることを特徴とする請求項1に記載の半導体デバイス。
- 前記第2のILDの応力が、緩和されることを特徴とする請求項1に記載の半導体デバイス。
- 前記第2のILDの応力が、引っ張りであることを特徴とする請求項1に記載の半導体デバイス。
- 前記第2のILDよりも大きな引っ張りである引っ張り応力を備えた前記第1および第2のNチャネルトランジスタの上に第3のILDを更に有することを特徴とする請求項8に記載の半導体デバイス。
- 第1のタイプの第1のトランジスタと、第1のタイプの回路に使用するための第2のタイプの第1のトランジスタとを有する第1の部分と、
前記第1のタイプの第2のトランジスタと、第2のタイプの回路に使用するための第2のタイプの第2のトランジスタとを有する第2の部分と、
第1のタイプの第1の応力を備えた第1のタイプの第1のトランジスタの上にある第1のILDと、
前記第1のタイプの第1の応力よりも少なくとも小さい第2の応力を備えた第1のタイプの第2のトランジスタの上にある第2のILDと
を有することを特徴とする半導体デバイス。 - 前記第1のタイプの第1のトランジスタと第1のタイプの第2のトランジスタがPチャネルトランジスタであり、
前記第1のタイプの第1の応力が圧縮である
ことを特徴とする請求項10に記載の半導体デバイス。 - 前記第1のタイプの回路が、論理回路であり、前記第2のタイプの回路がSRAMアレイである、ことを特徴とする請求項11に記載の半導体デバイス。
- 前記第1のタイプの第2のトランジスタが、SRAMアレイのプルアップトランジスタであることを特徴とする請求項12に記載の半導体デバイス。
- 引っ張り応力を備えた前記第2のタイプの第2のトランジスタおよび第1のトランジスタの上に第3のILDを更に有することを特徴とする請求項13に記載の半導体デバイス。
- 第2のILDが、前記第2のタイプの第2のトランジスタおよび第1のトランジスタの上にあることを特徴とする請求項13に記載の半導体デバイス。
- 半導体デバイスを製造する方法であって、
論理回路に使用される第1のNチャネルトランジスタを形成するステップと、
前記論理回路に使用される第1のPチャネルトランジスとを形成するステップと、
SRAMアレイに使用される第2のNチャネルトランジスタを形成するステップと、
前記SRAMアレイに使用される第2のPチャネルトランジスタを形成するステップと、
前記半導体デバイスの上に第1の応力を備える第1の誘電層を堆積するステップと、
前記第1のPチャネルトランジスタの上の第1の誘電層を除去するステップと、
前記半導体デバイスの上に前記第1の応力よりも大きな圧縮である第2の応力を備える第2の誘電層を堆積させるステップと、
前記第1および第2のNチャネルトランジスタおよび第2のPチャネルトランジスタの上の前記第2の誘電層を除去するステップと
を有することを特徴とする方法。 - 前記第1の応力が引っ張りであり、
前記第1の誘電層の第1の部分をより小さな引っ張りになるように、前記第2のPチャネルトランジスタの上にある前記第1の誘電層の第1の部分内に打ち込みをするステップを更に有することを特徴とする請求項16に記載の方法。 - 半導体デバイスを製造する方法であって、
論理回路に使用される第1のNチャネルトランジスタを形成するステップと、
前記論理回路に使用される第1のPチャネルトランジスタを形成するステップと、
SRAMアレイに使用される第2のNチャネルトランジスタを形成するステップと、
前記SRAMアレイに使用される第2のPチャネルトランジスタを形成するステップと、
前記半導体デバイスの上に第1の応力を備える第1の誘電層を堆積するステップと、
前記第1および第2のPチャネルトランジスタの上の前記誘電層を除去するステップと、
前記半導体デバイスの上に前記第1の応力よりも大きな圧縮である第2の応力を備える第2の誘電層を堆積するステップと、
前記第1および第2のNチャネルトランジスタおよび第2のPチャネルトランジスタの上の前記第2の層を除去するステップと、
前記半導体デバイスの上に、前記第1の応力と第2の応力との間である第3の応力を備える第3の誘電層を堆積するステップと、
前記第1および第2のNチャネルトランジスタおよび第1のPチャネルトランジスタの上の前記第3の誘電層を除去するステップと
を有することを特徴とする方法。 - 半導体デバイスを製造する方法であって、
論理回路に使用される第1のNチャネルトランジスタを形成するステップと、
前記論理回路に使用される第1のPチャネルトランジスタを形成するステップと、
SRAMアレイに使用される第2のNチャネルトランジスタを形成するステップと、
前記SRAMアレイに使用される第2のPチャネルトランジスタを形成するステップと、
前記半導体デバイスの上に、第1の応力を備える第1の誘電層を堆積させるステップと、
前記第1および第2のPチャネルトランジスタの上の前記第1の誘電層を除去するステップと、
前記半導体デバイスの上に、前記第1の応力よりも大きな圧縮である第2の応力を備えた第2の誘電層を堆積させるステップと、
前記第1および第2のNチャネルトランジスタの上の第2の誘電層を除去するステップであって、前記第2の誘電層の第1の部分が前記第1のPチャネルトランジスタの上に残り、前記第2の誘電層の第2の部分が前記第2のPチャネルトランジスタの上に残ることを特徴とする、ステップと、
前記第2の誘電層の前記第2の部分がより小さな圧縮となるように、前記第2の誘電層の第2の部分内に打ち込みをするステップと
を有することを特徴とする方法。 - 半導体デバイスを製造する方法であって、
第1のタイプの第1のトランジスタおよび第1のタイプの回路に使用するための第2のタイプの第1のトランジスタを備えた第1の部分を形成するステップと、
第1のタイプの第2のトランジスタおよび第2のタイプの回路に使用するための第2のタイプの第2のトランジスタを備えた第2の部分を形成するステップと、
第1のタイプの第1の応力を備えた第1のタイプの第1のトランジスタの上に第1のILDを形成するステップと、
第1のタイプの第1の応力よりも少なくとも小さな第2の応力を備えた第1のタイプの第2のトランジスタの上に第2のILDを形成するステップと
を有すること特徴とする方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/100,168 US7238990B2 (en) | 2005-04-06 | 2005-04-06 | Interlayer dielectric under stress for an integrated circuit |
US11/100,168 | 2005-04-06 | ||
PCT/US2006/005369 WO2006107413A2 (en) | 2005-04-06 | 2006-02-16 | Interlayer dielectric under stress for an integrated circuit |
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EP (1) | EP1869708A4 (ja) |
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KR (1) | KR101221345B1 (ja) |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007027194A (ja) * | 2005-07-12 | 2007-02-01 | Renesas Technology Corp | 半導体装置 |
JP2012523112A (ja) * | 2009-04-01 | 2012-09-27 | コミサリア ア レネルジ アトミク エ オウ エネルジ アルタナティヴ | 明白に異なる閾値電圧を有するトランジスタを持つsoiから製造する集積回路 |
JP2013229597A (ja) * | 2012-04-25 | 2013-11-07 | Samsung Electronics Co Ltd | 応力近接効果を有する集積回路 |
Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7419250B2 (en) * | 1999-10-15 | 2008-09-02 | Silverbrook Research Pty Ltd | Micro-electromechanical liquid ejection device |
ATE367927T1 (de) | 1998-10-16 | 2007-08-15 | Silverbrook Res Pty Ltd | Verfahren zur herstellung einer düse für einen tintenstrahldruckkopf |
JP2003100902A (ja) | 2001-09-21 | 2003-04-04 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
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US8633537B2 (en) | 2007-05-25 | 2014-01-21 | Cypress Semiconductor Corporation | Memory transistor with multiple charge storing layers and a high work function gate electrode |
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US20090179253A1 (en) | 2007-05-25 | 2009-07-16 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
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US9449831B2 (en) | 2007-05-25 | 2016-09-20 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
US8643124B2 (en) | 2007-05-25 | 2014-02-04 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
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DE102007025342B4 (de) * | 2007-05-31 | 2011-07-28 | Globalfoundries Inc. | Höheres Transistorleistungsvermögen von N-Kanaltransistoren und P-Kanaltransistoren durch Verwenden einer zusätzlichen Schicht über einer Doppelverspannungsschicht |
US7915681B2 (en) | 2007-06-18 | 2011-03-29 | Infineon Technologies Ag | Transistor with reduced charge carrier mobility |
DE102007052051B4 (de) * | 2007-10-31 | 2012-09-20 | Advanced Micro Devices, Inc. | Herstellung verspannungsinduzierender Schichten über einem Bauteilgebiet mit dichtliegenden Transistorelementen |
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US7727834B2 (en) * | 2008-02-14 | 2010-06-01 | Toshiba America Electronic Components, Inc. | Contact configuration and method in dual-stress liner semiconductor device |
DE102008011814B4 (de) | 2008-02-29 | 2012-04-26 | Advanced Micro Devices, Inc. | CMOS-Bauelement mit vergrabener isolierender Schicht und verformten Kanalgebieten sowie Verfahren zum Herstellen derselben |
US7977202B2 (en) * | 2008-05-02 | 2011-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing device performance drift caused by large spacings between active regions |
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US8723827B2 (en) | 2009-07-28 | 2014-05-13 | Cypress Semiconductor Corporation | Predictive touch surface scanning |
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US10597769B2 (en) | 2017-04-05 | 2020-03-24 | International Business Machines Corporation | Method of fabricating a magnetic stack arrangement of a laminated magnetic inductor |
US10347411B2 (en) | 2017-05-19 | 2019-07-09 | International Business Machines Corporation | Stress management scheme for fabricating thick magnetic films of an inductor yoke arrangement |
CN109713040A (zh) * | 2018-12-20 | 2019-05-03 | 中国科学院微电子研究所 | 一种集成电路结构 |
CN109829240B (zh) * | 2019-02-19 | 2023-01-24 | 中国科学院微电子研究所 | 一种集成电路性能的优化方法 |
CN113611672A (zh) * | 2021-06-18 | 2021-11-05 | 联芯集成电路制造(厦门)有限公司 | 形成半导体元件的方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002043151A1 (en) * | 2000-11-22 | 2002-05-30 | Hitachi, Ltd | Semiconductor device and method for fabricating the same |
JP2004165197A (ja) * | 2002-11-08 | 2004-06-10 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
JP2006237070A (ja) * | 2005-02-22 | 2006-09-07 | Sony Corp | 半導体集積回路の製造方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19535629C1 (de) * | 1995-09-25 | 1996-09-12 | Siemens Ag | Verfahren zur Herstellung einer integrierten CMOS-Schaltung |
JP3560480B2 (ja) * | 1998-10-05 | 2004-09-02 | シャープ株式会社 | スタティック・ランダム・アクセスメモリ |
JP2001015704A (ja) * | 1999-06-29 | 2001-01-19 | Hitachi Ltd | 半導体集積回路 |
US6580136B2 (en) * | 2001-01-30 | 2003-06-17 | International Business Machines Corporation | Method for delineation of eDRAM support device notched gate |
DE10222083B4 (de) * | 2001-05-18 | 2010-09-23 | Samsung Electronics Co., Ltd., Suwon | Isolationsverfahren für eine Halbleitervorrichtung |
JP2003060076A (ja) * | 2001-08-21 | 2003-02-28 | Nec Corp | 半導体装置及びその製造方法 |
JP4173672B2 (ja) * | 2002-03-19 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
US6882025B2 (en) * | 2003-04-25 | 2005-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained-channel transistor and methods of manufacture |
US7301206B2 (en) * | 2003-08-01 | 2007-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors |
US6982196B2 (en) * | 2003-11-04 | 2006-01-03 | International Business Machines Corporation | Oxidation method for altering a film structure and CMOS transistor structure formed therewith |
US20050214998A1 (en) * | 2004-03-26 | 2005-09-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Local stress control for CMOS performance enhancement |
KR101025761B1 (ko) * | 2004-03-30 | 2011-04-04 | 삼성전자주식회사 | 디지탈 회로 및 아날로그 회로를 가지는 반도체 집적회로및 그 제조 방법 |
US20050266632A1 (en) * | 2004-05-26 | 2005-12-01 | Yun-Hsiu Chen | Integrated circuit with strained and non-strained transistors, and method of forming thereof |
DE102004026149B4 (de) * | 2004-05-28 | 2008-06-26 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Erzeugen eines Halbleiterbauelements mit Transistorelementen mit spannungsinduzierenden Ätzstoppschichten |
US7348284B2 (en) * | 2004-08-10 | 2008-03-25 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
-
2005
- 2005-04-06 US US11/100,168 patent/US7238990B2/en not_active Expired - Fee Related
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-
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-
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- 2010-04-01 US US12/752,699 patent/US20100190354A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002043151A1 (en) * | 2000-11-22 | 2002-05-30 | Hitachi, Ltd | Semiconductor device and method for fabricating the same |
JP2004165197A (ja) * | 2002-11-08 | 2004-06-10 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
JP2006237070A (ja) * | 2005-02-22 | 2006-09-07 | Sony Corp | 半導体集積回路の製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007027194A (ja) * | 2005-07-12 | 2007-02-01 | Renesas Technology Corp | 半導体装置 |
JP2012523112A (ja) * | 2009-04-01 | 2012-09-27 | コミサリア ア レネルジ アトミク エ オウ エネルジ アルタナティヴ | 明白に異なる閾値電圧を有するトランジスタを持つsoiから製造する集積回路 |
JP2013229597A (ja) * | 2012-04-25 | 2013-11-07 | Samsung Electronics Co Ltd | 応力近接効果を有する集積回路 |
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WO2006107413A3 (en) | 2009-05-07 |
TWI390726B (zh) | 2013-03-21 |
JP5112290B2 (ja) | 2013-01-09 |
EP1869708A4 (en) | 2010-08-25 |
US20060226490A1 (en) | 2006-10-12 |
KR101221345B1 (ko) | 2013-01-11 |
KR20070118240A (ko) | 2007-12-14 |
CN101558494B (zh) | 2012-03-28 |
US20100190354A1 (en) | 2010-07-29 |
US7238990B2 (en) | 2007-07-03 |
US7718485B2 (en) | 2010-05-18 |
US20070218618A1 (en) | 2007-09-20 |
EP1869708A2 (en) | 2007-12-26 |
CN101558494A (zh) | 2009-10-14 |
WO2006107413A2 (en) | 2006-10-12 |
TW200727474A (en) | 2007-07-16 |
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