CN113611672A - 形成半导体元件的方法 - Google Patents

形成半导体元件的方法 Download PDF

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CN113611672A
CN113611672A CN202110676015.XA CN202110676015A CN113611672A CN 113611672 A CN113611672 A CN 113611672A CN 202110676015 A CN202110676015 A CN 202110676015A CN 113611672 A CN113611672 A CN 113611672A
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transistor
gate
region
stress
stress layer
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菊蕊
谈文毅
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United Semi Integrated Circuit Manufacture Xiamen Co ltd
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Abstract

本发明公开一种形成半导体元件的方法。首先提供一基底，具有逻辑电路区和存储单元区。在逻辑电路区内形成具有第一栅极的第一晶体管并且在存储单元区内形成具有第二栅极的第二晶体管。沉积应力层，覆盖逻辑电路区中的第一晶体管和存储单元区中的第二晶体管。使第一晶体管和第二晶体管在应力层的影响下进行退火制作工艺，再结晶第一栅极和第二栅极。

Description

形成半导体元件的方法
技术领域
本发明涉及半导体技术领域，特别是涉及一种改良的半导体元件的制造方法。
背景技术
应力工程(Stress engineering)已被用于提高场效晶体管(FET)元件的元件性能。通常，N型FET使用拉伸(tensile)应力，P型FET使用压缩(compressive)应力以提高元件性能。
静态随机存取存储器(SRAM)常应用于集成电路中。嵌入式SRAM在高速通信、图像处理和系统单芯片(SoC)应用中特别受欢迎。SRAM单元具有无需刷新即可保存数据的优点。
然而，在制造40纳米以下超低电压(ULP)SRAM的过程中所省略的P型轻掺杂漏极(PLDD)光掩模往往导致SRAM面临较高的等待漏电流(Isb)问题。
发明内容
本发明的主要目的在于提供一种改良的形成半导体元件的方法，以解决现有技术的不足与缺点。
本发明一方面提供一种形成半导体元件的方法，包括：提供一基底，其上具有一逻辑电路区和一存储单元区；在所述逻辑电路区内形成具有一第一栅极的一第一晶体管并且在所述存储单元区内形成具有一第二栅极的一第二晶体管，其中所述第一晶体管为一NMOS晶体管，所述第二晶体管为一PMOS晶体管；沉积一应力层，覆盖所述逻辑电路区中的所述第一晶体管和所述存储单元区中的所述第二晶体管；以及使所述第一晶体管和所述第二晶体管在所述应力层的影响下进行一退火制作工艺，以再结晶所述第一栅极和所述第二栅极。
根据本发明实施例，所述应力层是氮化硅层。
根据本发明实施例，所述应力层具有拉伸应力。
根据本发明实施例，所述应力层产生一压缩应力，在所述退火制作工艺中对所述第一栅极和所述第二栅极进行再结晶时，所述压缩应力被存储在所述第一栅极和所述第二栅极内。
根据本发明实施例，被存储在所述第一栅极和所述第二栅极内的所述压缩应力在所述第一晶体管的一第一通道区和所述第二晶体管的一第二通道区内引起一压缩应变。
根据本发明实施例，所述压缩应变提高了所述第一晶体管的性能，而降低了所述第二晶体管的性能。
根据本发明实施例，所述第一栅极和所述第二栅极为多晶硅栅极。
根据本发明实施例，对所述第一晶体管和第二晶体管进行所述退火制作工艺后，所述方法另包含：去除所述应力层。
附图说明
图1至图3例示一种形成半导体元件的方法的示意图。
主要元件符号说明
1 半导体元件
100 基底
110 NMOS晶体管
120 PMOS晶体管
111、121、311、321 栅极
111L、121L、311L、321L 栅极介电层
112、114 NLDD区
116、118 N型重掺杂区
122、124、312、314、322、324 PLDD区
126、128、316、318、326、328 P型重掺杂区
119、129、319、329 间隙壁
CH-1、CH-2、CHN、CHP 通道区
LR 逻辑电路区
MR 存储单元区
PL PMOS拉升晶体管
PR PMOS拉升晶体管
SL 应力层
ST 沟槽隔离结构
具体实施方式
在下文中，将参照附图说明细节，该些附图中的内容也构成说明书细节描述的一部分，并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技术人士得以具以实施。
当然，也可采行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为是限制，反之，其中所包含的实施例将由随附的权利要求来加以界定。
请参阅图1至图3，其例示一种形成半导体元件1的方法。首先
如图1所示，提供一基底100，其上具有一逻辑电路区LR和一存储单元区MR。根据本发明实施例，存储单元区MR内将形成由复数个晶体管所构成的静态随机存取存储器(SRAM)，例如，六晶体管(6T)SRAM单元，由两个交叉耦合的反相器和存取晶体管组成，用于读取和写入数据，其中，6TSRAM单元的存取架构中可以包括两个PMOS拉升晶体管(pull uptransistor)PL和PR。
在制造40纳米以下超低电压(ULP)SRAM的过程中，省略了P型轻掺杂漏极(PLDD)光掩模，PMOS拉升晶体管PL的PLDD掺杂是与嵌入式高压元件一同形成，这使得SRAM单元的PMOS拉升晶体管PL在电性表现上的反应过快，导致SRAM面临较高的等待漏电流(Isb)问题。本发明可以解决这个问题。
根据本发明实施例，在图1中，两个PMOS拉升晶体管PL和PR彼此串接在一起，其中，PMOS拉升晶体管PL包含一栅极311，例如，多晶硅栅极，设置在基底100上。在栅极311和基底100之间，可以设置一栅极介电层311L。PMOS拉升晶体管PL还包含一PLDD区312和一PLDD区314，其中PLDD区312连接一P型重掺杂区316，而PLDD区314连接一P型重掺杂区318。在PLDD区312和PLDD区314之间是一通道区CH-1。在栅极311的侧壁上可以设置有一间隙壁319。
根据本发明实施例，PMOS拉升晶体管PR包含一栅极321，例如，多晶硅栅极，设置在基底100上。在栅极321和基底100之间，可以设置一栅极介电层321L。PMOS拉升晶体管PR还包含一PLDD区322和一PLDD区324，其中PLDD区322连接一P型重掺杂区326，而PLDD区324连接一P型重掺杂区328。P型重掺杂区328和P型重掺杂区318连接在一起。在PLDD区322和PLDD区324之间是一通道区CH-2。在栅极321的侧壁上可以设置有一间隙壁329。
根据本发明实施例，在逻辑电路区LR内可以形成有一NMOS晶体管110和一PMOS晶体管120。根据本发明实施例，NMOS晶体管110包含一栅极111，例如，多晶硅栅极，设置在基底100上。在栅极111和基底100之间，可以设置一栅极介电层111L。NMOS晶体管110还包含一NLDD区112和一NLDD区114，其中NLDD区112连接一N型重掺杂区116，而NLDD区114连接一N型重掺杂区118。在NLDD区112和NLDD区114之间是一通道区CHN。在栅极111的侧壁上可以设置有一间隙壁119。
根据本发明实施例，PMOS晶体管120包含一栅极121，例如，多晶硅栅极，设置在基底100上。在栅极121和基底100之间，可以设置一栅极介电层121L。PMOS晶体管120还包含一PLDD区122和一PLDD区124，其中PLDD区122连接一P型重掺杂区126，而PLDD区124连接一P型重掺杂区128。在PLDD区122和PLDD区124之间是一通道区CHP。在栅极121的侧壁上可以设置有一间隙壁129。基底100内设置有一沟槽隔离结构ST，用来将NMOS晶体管110和PMOS晶体管120彼此隔离。
根据本发明实施例，在完成逻辑电路区LR和存储单元区MR内的晶体管的制作后，接着，全面沉积一应力层(stressor layer)SL，覆盖逻辑电路区LR中的NMOS晶体管110和PMOS晶体管120，和存储单元区MR中的PMOS拉升晶体管PL和PR。根据本发明实施例，应力层SL可以是氮化硅层。根据本发明实施例，应力层SL具有拉伸应力(tensile stress)。
如图2所示，接着，利用光刻及蚀刻制作工艺，将逻辑电路区LR内覆盖在PMOS晶体管120上的应力层SL去除，而剩下的应力层SL继续覆盖着逻辑电路区LR内的NMOS晶体管110和存储单元区MR内的PMOS拉升晶体管PL和PR。
如图3所示，接着，对逻辑电路区LR中的NMOS晶体管110和PMOS晶体管120和存储单元区MR中的PMOS拉升晶体管PL和PR，进行一退火制作工艺。逻辑电路区LR中的NMOS晶体管110的栅极111和存储单元区MR中的PMOS拉升晶体管PL和PR的栅极311和321在应力层SL的影响下进行再结晶。
根据本发明实施例，应力层SL产生一压缩应力，在退火制作工艺中，栅极111和栅极311和321再结晶时，所述压缩应力被存储在栅极111和栅极311和321内。根据本发明实施例，被存储在栅极111和栅极311和321内的所述压缩应力在NMOS晶体管110的通道区CHN和PMOS拉升晶体管PL和PR的通道区CH-1和CH-2内引起压缩应变(compressive strain)。
根据本发明实施例，所述压缩应变提高了NMOS晶体管110的性能，而降低了PMOS拉升晶体管PL和PR的性能。根据本发明实施例，在完成对退火制作工艺后，接着去除剩下的应力层SL。
本发明的技术特征在于，利用具有拉伸应力的应力层SL，刻意使存储单元区MR内的PMOS拉升晶体管PL和PR的性能降低，解决了SRAM单元的PMOS拉升晶体管PL在电性表现上的反应过快的问题，使得SRAM的等待漏电流(Isb)可以恢复到正常范围。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (8)

1.一种形成半导体元件的方法，包括：
提供基底，其上具有逻辑电路区和存储单元区；
在所述逻辑电路区内形成具有第一栅极的第一晶体管并且在所述存储单元区内形成具有第二栅极的第二晶体管，其中所述第一晶体管为NMOS晶体管，所述第二晶体管为PMOS晶体管；
沉积应力层，覆盖所述逻辑电路区中的所述第一晶体管和所述存储单元区中的所述第二晶体管；以及
使所述第一晶体管和所述第二晶体管在所述应力层的影响下进行退火制作工艺，以再结晶所述第一栅极和所述第二栅极。
2.根据权利要求1所述的方法，其中，所述应力层是氮化硅层。
3.根据权利要求1所述的方法，其中，所述应力层具有拉伸应力。
4.根据权利要求3所述的方法，其中，所述应力层产生压缩应力，在所述退火制作工艺中对所述第一栅极和所述第二栅极进行再结晶时，所述压缩应力被存储在所述第一栅极和所述第二栅极内。
5.根据权利要求4所述的方法，其中，被存储在所述第一栅极和所述第二栅极内的所述压缩应力在所述第一晶体管的第一通道区和所述第二晶体管的第二通道区内引起压缩应变。
6.根据权利要求5所述的方法，其中，所述压缩应变提高了所述第一晶体管的性能，而降低了所述第二晶体管的性能。
7.根据权利要求1所述的方法，其中，所述第一栅极和所述第二栅极为多晶硅栅极。
8.根据权利要求1所述的方法，其中，对所述第一晶体管和第二晶体管进行所述退火制作工艺后，所述方法另包含：
去除所述应力层。
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