CN101558494A - 用于集成电路的受应力作用的层间电介质 - Google Patents

用于集成电路的受应力作用的层间电介质 Download PDF

Info

Publication number
CN101558494A
CN101558494A CNA2006800088800A CN200680008880A CN101558494A CN 101558494 A CN101558494 A CN 101558494A CN A2006800088800 A CNA2006800088800 A CN A2006800088800A CN 200680008880 A CN200680008880 A CN 200680008880A CN 101558494 A CN101558494 A CN 101558494A
Authority
CN
China
Prior art keywords
transistor
stress
dielectric layer
semiconductor device
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2006800088800A
Other languages
English (en)
Other versions
CN101558494B (zh
Inventor
詹姆斯·D·伯内特
乔恩·D·奇克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN101558494A publication Critical patent/CN101558494A/zh
Application granted granted Critical
Publication of CN101558494B publication Critical patent/CN101558494B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/18—Peripheral circuit regions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)

Abstract

对于具有逻辑(16)和静态随机存取存储器(SRAM)阵列(18)的集成电路(10)，通过对SRAM阵列的层间电介质(ILD)(42、40)进行有别于逻辑的层间电介质(ILD)的处理来改善其性能。N沟道逻辑(20)和SRAM晶体管(24、26)具有非压缩应力的ILD(40)，P沟道逻辑晶体管(22)ILD(42)具有压缩应力，而P沟道SRAM晶体管(26)至少具有小于P沟道逻辑晶体管的压缩应力，即P沟道SRAM晶体管(26)可以是压缩性的但小于P沟道逻辑晶体管(22)的压缩性、或可以是松弛性的、或者可以是拉伸性的。这有利于使集成电路(10)的P沟道SRAM晶体管(26)具有比P沟道逻辑晶体管(22)更低的迁移率。具有更低迁移率的P沟道SRAM晶体管(26)会使得写入性能更好；在低功耗电源电压下无论是写入时间还是写入余量均能更佳。

Description

用于集成电路的受应力作用的层间电介质
技术领域
本发明涉及集成电路，尤其是涉及具有受到应力作用以改善集成电路性能的层间电介质的集成电路。
背景技术
已在开发的用于改善晶体管迁移率的技术之一是应变硅。典型地，硅层受到拉伸应力作用以改善N沟道迁移率。这已被扩展到使用层间电介质(ILD)，即夹在导电层之间的电介质层，其受到选择的应力作用来改善晶体管性能。对于N沟道晶体管而言这意味着使用拉伸应力，而对于P沟道晶体管而言这意味着使用压缩应力。
附图说明
下文中结合下列附图对本发明优选实施方案的详细描述将向本领域技术人员阐明本发明前述的和将述的和更多的具体目标和优点：
图1为处于根据本发明的多个实施方案所述的处理过程中某一阶段的半导体结构的截面图；
图2为处于根据本发明第一、第二、第三、第四实施方案所述的处理过程中后续阶段的图1的半导体结构的截面图；
图3为处于根据本发明第一和第四实施方案所述的处理过程中后续阶段的图2的半导体结构的截面图；
图4为处于根据本发明第一和第四实施方案所述的处理过程中后续阶段的图3的半导体结构的截面图；
图5为处于根据本发明第一和第四实施方案所述的处理过程中后续阶段的图4的半导体结构的截面图；
图6为处于根据本发明第一实施方案所述的处理过程中后续阶段的图5的半导体结构的截面图；
图7为处于根据本发明第二和第三实施方案所述的处理过程中后续阶段的图2的半导体结构的截面图；
图8为处于根据本发明第二和第三实施方案所述的处理过程中后续阶段的图7的半导体结构的截面图；
图9为处于根据本发明第二实施方案所述的处理过程中后续阶段的图8的半导体结构的截面图；
图10为处于根据本发明第二实施方案所述的处理过程中后续阶段的图9的半导体结构的截面图；
图11为处于根据本发明第二实施方案所述的处理过程中后续阶段的图10的半导体结构的截面图；
图12为处于根据本发明第二实施方案所述的处理过程中后续阶段的图11的半导体结构的截面图；
图13为处于根据本发明第三实施方案所述的处理过程中后续阶段的图8的半导体结构的截面图；
图14为处于根据本发明第三实施方案所述的处理过程中后续阶段的图13的半导体结构的截面图；
图15为处于根据本发明第四实施方案所述的处理过程中后续阶段的图5的半导体结构的截面图；
图16为处于根据本发明第四实施方案所述的处理过程中后续阶段的图15的半导体结构的截面图；
具体实施方式
一方面，对于同时具有逻辑和静态随机存取存储器(SRAM)阵列的集成电路，通过对SRAM阵列的层间电介质(ILD)进行有别于逻辑的处理来改善其性能。N沟道逻辑和N沟道SRAM晶体管均具有ILD，该ILD具有压缩应力；P沟道逻辑晶体管的ILD具有压缩应力；而P沟道SRAM晶体管至少具有小于P沟道逻辑晶体管的压缩应力，即P沟道SRAM晶体管可以是压缩性的但其小于P沟道逻辑晶体管的压缩应力的大小、或可以是松弛性的、或者可以是拉伸性的。这有利于使得集成电路的P沟道SRAM晶体管具有比P沟道逻辑晶体管更低的迁移率。具有更低迁移率的P沟道SRAM晶体管会使得写入性能更好；在低功耗电源电压下无论是写入时间还是写入余量均能更佳。这通过参照附图和下列说明会更好地理解。
如图1所示，半导体器件10中使用了SOI衬底，该SOI衬底包括相对较厚的绝缘层12和半导体层14。半导体层14优选地为硅但也可为诸如锗硅(silicon germanium)或硅碳(silicon carbon)之类的其他半导体材料。绝缘层12优选地为氧化物，但也可为其他绝缘材料。半导体器件10内置有逻辑部分16和SRAM阵列区域18。如图1所示，逻辑部分16包括N沟道晶体管20和P沟道晶体管22。晶体管20和22代表出现于一般的集成电路中用于形成逻辑功能电路诸如逻辑门、寄存器、处理单元、以及其它逻辑功能电路的许多其他的N沟道和P沟道晶体管，一般为数以百万计。类似地，如图1所示，SRAM阵列部分18包括N沟道晶体管24和P沟道晶体管26。晶体管24和26同样也代表形成SRAM阵列的许多其他的N沟道和P沟道晶体管，一般为数以百万计。逻辑晶体管20和22由形成于半导体层14中的隔离区28、30和32相互隔离开并与其它的晶体管隔离开。同样，SRAM晶体管24和26由隔离区34、36和38相互隔离开并与其它SRAM晶体管隔离开。
图2所示为在将电介质层40沉积于逻辑部分16和SRAM阵列部分18上之后的半导体器件10。电介质层40以具有拉伸应力的方式被沉积。电介质层40的示范材料为通过等离子增强化学气相沉积法(PECVD)沉积的氮化硅。拉伸应力的量是可以根据沉积参数进行选择的。电介质层40的厚度大约为晶体管20、22、24和26的栅的高度的一半。在本例中，这会使电介质层40的厚度为大约500埃。
图3所示为在从晶体管22有选择地去除了电介质层之后的半导体器件10，其中晶体管22为P沟道晶体管，其利用拉伸应力作用减小了迁移率。
图4所示为在逻辑部分16和SRAM阵列部分18之上沉积了电介质层42之后的半导体器件10。电介质层42以具有压缩应力地方式被沉积并且其厚度与电介质层40大致相同。电介质层42也优选地为通过PECVD沉积的氮化硅但是所选用的参数要使其具有压缩性。
图5所示为在有选择地蚀刻了电介质层42以使电介质层42只保留在晶体管22上并少量地与电介质层40重叠之后的半导体器件10。该蚀刻虽然是用掩模步骤来完成的，但还是导致电介质层40在电介质层42被蚀穿之后被暴露于蚀刻。因为电介质层40和42都为相似成分，是用不同参数形成的氮化硅，所以两层之间具有小的选择性(selectivity)。因此，优选地进行定时蚀刻(timed etch)。可以优选地形成厚度略大于电介质层42的电介质层40以解决一些进入到电介质层40中的过蚀刻。这时的结果就是N沟道晶体管20和24具有拉伸性的ILD，SRAM P沟道具有拉伸性的ILD，而逻辑P沟道具有压缩性的ILD。这可以增强晶体管20、22和24的迁移率并减少晶体管26的迁移率。晶体管26，作为SRAM阵列中的P沟道晶体管，被用作上拉晶体管。这种具有更低迁移率的上拉晶体管改善了写入性能。该写入性能既可以是对于低功耗电源电压应用中的写入余量也可以是对于更快的写入。
图6所示为在形成电介质层44之后的半导体器件10，电介质层44完成了在晶体管20、22、24和26之上的ILD的形成。电介质层44优选地为诸如TEOS的氧化物或者诸如掺杂玻璃的其他氧化物或者其他绝缘型材料。电介质层44优选地由能被平坦化并且具有松弛性或者几乎松弛性的应力的材料制成。在完成电介质层44之后，可以形成金属层以用于向集成电路提供互连。
图7所示为图2的半导体器件10在经过从晶体管26和晶体管22上去除电介质层的蚀刻之后得到的半导体器件45。图7中与图1到6类似的特征都被保留下来。
图8所示为在沉积电介质层42之后的半导体器件45，其中沉积与图4所示相同，位于晶体管20、22、24和26之上。
图9所示为从晶体管20、24和26之上有选择地去除电介质层42之后的半导体器件45。电介质层42的部分去除与图5相同地进行。这样的结果就是晶体管26不具有晶体管20、22和24所具有的那样的电介质层。
图10所示为在逻辑部分16和SRAM阵列部分18之上沉积电介质层46之后的半导体器件45。该电介质层也具有与电介质层40和42大致相同的厚度并且同样为通过PECVD沉积的氮化硅。这种情况下选择沉积参数以使电介质层46的压缩性至少小于电介质层42。这意味着电介质层46是压缩性的但是压缩性小于电介质层42、或松弛性的、或者拉伸性的中的一种。如果为拉伸性的，则其拉伸的量优选地不同于电介质层40的拉伸量。
图11所示为在有选择地从晶体管20、22和24之上去除了电介质层46之后的半导体器件45。这导致N沟道半导体20和24具有拉伸性的ILD、P沟道晶体管22具有压缩性的ILD、而P沟道晶体管46所具有的ILD的压缩性至少小于晶体管42的ILD的压缩性。SRAM单元因此具有了迁移率小于集成电路逻辑部分中所用的P沟道晶体管的上拉晶体管。这有利于SRAM单元并且能够改善写入余量或者写入速度。
图12所示为半导体器件45，具有已完成的ILD，表示了位于晶体管20、22、24和26之上的平坦的电介质层44的形成。在电介质层44之上可以形成金属互连。
图13所示为图8的半导体器件45在经过蚀刻之后得到的半导体器件49，该蚀刻从晶体管20和晶体管24之上去除电介质层42以使电介质层42保留于晶体管22和26上。图13中与图1到12中类似的特征都被保留下来。在该阶段，P沟道晶体管22和26具有相同的压缩应力。
图14中所示为在将注入掩模(implant mask)50形成于晶体管20、22和24上并且将注入物52注入到电介质层42中以使其转换为至少具有小于电介质层42的压缩应力的电介质层54之后的半导体器件49。注入掩模50优选地为光致抗蚀剂，但也可为其他合适的材料。注入物52优选地为氙，但也可以为其他具有能够减小电介质层54的压缩应力的量地效果的注入物。该注入物对于使电介质层42变得松弛特别有用。注入物使得SRAM单元中具有了具有较低迁移率的P沟道上拉晶体管并因此改善了写入余量或者写入速度。
图15所示为图5的半导体器件10在晶体管20、22和24之上形成了注入掩模56形成之后得到的半导体器件55。图13中与图1到6中类似的特征都被保留下来。这表示了位于晶体管26之上的电介质层40部分被暴露。
图16所示为在注入了可以减少电介质层40暴露部分的拉伸应力的注入物58以使电介质层40变为电介质层60之后的半导体器件55。该方法对于在需要使P沟道上拉晶体管稍微拉伸的时候减少迁移率特别有用，但其拉伸性不像N沟道晶体管的那样大。如果上拉晶体管拉伸得太大，就可能使读取静电噪声余量(read static noise margin)恶化。注入的结果就是SRAM单元中仍然具有迁移率低于逻辑P沟道的迁移率的P沟道上拉晶体管，并因此改善了写入余量或者写入速度。
本领域技术人员容易想到对文中用于解释目的所选的实施方案的各种改变和修改。比如，可以改变电介质层的形成顺序。不首先形成拉伸性的层40，而可以先形成压缩性的层42。所示的这些使用SOI衬底的实施方案也可以使用其他类型的衬底，诸如体硅(bulk)或者混合体硅-SOI混合体(bulk-SOI hybrid)。在不离开本发明的精神的前提下，这些修改和改变都被包括在只由下列权利要求的公正解释所限定的本发明的范围中。

Claims (20)

1.一种半导体器件，包括：
逻辑部分，包括第一N沟道晶体管和第一P沟道晶体管；
静态随机存取存储器(SRAM)阵列部分，包括第二N沟道晶体管和第二P沟道晶体管；
位于第一P沟道晶体管之上的、具有压缩应力的第一ILD；以及
位于第二P沟道晶体管之上的第二ILD，其具有压缩性至少小于第一ILD的压缩应力的应力。
2.根据权利要求1所述的半导体器件，其中，第一ILD和第二ILD包括应力不同的氮化硅。
3.根据权利要求1所述的半导体器件，其中，第二P沟道晶体管作为SRAM阵列中的上拉晶体管。
4.根据权利要求1所述的半导体器件，其中，第二ILD位于第一和第二N沟道晶体管之上。
5.根据权利要求1所述的半导体器件，还包括位于第一和第二N沟道晶体管之上的、具有拉伸应力的第三ILD。
6.根据权利要求1所述的半导体器件，其中，第二ILD的应力为压缩的。
7.根据权利要求1所述的半导体器件，其中，第二ILD的应力为松弛的。
8.根据权利要求1所述的半导体器件，其中，第二ILD的应力为拉伸的。
9.根据权利要求8所述的半导体器件，还包括位于第一和第二N沟道晶体管之上的第三ILD，其具有拉伸性至少大于第二ILD的拉伸应力。
10.一种半导体器件，包括：
第一部分，包括用在第一类型的电路中的第一类型的第一晶体管和第二类型的第一晶体管；
第二部分，包括用在第二类型的电路中的第一类型的第二晶体管和第二类型的第二晶体管；
位于第一类型的第一晶体管之上的第一ILD，其具有第一类型的第一应力；以及
位于第一类型的第二晶体管之上的第二ILD，其具有至少小于第一类型的第一应力的第二应力。
11.根据权利要求10所述的半导体器件，其中，
第一类型的第一晶体管和第一类型的第二晶体管为P沟道晶体管；以及
第一类型的第一应力为压缩性的。
12.根据权利要求11所述的半导体器件，其中，第一类型的电路为逻辑电路而第二类型的电路为SRAM阵列。
13.根据权利要求12所述的半导体器件，其中，第一类型的第二晶体管为SRAM阵列中的上拉晶体管。
14.根据权利要求13所述的半导体器件，还包括位于第二类型的第一和第二晶体管之上的、具有拉伸应力的第三ILD。
15.根据权利要求13所述的半导体器件，其中，第二ILD位于第二类型的第一和第二晶体管之上。
16.一种制造半导体器件的方法，包括以下步骤：
形成用于逻辑电路中的第一N沟道晶体管；
形成用于该逻辑电路中的第一P沟道晶体管；
形成用于SRAM阵列中的第二N沟道晶体管；
形成用于该SRAM阵列中的第二P沟道晶体管；
在半导体器件上沉积具有第一应力的第一电介质层；
去除位于第一P沟道晶体管之上的第一电介质层；
在半导体器件上沉积具有压缩性大于第一应力的第二应力的第二电介质层；以及
去除位于第一和第二N沟道晶体管以及第二P沟道晶体管之上的第二电介质层。
17.根据权利要求16所述的方法，其中，第一应力为拉伸应力，该方法还包括向位于第二P沟道晶体管之上的第一电介质层的第一部分中注入以使得第一电介质层的第一部分的拉伸性变小。
18.一种制造半导体器件的方法，包括以下步骤：
形成用于逻辑电路中的第一N沟道晶体管；
形成用于该逻辑电路中的第一P沟道晶体管；
形成用于SRAM阵列中的第二N沟道晶体管；
形成用于该SRAM阵列中的第二P沟道晶体管；
在半导体器件上沉积具有第一应力的第一电介质层；
去除位于第一和第二P沟道晶体管之上的第一电介质层；
在半导体器件上沉积具有压缩性大于第一应力的第二应力的第二电介质层；以及
去除位于第一和第二N沟道晶体管以及第二P沟道晶体管之上的第二电介质层；
在半导体器件上沉积具有处于第一应力和第二应力之间的第三应力的第三电介质层；
去除位于第一和第二N沟道晶体管以及第一P沟道晶体管之上的第三电介质层。
19.一种制造半导体器件的方法，包括以下步骤：
形成用于逻辑电路中的第一N沟道晶体管；
形成用于该逻辑电路中的第一P沟道晶体管；
形成用于SRAM阵列中的第二N沟道晶体管；
形成用于该SRAM阵列中的第二P沟道晶体管；
在半导体器件上沉积具有第一应力的第一电介质层；
去除位于第一和第二P沟道晶体管之上的第一电介质层；
在半导体器件上沉积具有压缩性大于第一应力的第二应力的第二电介质层；以及
去除位于第一和第二N沟道晶体管之上的第二电介质层，以将第二电介质层的第一部分保留在第一P沟道晶体管上并且将第二电介质层的第二部分保留在第二P沟道晶体管上；以及
向第二电介质层的第二部分注入以使得第二电介质层的第二部分的压缩性变小。
20.一种制造半导体器件的方法，包括以下步骤：
形成第一部分，包括用在第一类型的电路中的第一类型的第一晶体管和第二类型的第一晶体管；
形成第二部分，包括用在第二类型的电路中的第一类型的第二晶体管和第二类型的第二晶体管；
形成位于第一类型的第一晶体管之上的第一ILD，其具有第一类型的第一应力；以及
形成位于第一类型的第二晶体管之上的第二ILD，其具有至少小于第一类型的第一应力的第二应力。
CN2006800088800A 2005-04-06 2006-02-16 半导体器件及其制造方法 Expired - Fee Related CN101558494B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/100,168 US7238990B2 (en) 2005-04-06 2005-04-06 Interlayer dielectric under stress for an integrated circuit
US11/100,168 2005-04-06
PCT/US2006/005369 WO2006107413A2 (en) 2005-04-06 2006-02-16 Interlayer dielectric under stress for an integrated circuit

Publications (2)

Publication Number Publication Date
CN101558494A true CN101558494A (zh) 2009-10-14
CN101558494B CN101558494B (zh) 2012-03-28

Family

ID=37073903

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2006800088800A Expired - Fee Related CN101558494B (zh) 2005-04-06 2006-02-16 半导体器件及其制造方法

Country Status (7)

Country Link
US (3) US7238990B2 (zh)
EP (1) EP1869708A4 (zh)
JP (1) JP5112290B2 (zh)
KR (1) KR101221345B1 (zh)
CN (1) CN101558494B (zh)
TW (1) TWI390726B (zh)
WO (1) WO2006107413A2 (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569301A (zh) * 2012-03-01 2012-07-11 上海宏力半导体制造有限公司 Sram存储器及其形成方法
CN102637690A (zh) * 2012-04-24 2012-08-15 上海宏力半导体制造有限公司 Sram存储器及其形成方法
CN102646641A (zh) * 2012-05-04 2012-08-22 上海华力微电子有限公司 提高静态随机存储器写入冗余度的方法
CN102655123A (zh) * 2012-04-16 2012-09-05 上海华力微电子有限公司 一种提高静态随机存储器读出冗余度的方法
CN102738084A (zh) * 2012-05-04 2012-10-17 上海华力微电子有限公司 一种提高静态随机存储器写入冗余度的方法
CN103730469A (zh) * 2014-01-07 2014-04-16 上海华虹宏力半导体制造有限公司 静态随机存取存储单元及其形成方法
CN109713040A (zh) * 2018-12-20 2019-05-03 中国科学院微电子研究所 一种集成电路结构
CN109829240A (zh) * 2019-02-19 2019-05-31 中国科学院微电子研究所 一种集成电路性能的优化方法

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU1139100A (en) 1998-10-16 2000-05-08 Silverbrook Research Pty Limited Improvements relating to inkjet printers
US7419250B2 (en) * 1999-10-15 2008-09-02 Silverbrook Research Pty Ltd Micro-electromechanical liquid ejection device
JP2003100902A (ja) 2001-09-21 2003-04-04 Mitsubishi Electric Corp 半導体装置の製造方法
FR2884968B1 (fr) * 2005-04-20 2007-09-21 St Microelectronics Sa Circuit electronique integre a etat electrique stabilise
US7276755B2 (en) * 2005-05-02 2007-10-02 Advanced Micro Devices, Inc. Integrated circuit and method of manufacture
US7060549B1 (en) * 2005-07-01 2006-06-13 Advanced Micro Devices, Inc. SRAM devices utilizing tensile-stressed strain films and methods for fabricating the same
JP2007027194A (ja) * 2005-07-12 2007-02-01 Renesas Technology Corp 半導体装置
JP2007059473A (ja) * 2005-08-22 2007-03-08 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
DE102005046974B3 (de) * 2005-09-30 2007-04-05 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Erzeugen einer unterschiedlichen mechanischen Formung in unterschiedlichen Substratgebieten durch bilden einer Schicht mit verschieden modifizierter innerer Spannung und mit dem Verfahren hergestelltes Bauteil
JP4787593B2 (ja) * 2005-10-14 2011-10-05 パナソニック株式会社 半導体装置
US7485517B2 (en) * 2006-04-07 2009-02-03 United Microelectronics Corp. Fabricating method of semiconductor device
KR100762243B1 (ko) * 2006-09-19 2007-10-01 주식회사 하이닉스반도체 반도체 소자의 제조방법
DE102007004824A1 (de) * 2007-01-31 2008-08-07 Advanced Micro Devices, Inc., Sunnyvale Verbesserte Verspannungsübertragung in einem Zwischenschichtdielektrikum durch Verwendung einer zusätzlichen Verspannungsschicht über einer Schicht mit dualer Verspannung in einem Halbleiterbauelement
DE102007004883B4 (de) * 2007-01-31 2011-07-21 Globalfoundries Inc. Verfahren zur Reduzierung durch Ätzen hervorgerufener Prozessungleichmäßigkeiten durch Weglassen der Abscheidung einer Endpunkterkennungsschicht während der Strukturierung verspannter Deckschichten in einem Halbleiterbauelement
DE102007009901B4 (de) * 2007-02-28 2011-07-07 Globalfoundries Inc. Technik zum Strukturieren unterschiedlich verspannter Schichten, die über Transistoren ausgebildet sind, durch verbesserte Ätzsteuerungsstrategien
US8643124B2 (en) 2007-05-25 2014-02-04 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
US20090179253A1 (en) 2007-05-25 2009-07-16 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
US8093128B2 (en) * 2007-05-25 2012-01-10 Cypress Semiconductor Corporation Integration of non-volatile charge trap memory devices and logic CMOS devices
US8871595B2 (en) 2007-05-25 2014-10-28 Cypress Semiconductor Corporation Integration of non-volatile charge trap memory devices and logic CMOS devices
US8633537B2 (en) 2007-05-25 2014-01-21 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers and a high work function gate electrode
US9449831B2 (en) 2007-05-25 2016-09-20 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
US8940645B2 (en) 2007-05-25 2015-01-27 Cypress Semiconductor Corporation Radical oxidation process for fabricating a nonvolatile charge trap memory device
DE102007025342B4 (de) * 2007-05-31 2011-07-28 Globalfoundries Inc. Höheres Transistorleistungsvermögen von N-Kanaltransistoren und P-Kanaltransistoren durch Verwenden einer zusätzlichen Schicht über einer Doppelverspannungsschicht
US7915681B2 (en) * 2007-06-18 2011-03-29 Infineon Technologies Ag Transistor with reduced charge carrier mobility
DE102007052051B4 (de) * 2007-10-31 2012-09-20 Advanced Micro Devices, Inc. Herstellung verspannungsinduzierender Schichten über einem Bauteilgebiet mit dichtliegenden Transistorelementen
US7863646B2 (en) * 2007-12-13 2011-01-04 International Business Machines Corporation Dual oxide stress liner
DE102007063272B4 (de) * 2007-12-31 2012-08-30 Globalfoundries Inc. Dielektrisches Zwischenschichtmaterial in einem Halbleiterbauelement mit verspannten Schichten mit einem Zwischenpuffermaterial
US7727834B2 (en) * 2008-02-14 2010-06-01 Toshiba America Electronic Components, Inc. Contact configuration and method in dual-stress liner semiconductor device
DE102008011814B4 (de) 2008-02-29 2012-04-26 Advanced Micro Devices, Inc. CMOS-Bauelement mit vergrabener isolierender Schicht und verformten Kanalgebieten sowie Verfahren zum Herstellen derselben
US7977202B2 (en) 2008-05-02 2011-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing device performance drift caused by large spacings between active regions
DE102008059649B4 (de) * 2008-11-28 2013-01-31 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Geringere topographieabhängige Unregelmäßigkeiten während der Strukturierung zweier unterschiedlicher verspannungsinduzierender Schichten in der Kontaktebene eines Halbleiterbauelements
FR2944139B1 (fr) * 2009-04-01 2011-09-09 Commissariat Energie Atomique Circuit integre realise en soi presentant des transistors a tensions de seuil distinctes
US8723827B2 (en) 2009-07-28 2014-05-13 Cypress Semiconductor Corporation Predictive touch surface scanning
US9041082B2 (en) * 2010-10-07 2015-05-26 International Business Machines Corporation Engineering multiple threshold voltages in an integrated circuit
US8685813B2 (en) 2012-02-15 2014-04-01 Cypress Semiconductor Corporation Method of integrating a charge-trapping gate stack into a CMOS flow
KR101912582B1 (ko) * 2012-04-25 2018-12-28 삼성전자 주식회사 반도체 장치 및 그 제조 방법
CN102637644A (zh) * 2012-05-04 2012-08-15 上海华力微电子有限公司 提高静态随机存储器写入冗余度的方法
CN102683188A (zh) * 2012-05-10 2012-09-19 上海华力微电子有限公司 提高静态随机存储器写入冗余度的方法
US9054220B2 (en) 2013-02-08 2015-06-09 Freescale Semiconductor, Inc. Embedded NVM in a HKMG process
US9412866B2 (en) * 2013-06-24 2016-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. BEOL selectivity stress film
US10593449B2 (en) 2017-03-30 2020-03-17 International Business Machines Corporation Magnetic inductor with multiple magnetic layer thicknesses
US10607759B2 (en) 2017-03-31 2020-03-31 International Business Machines Corporation Method of fabricating a laminated stack of magnetic inductor
US10597769B2 (en) 2017-04-05 2020-03-24 International Business Machines Corporation Method of fabricating a magnetic stack arrangement of a laminated magnetic inductor
US10347411B2 (en) 2017-05-19 2019-07-09 International Business Machines Corporation Stress management scheme for fabricating thick magnetic films of an inductor yoke arrangement
CN113611672A (zh) * 2021-06-18 2021-11-05 联芯集成电路制造(厦门)有限公司 形成半导体元件的方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19535629C1 (de) * 1995-09-25 1996-09-12 Siemens Ag Verfahren zur Herstellung einer integrierten CMOS-Schaltung
JP3560480B2 (ja) * 1998-10-05 2004-09-02 シャープ株式会社 スタティック・ランダム・アクセスメモリ
JP2001015704A (ja) * 1999-06-29 2001-01-19 Hitachi Ltd 半導体集積回路
JP4597479B2 (ja) * 2000-11-22 2010-12-15 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US6580136B2 (en) * 2001-01-30 2003-06-17 International Business Machines Corporation Method for delineation of eDRAM support device notched gate
US20020197823A1 (en) * 2001-05-18 2002-12-26 Yoo Jae-Yoon Isolation method for semiconductor device
JP2003060076A (ja) * 2001-08-21 2003-02-28 Nec Corp 半導体装置及びその製造方法
JP4173672B2 (ja) * 2002-03-19 2008-10-29 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JP2004165197A (ja) * 2002-11-08 2004-06-10 Renesas Technology Corp 半導体集積回路装置およびその製造方法
US6882025B2 (en) * 2003-04-25 2005-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Strained-channel transistor and methods of manufacture
US7301206B2 (en) * 2003-08-01 2007-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
US6982196B2 (en) * 2003-11-04 2006-01-03 International Business Machines Corporation Oxidation method for altering a film structure and CMOS transistor structure formed therewith
US20050214998A1 (en) * 2004-03-26 2005-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Local stress control for CMOS performance enhancement
KR101025761B1 (ko) * 2004-03-30 2011-04-04 삼성전자주식회사 디지탈 회로 및 아날로그 회로를 가지는 반도체 집적회로및 그 제조 방법
US20050266632A1 (en) * 2004-05-26 2005-12-01 Yun-Hsiu Chen Integrated circuit with strained and non-strained transistors, and method of forming thereof
DE102004026149B4 (de) * 2004-05-28 2008-06-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Erzeugen eines Halbleiterbauelements mit Transistorelementen mit spannungsinduzierenden Ätzstoppschichten
US7348284B2 (en) * 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
JP4453572B2 (ja) * 2005-02-22 2010-04-21 ソニー株式会社 半導体集積回路の製造方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569301A (zh) * 2012-03-01 2012-07-11 上海宏力半导体制造有限公司 Sram存储器及其形成方法
CN102655123A (zh) * 2012-04-16 2012-09-05 上海华力微电子有限公司 一种提高静态随机存储器读出冗余度的方法
CN102637690A (zh) * 2012-04-24 2012-08-15 上海宏力半导体制造有限公司 Sram存储器及其形成方法
CN102646641A (zh) * 2012-05-04 2012-08-22 上海华力微电子有限公司 提高静态随机存储器写入冗余度的方法
CN102738084A (zh) * 2012-05-04 2012-10-17 上海华力微电子有限公司 一种提高静态随机存储器写入冗余度的方法
CN103730469A (zh) * 2014-01-07 2014-04-16 上海华虹宏力半导体制造有限公司 静态随机存取存储单元及其形成方法
US9312263B2 (en) 2014-01-07 2016-04-12 Shanghai Huadong Grace Semiconductor Manufacturing Corporation Static random access memory cell and forming method thereof
CN109713040A (zh) * 2018-12-20 2019-05-03 中国科学院微电子研究所 一种集成电路结构
CN109829240A (zh) * 2019-02-19 2019-05-31 中国科学院微电子研究所 一种集成电路性能的优化方法

Also Published As

Publication number Publication date
KR20070118240A (ko) 2007-12-14
EP1869708A4 (en) 2010-08-25
WO2006107413A3 (en) 2009-05-07
KR101221345B1 (ko) 2013-01-11
EP1869708A2 (en) 2007-12-26
US20100190354A1 (en) 2010-07-29
US20070218618A1 (en) 2007-09-20
TW200727474A (en) 2007-07-16
US7238990B2 (en) 2007-07-03
JP2008538859A (ja) 2008-11-06
US7718485B2 (en) 2010-05-18
CN101558494B (zh) 2012-03-28
TWI390726B (zh) 2013-03-21
WO2006107413A2 (en) 2006-10-12
US20060226490A1 (en) 2006-10-12
JP5112290B2 (ja) 2013-01-09

Similar Documents

Publication Publication Date Title
CN101558494B (zh) 半导体器件及其制造方法
US10770353B2 (en) Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed
US8143165B2 (en) Method for fabricating semiconductor devices using strained silicon bearing material
US8008724B2 (en) Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers
US7285826B2 (en) High mobility CMOS circuits
US6737332B1 (en) Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same
Hu Device challenges and opportunities
US20080220594A1 (en) Fabrication method of a mixed substrate and use of the substrate for producing circuits
JP5268385B2 (ja) 半導体装置
US7268362B2 (en) High performance transistors with SiGe strain
US8183105B2 (en) Integrated circuit device with stress reduction layer
US20190385856A1 (en) Method of forming multi-threshold voltage devices and devices so formed
US7041562B2 (en) Method for forming multiple gate oxide thickness utilizing ashing and cleaning
Iwai CMOS Scaling for sub-90 nm to sub-10 nm
US7436036B2 (en) PMOS transistor of semiconductor device, semiconductor device comprising the same, and method for manufacturing the same
US7541234B2 (en) Methods of fabricating integrated circuit transistors by simultaneously removing a photoresist layer and a carbon-containing layer on different active areas
Park et al. High-k gate dielectrics for nanoscale CMOS devices: status, challenges, and future
CN101667577A (zh) 基于高介电常数材料的抗nmos器件总剂量辐照的集成电路
Cai et al. Extending dual stress liner process to high performance 32nm node SOI CMOS manufacturing
Polishchuk et al. A Low-Cost Strained Silicon SRAM Technology with Reduced Contact Resistance
Okushima et al. Influence of Gate Oxide Quality on Plasma Process-Induced Charging Damage in Ultra Thin Gate Oxide
Sato et al. Body-charge-induced switching characteristics in fully depleted silicon-on-insulator digital circuits
KR20010058162A (ko) 에스램 소자의 박막트랜지스터 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120328

Termination date: 20200216