FR2884968B1 - Circuit electronique integre a etat electrique stabilise - Google Patents

Circuit electronique integre a etat electrique stabilise

Info

Publication number
FR2884968B1
FR2884968B1 FR0503958A FR0503958A FR2884968B1 FR 2884968 B1 FR2884968 B1 FR 2884968B1 FR 0503958 A FR0503958 A FR 0503958A FR 0503958 A FR0503958 A FR 0503958A FR 2884968 B1 FR2884968 B1 FR 2884968B1
Authority
FR
France
Prior art keywords
electronic circuit
integrated electronic
electric state
stabilized electric
stabilized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0503958A
Other languages
English (en)
Other versions
FR2884968A1 (fr
Inventor
Jean Pierre Schoellkopf
Philippe Roche
Herve Jaouen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0503958A priority Critical patent/FR2884968B1/fr
Priority to US11/407,849 priority patent/US20060258066A1/en
Publication of FR2884968A1 publication Critical patent/FR2884968A1/fr
Application granted granted Critical
Publication of FR2884968B1 publication Critical patent/FR2884968B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
FR0503958A 2005-04-20 2005-04-20 Circuit electronique integre a etat electrique stabilise Expired - Fee Related FR2884968B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0503958A FR2884968B1 (fr) 2005-04-20 2005-04-20 Circuit electronique integre a etat electrique stabilise
US11/407,849 US20060258066A1 (en) 2005-04-20 2006-04-20 Electrically stabilized integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0503958A FR2884968B1 (fr) 2005-04-20 2005-04-20 Circuit electronique integre a etat electrique stabilise

Publications (2)

Publication Number Publication Date
FR2884968A1 FR2884968A1 (fr) 2006-10-27
FR2884968B1 true FR2884968B1 (fr) 2007-09-21

Family

ID=35447407

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0503958A Expired - Fee Related FR2884968B1 (fr) 2005-04-20 2005-04-20 Circuit electronique integre a etat electrique stabilise

Country Status (2)

Country Link
US (1) US20060258066A1 (fr)
FR (1) FR2884968B1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3977564A4 (fr) * 2019-05-24 2023-06-14 3M Innovative Properties Company Article réfléchissant de radar ayant un gradient de permittivité

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09260510A (ja) * 1996-01-17 1997-10-03 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6777320B1 (en) * 1998-11-13 2004-08-17 Intel Corporation In-plane on-chip decoupling capacitors and method for making same
CN1449585A (zh) * 2000-11-22 2003-10-15 株式会社日立制作所 半导体器件及其制造方法
JP2002359298A (ja) * 2001-05-31 2002-12-13 Mitsubishi Electric Corp 半導体記憶装置
US7022561B2 (en) * 2002-12-02 2006-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS device
KR20040069665A (ko) * 2003-01-30 2004-08-06 주식회사 하이닉스반도체 에스램 셀 및 그의 제조방법
JP3802002B2 (ja) * 2003-03-27 2006-07-26 三星電子株式会社 半導体装置の製造方法
US6984564B1 (en) * 2004-06-24 2006-01-10 International Business Machines Corporation Structure and method to improve SRAM stability without increasing cell area or off current
DE102004042167B4 (de) * 2004-08-31 2009-04-02 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Ausbilden einer Halbleiterstruktur, die Transistorelemente mit unterschiedlich verspannten Kanalgebieten umfasst, und entsprechende Halbleiterstruktur
US7238990B2 (en) * 2005-04-06 2007-07-03 Freescale Semiconductor, Inc. Interlayer dielectric under stress for an integrated circuit

Also Published As

Publication number Publication date
US20060258066A1 (en) 2006-11-16
FR2884968A1 (fr) 2006-10-27

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20131231