JP2008522415A - 電力低減型磁気抵抗ランダム・アクセス・メモリ素子 - Google Patents
電力低減型磁気抵抗ランダム・アクセス・メモリ素子 Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
Abstract
Description
ここで、Hk(固有)は、磁気領域104を備える材料の固有異方性であり、そしてHk(形状)は、磁気領域104の形状に起因した異方性である。同様に、HSATは、次式により表される。
この式では、HSAT(固有)は、第1の磁気領域104の磁性層が連続したフィルム(膜)として形成された場合互いに実質的に平行であるときの磁界であり、そしてHSAT(形状)は、磁気領域104の磁性層の静磁気結合を磁気領域104の形状の結果として表す。
Claims (20)
- メモリ素子のアレイを有する磁気抵抗ランダム・アクセス装置であって、
各メモリ素子が、
固定の磁気部分と、
前記固定の磁気部分に近接して配設されたトンネル障壁部分と、
前記トンネル障壁部分に近接して配設された自由SAF構造と、を備え、
前記メモリ素子のアレイが、次式
ここで、<Hsw>は、前記アレイに関する平均切り替え磁界であり、
<HSAT>は、前記アレイに関する平均飽和磁界であり、
前記各メモリ素子に関するHswは、次式
ここで、Hkは、前記各メモリ素子の前記自由SAF構造の合計異方性磁界を表し、
HSATは、前記各メモリ素子の前記自由SAF構造に関する合計反強磁性結合飽和磁界を表し、
Nは、1以上の整数であり、
σswは、<Hsw>についての標準偏差であり、
σsatは、<HSAT>についての標準偏差であり、
前記自由SAF構造は、前記メモリ素子のアレイが熱的に安定であり且つ所定の電流値より下である動作電流を要求するようにHk、HSAT及びN値を有するように構成される、磁気抵抗ランダム・アクセス装置。 - 前記アレイの前記各メモリ素子の前記自由SAF構造のHkが、15Oe−マイクロメートルを前記自由SAF構造の幅で除算した値より大きくない値を有し、
前記幅が、前記自由SAF構造の長軸に対して直角方向にある前記自由SAF構造の寸法(単位マイクロメートル)である
請求項1記載の磁気抵抗ランダム・アクセス装置。 - 前記自由SAF構造が、2つの磁気部分を備え、
前記2つの磁気部分のそれぞれが、低い磁化材料の層を備える
請求項1記載の磁気抵抗ランダム・アクセス装置。 - 前記少なくとも2つの磁気部分のそれぞれが、Ni、Fe、Co、Ni合金、Fe合金、及びCo合金から成るグループから選択される材料を備える請求項3記載の磁気抵抗ランダム・アクセス装置。
- 前記低い磁化材料が、モリブデン、タンタル及び硼素から成るグループから選択される少なくとも1つの材料を用いてドーピングされる請求項3記載の磁気抵抗ランダム・アクセス装置。
- 前記2つの磁気部分の少なくとも1つが更に、高いスピン偏極材料の層を備える請求項3記載の磁気抵抗ランダム・アクセス装置。
- 前記自由SAF構造が、2つの磁気部分を備え、
前記2つの磁気部分のそれぞれが、約5nmより大きくない厚さを有する
請求項1記載の磁気抵抗ランダム・アクセス装置。 - 前記自由SAF構造が、或る長さと、或る幅と、約1から約3の範囲にある長さ/幅比とを有する請求項1記載の磁気抵抗ランダム・アクセス装置。
- 前記自由SAF構造が、約2から約2.5の範囲にある長さ/幅比を有する請求項8記載の磁気抵抗ランダム・アクセス装置。
- 前記自由SAF構造が、約150Oeから約350Oeの範囲にあるHSATの値を有する請求項1記載の磁気抵抗ランダム・アクセス装置。
- 前記自由SAF構造が、ほぼ180/w0.5(Oe)より小さいHSATの値を有するよう構成され、
ここで、wは、前記自由SAF構造の幅(単位マイクロメートル)である
請求項1記載の磁気抵抗ランダム・アクセス装置。 - 前記自由SAF構造が、2次SAF構造である請求項1記載の磁気抵抗ランダム・アクセス装置。
- 前記自由SAF構造が、反強磁性結合スペーサ層により分離された2つの磁気部分と、前記反強磁性結合スペーサ層のみより高い反強磁性交換結合を生成する材料の層とを備える請求項12記載の磁気抵抗ランダム・アクセス装置。
- 前記自由SAF構造が、反強磁性結合スペーサ層により分離された2つの磁気部分を備え、
前記反強磁性結合スペーサ層の厚さは、前記自由SAF構造が1次SAF構造であるような厚さであり、
前記反強磁性結合スペーサ層の前記厚さは、前記反強磁性結合材料の反強磁性結合飽和磁界HSATが最大である厚さより大きい
請求項1記載の磁気抵抗ランダム・アクセス装置。 - 前記自由SAF構造が、異方性軸を有し、且つ前記異方性軸に実質的に沿って配設された少なくとも1つの実質的に尖頭の端部を有する形状を有する請求項1記載の磁気抵抗ランダム・アクセス装置。
- ディジット・ラインの上に重なる固定の磁気部分を被着するステップと、
前記固定の磁気部分の上に重なるトンネル障壁部分を形成するステップと、
前記トンネル障壁部分の上に重なる第1の磁気部分を被着するステップであって、前記磁気部分がNi80Fe20の磁化より大きくない磁化を有する材料を備える、前記第1の磁気部分を被着するステップと、
前記第1の磁気部分の上に重なる反強磁性結合層を形成するステップと、
前記の反強磁性結合スペーサ層の上に重なる第2の磁気部分を被着するステップであって、前記第2の磁気部分がNi80Fe20の磁化より大きくない磁気モーメントを有する材料を備える、前記第2の磁気部分を被着するステップと、
前記第2の磁気部分の上に重なるビット・ラインを形成するステップと、を備え、
前記第1の磁気部分、前記反強磁性結合層及び前記第2の磁気部分が、自由SAF構造を形成し、
前記第1の磁気部分及び前記第2の磁気部分は、前記自由SAF構造が実質的に均衡化され且つ前記ディジット・ライン及び前記ビット・ラインに対して或る角度に指向された結果的に生じる磁気モーメントを有するように形成される、磁気エレクトロニクス・メモリ素子を製造する方法。 - 前記第1の磁気部分及び前記第2の磁気部分は、それぞれ、Ni、Fe、Co、Ni合金、Fe合金及びCo合金から成るグループから選択される材料から形成される請求項16記載の磁気エレクトロニクス・メモリ素子を製造する方法。
- 第1の磁気部分を被着する前記ステップが、モリブデン、タンタル及び硼素から成るグループから選択される少なくとも1つの材料を備える第1の磁気部分を被着するステップを備える請求項17記載の磁気エレクトロニクス・メモリ素子を製造する方法。
- 第2の磁気部分を被着する前記ステップが、モリブデン、タンタル及び硼素から成るグループから選択される少なくとも1つの材料を備える第2の磁気部分を被着するステップを備える請求項17記載の磁気エレクトロニクス・メモリ素子を製造する方法。
- 第1の磁気部分を被着する前記ステップが更に、前記トンネル障壁部分の上に重なる第1の材料層を被着するステップを備え、
前記第1の材料層が、前記第1の磁気部分のスピン偏極より大きいスピン偏極を有する材料を備え、
第2の磁気部分を被着する前記ステップが更に、第2の材料層を被着するステップであって、前記第2の材料層が、前記自由SAF構造が磁気モーメントについて実質的に均衡化されるように磁気モーメントを有する、前記第2の材料層を被着するステップを備える請求項16記載の磁気エレクトロニクス・メモリ素子を製造する方法。
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US10/997,118 US7129098B2 (en) | 2004-11-24 | 2004-11-24 | Reduced power magnetoresistive random access memory elements |
US10/997,118 | 2004-11-24 | ||
PCT/US2005/042764 WO2006058224A1 (en) | 2004-11-24 | 2005-11-21 | Reduced power magnetoresistive random access memory elements |
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JP5080267B2 JP5080267B2 (ja) | 2012-11-21 |
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JP (1) | JP5080267B2 (ja) |
KR (1) | KR101247255B1 (ja) |
CN (1) | CN100530439C (ja) |
TW (1) | TWI398871B (ja) |
WO (1) | WO2006058224A1 (ja) |
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US7129098B2 (en) | 2006-10-31 |
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US20060108620A1 (en) | 2006-05-25 |
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