JP2008508704A - 基板上で層をエッチングする方法 - Google Patents
基板上で層をエッチングする方法 Download PDFInfo
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- JP2008508704A JP2008508704A JP2007523054A JP2007523054A JP2008508704A JP 2008508704 A JP2008508704 A JP 2008508704A JP 2007523054 A JP2007523054 A JP 2007523054A JP 2007523054 A JP2007523054 A JP 2007523054A JP 2008508704 A JP2008508704 A JP 2008508704A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00444—Surface micromachining, i.e. structuring layers on the substrate
- B81C1/00468—Releasing structures
- B81C1/00476—Releasing structures removing a sacrificial layer
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
- B81C1/00595—Control etch selectivity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Geometry (AREA)
- Pressure Sensors (AREA)
- Micromachines (AREA)
- Drying Of Semiconductors (AREA)
- Investigating Or Analyzing Materials By The Use Of Fluid Adsorption Or Reactions (AREA)
Abstract
Description
本発明は基板上で除去すべき層をエッチングする方法に関する。
本発明の方法は、基板上の珪素−ゲルマニウム合金からなる層を気相エッチングの際にエッチングガスを使用して、特にシリコンからなる基板に対して高い選択性で除去できることにもとづく。特に有利なエッチングガスとしてClF3を使用することが提案される。Si1−xGex層のエッチング特性を合金中のGe部分により制御できる。
本発明の実施例は図面に示され、以下の説明で詳細に説明する。
本発明の方法はまず例示的にマイクロメカニックセンサーの製造方法により示される。図1に示される層系を製造するために、シリコン基板Sub上にまず第1絶縁層1、典型的に厚い断熱酸化物を堆積する。この酸化物層の可能な厚さは数μmの範囲にあり、例えば2.5μmである。
Claims (17)
- 基板(Sub)、特にシリコン基板上で除去すべき層をエッチングする方法において、除去すべき層が基板(Sub)にすでに存在するまたは基板(Sub)に堆積したSi1−xGex層(4,6,10)であり、このSi1−xGex層(4,6,10)を、気相エッチングの際にエッチングガスを使用して少なくとも部分的に除去することを特徴とする基板上で除去すべき層をエッチングする方法。
- エッチングガスとして、BrF3、XeF2またはClF3を使用する請求項1記載の方法。
- Si1−xGex層(4,6,10)のエッチング特性をGe割合により制御する請求項1または2記載の方法。
- Si1−xGex層(4,6,10)がx=0.05〜x=0.5の値の範囲からのxの値を有するGe割合を有する請求項1から3までのいずれか1項記載の方法。
- Si1−xGex層(4,6,10)がx=0.1〜x=0.5の値の範囲からのxの値を有するGe割合を有する請求項4記載の方法。
- Si1−xGex層(4,6,10)がx=0.05〜x=0.3の値の範囲からのxの値を有するGe割合を有する請求項1から3までのいずれか1項記載の方法。
- Si1−xGex層(4,6,10)がx=0.1〜x=0.3の値の範囲からのxの値を有するGe割合を有する請求項6記載の方法。
- 堆積したSi1−xGex層(4,6,10)上にシリコン層(5,7,12)を成長させ、パターン化し、引き続きこのSi構造体を露出するために、Si1−xGex層(4,6,10)を、露出すべき構造体の下の犠牲層または充填層として少なくとも部分的に除去する請求項1から7までのいずれか1項記載の方法。
- Si1−xGex層(4,6,10)とシリコン層(5,7,12)の間に拡散バリアまたは保護層として、特に厚さ10〜100nmを有する酸化物層または窒化物層が存在する請求項8記載の方法。
- シリコン層(5,7,12)としてポリシリコン層をエピタキシャル成長する請求項8または9記載の方法。
- シリコン層(5,7,12)のパターン化を、フッ素ベースグラビアエッチング法を使用して、分離した、それぞれ交互に連続するエッチング工程および重合工程で実施する請求項8から10までのいずれか1項記載の方法。
- Si1−xGex層(4,6,10)を、第1絶縁層(1)、導体層(2)および第2絶縁層(3)が被覆された基板(Sub)上に堆積する請求項1から11までのいずれか1項記載の方法。
- 第1絶縁層(1)としてSiO2層を熱によりSiからなる基板(Sub)に形成する請求項12記載の方法。
- 導体層(2)としてポリシリコン層を被覆し、パターン化する請求項12または13記載の方法。
- 第2絶縁層(3)として酸化物層を被覆する請求項12から14までのいずれか1項記載の方法。
- Si1−xGex層(10)を充填層として1つの領域にセンサー素子と一緒に堆積し、空間(15)を形成するために基板(Sub)にキャップ層(12a)を堆積後に除去する請求項1から11までのいずれか1項記載の方法。
- キャップ層(12a)に、Si1−xGex層(10)にエッチングガスを導く穿孔用孔(14)を設ける請求項16記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004036803.1 | 2004-07-29 | ||
DE102004036803A DE102004036803A1 (de) | 2004-07-29 | 2004-07-29 | Verfahren zum Ätzen einer Schicht auf einem Substrat |
PCT/EP2005/053121 WO2006013137A2 (de) | 2004-07-29 | 2005-07-01 | Verfahren zum ätzen einer sige-schicht auf einem substrat |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2008508704A true JP2008508704A (ja) | 2008-03-21 |
JP2008508704A5 JP2008508704A5 (ja) | 2010-06-24 |
JP4686544B2 JP4686544B2 (ja) | 2011-05-25 |
Family
ID=35124738
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007523054A Expired - Fee Related JP4686544B2 (ja) | 2004-07-29 | 2005-07-01 | 基板上で層をエッチングする方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8182707B2 (ja) |
EP (1) | EP1774572B1 (ja) |
JP (1) | JP4686544B2 (ja) |
KR (1) | KR101130988B1 (ja) |
DE (1) | DE102004036803A1 (ja) |
WO (1) | WO2006013137A2 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012134423A (ja) * | 2010-12-24 | 2012-07-12 | Asahi Kasei Electronics Co Ltd | 半導体装置の製造方法 |
WO2013027653A1 (ja) * | 2011-08-25 | 2013-02-28 | 大日本スクリーン製造株式会社 | パターン形成方法 |
WO2018180670A1 (ja) * | 2017-03-29 | 2018-10-04 | 東京エレクトロン株式会社 | 基板処理方法及び記憶媒体 |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
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DE10234589A1 (de) * | 2002-07-30 | 2004-02-12 | Robert Bosch Gmbh | Schichtsystem mit einer Siliziumschicht und einer Passivierschicht, Verfahren zur Erzeugung einer Passivierschicht auf einer Siliziumschicht und deren Verwendung |
DE102005047081B4 (de) * | 2005-09-30 | 2019-01-31 | Robert Bosch Gmbh | Verfahren zum plasmalosen Ätzen von Silizium mit dem Ätzgas ClF3 oder XeF2 |
DE102006024668A1 (de) | 2006-05-26 | 2007-11-29 | Robert Bosch Gmbh | Mikromechanisches Bauelement und Verfahren zu dessen Herstellung |
DE102006049259A1 (de) | 2006-10-19 | 2008-04-30 | Robert Bosch Gmbh | Verfahren zur Herstellung eines mikromechanischen Bauelementes mit einer Dünnschicht-Verkappung |
DE102007033685A1 (de) | 2007-07-19 | 2009-01-22 | Robert Bosch Gmbh | Verfahren zum Ätzen einer Schicht auf einem Silizium-Halbleitersubstrat |
DE102008042432A1 (de) | 2008-09-29 | 2010-04-01 | Robert Bosch Gmbh | Verfahren zur Herstellung eines Halbleiterbauelements |
DE102010001420A1 (de) | 2010-02-01 | 2011-08-04 | Robert Bosch GmbH, 70469 | III-V-Halbleiter-Solarzelle |
DE102010001504B4 (de) | 2010-02-02 | 2020-07-16 | Robert Bosch Gmbh | Eine Filtereinrichtung und ein Verfahren zur Herstellung einer Filtereinrichtung |
DE102011086610B4 (de) | 2011-11-18 | 2022-11-10 | Robert Bosch Gmbh | Verfahren zur Herstellung von Halbleiterstrukturen auf Siliziumcarbid-Basis |
US9738516B2 (en) | 2015-04-29 | 2017-08-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure to reduce backside silicon damage |
JP7005748B2 (ja) * | 2017-08-31 | 2022-01-24 | グーグル エルエルシー | 量子情報処理デバイス形成 |
DE102017120290B3 (de) * | 2017-09-04 | 2018-11-08 | Infineon Technologies Ag | Verfahren zum Prozessieren einer Schichtstruktur |
CN109437093A (zh) * | 2018-10-26 | 2019-03-08 | 中国科学院苏州纳米技术与纳米仿生研究所 | 自支撑微纳米结构及其制作方法 |
KR102599015B1 (ko) * | 2019-09-11 | 2023-11-06 | 주식회사 테스 | 기판 처리 방법 |
US11791155B2 (en) * | 2020-08-27 | 2023-10-17 | Applied Materials, Inc. | Diffusion barriers for germanium |
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JPH0192385A (ja) * | 1987-09-30 | 1989-04-11 | Iwatani Internatl Corp | 金属類物質又はその化合物を材質とする部材の微細加工方法 |
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2004
- 2004-07-29 DE DE102004036803A patent/DE102004036803A1/de not_active Ceased
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2005
- 2005-07-01 JP JP2007523054A patent/JP4686544B2/ja not_active Expired - Fee Related
- 2005-07-01 EP EP05761141.0A patent/EP1774572B1/de not_active Expired - Fee Related
- 2005-07-01 WO PCT/EP2005/053121 patent/WO2006013137A2/de active Application Filing
- 2005-07-01 KR KR1020077002100A patent/KR101130988B1/ko active IP Right Grant
- 2005-07-01 US US11/658,461 patent/US8182707B2/en active Active
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JPH0192385A (ja) * | 1987-09-30 | 1989-04-11 | Iwatani Internatl Corp | 金属類物質又はその化合物を材質とする部材の微細加工方法 |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012134423A (ja) * | 2010-12-24 | 2012-07-12 | Asahi Kasei Electronics Co Ltd | 半導体装置の製造方法 |
WO2013027653A1 (ja) * | 2011-08-25 | 2013-02-28 | 大日本スクリーン製造株式会社 | パターン形成方法 |
JPWO2013027653A1 (ja) * | 2011-08-25 | 2015-03-19 | 大日本スクリーン製造株式会社 | パターン形成方法 |
US9082725B2 (en) | 2011-08-25 | 2015-07-14 | SCREEN Holdings Co., Ltd. | Pattern forming method |
WO2018180670A1 (ja) * | 2017-03-29 | 2018-10-04 | 東京エレクトロン株式会社 | 基板処理方法及び記憶媒体 |
Also Published As
Publication number | Publication date |
---|---|
JP4686544B2 (ja) | 2011-05-25 |
WO2006013137A2 (de) | 2006-02-09 |
KR101130988B1 (ko) | 2012-03-28 |
DE102004036803A1 (de) | 2006-03-23 |
EP1774572B1 (de) | 2016-09-28 |
KR20070046087A (ko) | 2007-05-02 |
US8182707B2 (en) | 2012-05-22 |
WO2006013137A3 (de) | 2006-04-06 |
EP1774572A2 (de) | 2007-04-18 |
US20080311751A1 (en) | 2008-12-18 |
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