JP2008505497A - 二層レジストプラズマエッチングの方法 - Google Patents
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/094—Multilayer resist systems, e.g. planarising layers
Abstract
【解決手段】プラズマエッチング室内において、基板の上に形成された二層レジストをエッチングするための方法が提供される。該方法は、二層レジストの第1の層の上にパターンを形成された基板をエッチング室に導入する工程から開始される。次いで、SiCl4ガスがエッチング室に流し込まれる。次に、SiCl4ガスを流し入れつつエッチング室内においてプラズマを発生させる。次いで、二層レジストがエッチングされる。
【選択図】図15
Description
Claims (19)
- プラズマエッチング室内において、基板の上に形成された二層レジストをエッチングするための方法であって、
前記二層レジストの第1の層の上にパターンが形成されている前記基板を、前記プラズマエッチング室に導入し、
前記プラズマエッチング室にSiCl4ガスを流入させ、
前記SiCl4ガスを流し入れつつ前記プラズマエッチング室内においてプラズマを発生させ、
前記二層レジストをエッチングする、方法。 - 請求項1に記載の方法であって、
前記プラズマエッチング室へのSiCl4ガスの流入は、前記SiCl4ガスを約0.1立方センチメートル毎分(sccm)と6sccmとの間の流量で流すことを含む、方法。 - 請求項1に記載の方法であって、更に、
前記プラズマエッチング室に塩素ガスを流し入れ、
前記プラズマエッチング室に臭化水素ガスを流し入れ、
前記プラズマエッチング室に不活性ガスを流し入れる、方法。 - 請求項3に記載の方法であって、
前記不活性ガスは窒素である、方法。 - 請求項1に記載の方法であって、
前記SiCl4ガスの流入の間に行われる前記プラズマエッチング室内におけるプラズマの発生は、酸素をベースにしたプラズマを生成することを含む、方法。 - 請求項1に記載の方法であって、
前記SiCl4ガスの流入の間に行われる前記プラズマエッチング室内におけるプラズマの発生は、プラズマ密度を約1×109/cm3から約1×1012/cm3までの間に維持することを含む、方法。 - 請求項1に記載の方法であって、
前記SiCl4ガスの流入の間に行われる前記プラズマエッチング室内におけるプラズマの発生は、イオンエネルギを約150ボルトから約400ボルトまでの間に維持することを含む、方法。 - 請求項6に記載の方法であって、
プラズマ密度の約1×109/cm3から約1×1012/cm3までの間での維持は、室圧を約3ミリトールから約15ミリトールまでの間に設定することと、前記プラズマエッチング室の上部電極の電力レベルを約300ワットから約1000ワットまでの間に設定することとを含む、方法。 - 請求項7に記載の方法であって、
イオンエネルギの約150ボルトから約400ボルトまでの間での維持は、下部電極のための高周波(RF)ピーク電圧を約200ボルトから300ボルトまでの間に設定することを含む、方法。 - 請求項1に記載の方法であって、
前記SiCl4ガスの流入の間に行われる前記プラズマエッチング室内におけるプラズマの発生は、室温を摂氏約20度から摂氏約70度までの間に維持することを含む、方法。 - エッチング室内において、二層レジストのエッチング中に限界寸法の偏りを制御するための方法であって、
前記エッチング室にSiCl4ガスを流入させつつ前記エッチング室内において酸素をベースにしたプラズマを発生させ、
プラズマ密度を約1×109/cm3から約1×1012/cm3までの間に維持し、
前記二層レジストの各層をエッチングする、方法。 - 請求項11に記載の方法であって、
前記エッチング室へのSiCl4ガスの流入の間に行われる前記エッチング室内における酸素をベースにしたプラズマの発生は、
前記エッチング室に塩素ガスを流し入れることと、
前記エッチング室に臭化水素(HBr)ガスを流し入れることと、
前記エッチング室に不活性ガスを流し入れることと、を含む方法。 - 請求項11に記載の方法であって、
前記エッチング室へのSiCl4ガスの流入の間に行われる前記エッチング室内における酸素をベースにしたプラズマの発生は、前記SiCl4ガスを約0.1sccm(立方センチメートル毎分)から6sccmまでの間の流量で前記エッチング室に流し入れることを含む、方法。 - 請求項11に記載の方法であって、更に、
イオンエネルギ約150ボルトから約400ボルトまでの間に維持することを備える方法。 - 請求項14に記載の方法であって、
イオンエネルギの約150ボルトから約400ボルトまでの間での維持は、下部電極のための高周波(RF)ピーク電圧を約200ボルトから300ボルトまでの間に設定することを含む、方法。 - 請求項11に記載の方法であって、
プラズマ密度の約1×109/cm3から約1×1012/cm3までの間での維持は、上部電極に関連した電力レベルを約300ワットから約1000ワットまでの間に維持することを含む、方法。 - 請求項12に記載の方法であって、更に、
前記エッチング室に入れる酸素ガスの流量の、前記エッチング室に入れる塩素ガスに対する比を、約10:1に維持する工程を備える方法。 - 請求項12に記載の方法であって、
前記不活性ガスの流量は約50sccmから約200sccmまでの間であり、前記臭化水素(HBr)ガスの流量は約50sccmから約100sccmまでの間であり、前記塩素ガスの流量は約10sccmから約50sccmまでの間である、方法。 - 請求項11に記載の方法であって、
前記二層レジストは、第2の層の上に設けられた、シリコンを含有する第1の層を含む、方法。
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US10/882,842 US7141505B2 (en) | 2003-06-27 | 2004-06-30 | Method for bilayer resist plasma etch |
PCT/US2005/022809 WO2006004693A2 (en) | 2004-06-30 | 2005-06-27 | Method for bilayer resist plasma etch |
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JP2012168475A Division JP2013030778A (ja) | 2004-06-30 | 2012-07-30 | 二層レジストプラズマエッチングの方法 |
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JP2007519342A Pending JP2008505497A (ja) | 2004-06-30 | 2005-06-27 | 二層レジストプラズマエッチングの方法 |
JP2012168475A Withdrawn JP2013030778A (ja) | 2004-06-30 | 2012-07-30 | 二層レジストプラズマエッチングの方法 |
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US (1) | US7141505B2 (ja) |
EP (1) | EP1774542A4 (ja) |
JP (2) | JP2008505497A (ja) |
KR (1) | KR101111924B1 (ja) |
CN (1) | CN1985335B (ja) |
IL (1) | IL180025A (ja) |
TW (1) | TWI284372B (ja) |
WO (1) | WO2006004693A2 (ja) |
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JP2007250940A (ja) * | 2006-03-17 | 2007-09-27 | Hitachi High-Technologies Corp | ドライエッチング方法 |
JP2009238889A (ja) * | 2008-03-26 | 2009-10-15 | Tokyo Electron Ltd | エッチング方法及び半導体デバイスの製造方法 |
WO2010110081A1 (ja) * | 2009-03-25 | 2010-09-30 | 東京エレクトロン株式会社 | マイクロレンズアレイの製造方法およびマイクロレンズアレイ |
KR20150031227A (ko) | 2012-06-15 | 2015-03-23 | 도쿄엘렉트론가부시키가이샤 | 플라즈마 에칭 방법 및 플라즈마 처리 장치 |
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US8124537B2 (en) * | 2008-02-12 | 2012-02-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for etching integrated circuit structure |
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CN103367863B (zh) * | 2012-04-09 | 2015-02-18 | 中国科学院上海微系统与信息技术研究所 | 一种集成宽频带天线及其制作方法 |
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Cited By (7)
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JP2007250940A (ja) * | 2006-03-17 | 2007-09-27 | Hitachi High-Technologies Corp | ドライエッチング方法 |
JP2009238889A (ja) * | 2008-03-26 | 2009-10-15 | Tokyo Electron Ltd | エッチング方法及び半導体デバイスの製造方法 |
KR101110238B1 (ko) * | 2008-03-26 | 2012-03-14 | 도쿄엘렉트론가부시키가이샤 | 에칭 방법 및 반도체 디바이스의 제조 방법 |
WO2010110081A1 (ja) * | 2009-03-25 | 2010-09-30 | 東京エレクトロン株式会社 | マイクロレンズアレイの製造方法およびマイクロレンズアレイ |
JP2010224471A (ja) * | 2009-03-25 | 2010-10-07 | Tokyo Electron Ltd | マイクロレンズアレイの製造方法およびマイクロレンズアレイ |
US9147580B2 (en) | 2012-04-05 | 2015-09-29 | Tokyo Electron Limited | Plasma etching method and plasma processing apparatus |
KR20150031227A (ko) | 2012-06-15 | 2015-03-23 | 도쿄엘렉트론가부시키가이샤 | 플라즈마 에칭 방법 및 플라즈마 처리 장치 |
Also Published As
Publication number | Publication date |
---|---|
IL180025A0 (en) | 2007-05-15 |
CN1985335A (zh) | 2007-06-20 |
TWI284372B (en) | 2007-07-21 |
WO2006004693A3 (en) | 2006-05-04 |
EP1774542A2 (en) | 2007-04-18 |
US20050023242A1 (en) | 2005-02-03 |
US7141505B2 (en) | 2006-11-28 |
EP1774542A4 (en) | 2008-12-24 |
KR20070032961A (ko) | 2007-03-23 |
KR101111924B1 (ko) | 2012-02-17 |
JP2013030778A (ja) | 2013-02-07 |
TW200612494A (en) | 2006-04-16 |
IL180025A (en) | 2011-06-30 |
WO2006004693A2 (en) | 2006-01-12 |
CN1985335B (zh) | 2010-05-12 |
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