JP2007538474A5 - - Google Patents

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Publication number
JP2007538474A5
JP2007538474A5 JP2007527379A JP2007527379A JP2007538474A5 JP 2007538474 A5 JP2007538474 A5 JP 2007538474A5 JP 2007527379 A JP2007527379 A JP 2007527379A JP 2007527379 A JP2007527379 A JP 2007527379A JP 2007538474 A5 JP2007538474 A5 JP 2007538474A5
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JP
Japan
Prior art keywords
programmable logic
pld
logic device
transistor
circuit
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Pending
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JP2007527379A
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English (en)
Japanese (ja)
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JP2007538474A (ja
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Priority claimed from US10/848,953 external-priority patent/US7348827B2/en
Priority claimed from US10/865,402 external-priority patent/US7129745B2/en
Application filed filed Critical
Publication of JP2007538474A publication Critical patent/JP2007538474A/ja
Publication of JP2007538474A5 publication Critical patent/JP2007538474A5/ja
Pending legal-status Critical Current

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JP2007527379A 2004-05-19 2005-05-18 集積回路の性能を調整するための装置および方法 Pending JP2007538474A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/848,953 US7348827B2 (en) 2004-05-19 2004-05-19 Apparatus and methods for adjusting performance of programmable logic devices
US10/865,402 US7129745B2 (en) 2004-05-19 2004-06-10 Apparatus and methods for adjusting performance of integrated circuits
PCT/US2005/017265 WO2005116878A2 (en) 2004-05-19 2005-05-18 Apparatus and methods for adjusting performance of integrated circuits

Publications (2)

Publication Number Publication Date
JP2007538474A JP2007538474A (ja) 2007-12-27
JP2007538474A5 true JP2007538474A5 (enExample) 2008-07-03

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JP2007527379A Pending JP2007538474A (ja) 2004-05-19 2005-05-18 集積回路の性能を調整するための装置および方法

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US (3) US7129745B2 (enExample)
EP (1) EP1776759B1 (enExample)
JP (1) JP2007538474A (enExample)
CN (1) CN102361449B (enExample)
WO (1) WO2005116878A2 (enExample)

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