JP2007538474A - 集積回路の性能を調整するための装置および方法 - Google Patents

集積回路の性能を調整するための装置および方法 Download PDF

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Publication number
JP2007538474A
JP2007538474A JP2007527379A JP2007527379A JP2007538474A JP 2007538474 A JP2007538474 A JP 2007538474A JP 2007527379 A JP2007527379 A JP 2007527379A JP 2007527379 A JP2007527379 A JP 2007527379A JP 2007538474 A JP2007538474 A JP 2007538474A
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Japan
Prior art keywords
pld
body bias
programmable logic
circuit
logic device
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Pending
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JP2007527379A
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English (en)
Japanese (ja)
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JP2007538474A5 (enExample
Inventor
デイビッド ルイス，
ボーン ベッツ，
イルファン ラヒム，
ピーター マクレニー，
ヨウ−ジュアン ダブリュー． リュー，
ブルース ペダーセン，
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Altera Corp
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Altera Corp
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Priority claimed from US10/848,953 external-priority patent/US7348827B2/en
Application filed by Altera Corp filed Critical Altera Corp
Publication of JP2007538474A publication Critical patent/JP2007538474A/ja
Publication of JP2007538474A5 publication Critical patent/JP2007538474A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00156—Layout of the delay element using opamps, comparators, voltage multipliers or other analog building blocks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0018—Special modifications or use of the back gate voltage of a FET

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Pulse Circuits (AREA)
JP2007527379A 2004-05-19 2005-05-18 集積回路の性能を調整するための装置および方法 Pending JP2007538474A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/848,953 US7348827B2 (en) 2004-05-19 2004-05-19 Apparatus and methods for adjusting performance of programmable logic devices
US10/865,402 US7129745B2 (en) 2004-05-19 2004-06-10 Apparatus and methods for adjusting performance of integrated circuits
PCT/US2005/017265 WO2005116878A2 (en) 2004-05-19 2005-05-18 Apparatus and methods for adjusting performance of integrated circuits

Publications (2)

Publication Number Publication Date
JP2007538474A true JP2007538474A (ja) 2007-12-27
JP2007538474A5 JP2007538474A5 (enExample) 2008-07-03

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JP2007527379A Pending JP2007538474A (ja) 2004-05-19 2005-05-18 集積回路の性能を調整するための装置および方法

Country Status (5)

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US (3) US7129745B2 (enExample)
EP (1) EP1776759B1 (enExample)
JP (1) JP2007538474A (enExample)
CN (1) CN102361449B (enExample)
WO (1) WO2005116878A2 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007243178A (ja) * 2006-03-06 2007-09-20 Altera Corp 調整可能なトランジスタボディバイアス回路網
JP2013046068A (ja) * 2011-08-19 2013-03-04 Altera Corp フィールドプログラマブルゲートアレイの性能を向上させるための装置および関連方法
JPWO2021251206A1 (enExample) * 2020-06-09 2021-12-16

Families Citing this family (93)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7180322B1 (en) 2002-04-16 2007-02-20 Transmeta Corporation Closed loop feedback control of integrated circuits
US7886164B1 (en) 2002-11-14 2011-02-08 Nvidia Corporation Processor temperature adjustment system and method
US7849332B1 (en) 2002-11-14 2010-12-07 Nvidia Corporation Processor voltage adjustment system and method
US7882369B1 (en) 2002-11-14 2011-02-01 Nvidia Corporation Processor performance adjustment system and method
US7205758B1 (en) * 2004-02-02 2007-04-17 Transmeta Corporation Systems and methods for adjusting threshold voltage
US7949864B1 (en) * 2002-12-31 2011-05-24 Vjekoslav Svilan Balanced adaptive body bias control
US7649402B1 (en) 2003-12-23 2010-01-19 Tien-Min Chen Feedback-controlled body-bias voltage source
US7816742B1 (en) 2004-09-30 2010-10-19 Koniaris Kleanthes G Systems and methods for integrated circuits comprising multiple body biasing domains
US7859062B1 (en) 2004-02-02 2010-12-28 Koniaris Kleanthes G Systems and methods for integrated circuits comprising multiple body biasing domains
FR2868181B1 (fr) * 2004-03-29 2006-05-26 Soisic Sa Procede de simulation d'un circuit a l'etat stationnaire
US7112997B1 (en) * 2004-05-19 2006-09-26 Altera Corporation Apparatus and methods for multi-gate silicon-on-insulator transistors
US7348827B2 (en) * 2004-05-19 2008-03-25 Altera Corporation Apparatus and methods for adjusting performance of programmable logic devices
US7400167B2 (en) 2005-08-16 2008-07-15 Altera Corporation Apparatus and methods for optimizing the performance of programmable logic devices
US7326972B2 (en) * 2004-06-30 2008-02-05 Intel Corporation Interconnect structure in integrated circuits
US7509504B1 (en) * 2004-09-30 2009-03-24 Transmeta Corporation Systems and methods for control of integrated circuits comprising body biasing systems
EP1820083A1 (en) * 2004-11-10 2007-08-22 Freescale Semiconductor, Inc. Apparatus and method for controlling voltage and frequency using multiple reference circuits
US7739531B1 (en) 2005-03-04 2010-06-15 Nvidia Corporation Dynamic voltage scaling
US7394708B1 (en) * 2005-03-18 2008-07-01 Xilinx, Inc. Adjustable global tap voltage to improve memory cell yield
US7295036B1 (en) * 2005-11-30 2007-11-13 Altera Corporation Method and system for reducing static leakage current in programmable logic devices
US8010931B1 (en) * 2006-02-24 2011-08-30 University Of Southern California Tool for a configurable integrated circuit that uses determination of dynamic power consumption
WO2007096913A1 (en) * 2006-02-24 2007-08-30 Stmicroelectronics S.R.L. Method for designing a complex integrated electronic circuit architecture
US7936184B2 (en) * 2006-02-24 2011-05-03 Altera Corporation Apparatus and methods for adjusting performance of programmable logic devices
US7355437B2 (en) 2006-03-06 2008-04-08 Altera Corporation Latch-up prevention circuitry for integrated circuits with transistor body biasing
US7330049B2 (en) * 2006-03-06 2008-02-12 Altera Corporation Adjustable transistor body bias generation circuitry with latch-up prevention
US7486106B1 (en) * 2006-03-24 2009-02-03 Altera Corporation CPLD for multi-wire keyboard decode with timed power control circuit
US7463057B1 (en) 2006-03-29 2008-12-09 Altera Corporation Integrated circuits with adjustable memory element power supplies
US7891865B2 (en) * 2006-05-03 2011-02-22 International Business Machines Corporation Structure for bolometric on-chip temperature sensor
JP2007311535A (ja) * 2006-05-18 2007-11-29 Matsushita Electric Ind Co Ltd セル配置方法
KR100784908B1 (ko) * 2006-08-11 2007-12-11 주식회사 하이닉스반도체 전압 조절 장치
US20080180129A1 (en) * 2006-08-31 2008-07-31 Actel Corporation Fpga architecture with threshold voltage compensation and reduced leakage
US7388531B1 (en) * 2006-09-26 2008-06-17 Marvell International Ltd. Current steering DAC using thin oxide devices
US7826549B1 (en) * 2006-11-02 2010-11-02 Sudhir Aggarwal Wireless communication transmitter and system having the same
US8705300B1 (en) * 2007-02-27 2014-04-22 Altera Corporation Memory array circuitry with stability enhancement features
US7889751B2 (en) * 2007-03-06 2011-02-15 Sudhir Aggarwal Low power wireless communication system
US9134782B2 (en) 2007-05-07 2015-09-15 Nvidia Corporation Maintaining optimum voltage supply to match performance of an integrated circuit
JP5162956B2 (ja) * 2007-05-11 2013-03-13 ソニー株式会社 半導体集積回路およびその動作方法
US7716615B2 (en) * 2007-08-31 2010-05-11 International Business Machines Corporation Redundant critical path circuits to meet performance requirement
US7675317B2 (en) * 2007-09-14 2010-03-09 Altera Corporation Integrated circuits with adjustable body bias and power supply circuitry
US8949763B1 (en) * 2007-10-02 2015-02-03 Altera Corporation Apparatus and methods for optimization of integrated circuits
US7890893B2 (en) * 2008-01-10 2011-02-15 International Business Machines Corporation Design structure for semiconductor on-chip repair scheme for negative bias temperature instability
US7679537B2 (en) * 2008-01-21 2010-03-16 Honeywell International Inc. Precision microcontroller-based pulse width modulation digital-to-analog conversion circuit and method
US8370663B2 (en) 2008-02-11 2013-02-05 Nvidia Corporation Power management with dynamic frequency adjustments
US20090267588A1 (en) * 2008-04-23 2009-10-29 Schmitz Michael J Method and apparatus to dynamically control impedance to maximize power supply
US8102187B2 (en) * 2008-05-02 2012-01-24 Texas Instruments Incorporated Localized calibration of programmable digital logic cells
US20090292849A1 (en) * 2008-05-22 2009-11-26 Khoo Ken Adaptable pci express controller core
US20090302887A1 (en) * 2008-06-10 2009-12-10 Tad Kwasniewski Apparatus for power consumption reduction in programmable logic devices and associated methods
US8099704B1 (en) * 2008-07-28 2012-01-17 Altera Corporation Performance improvements in an integrated circuit by selectively applying forward bias voltages
US7639041B1 (en) * 2008-07-28 2009-12-29 Altera Corporation Hotsocket-compatible body bias circuitry with power-up current reduction capabilities
US7952423B2 (en) * 2008-09-30 2011-05-31 Altera Corporation Process/design methodology to enable high performance logic and analog circuits using a single process
WO2010052607A1 (en) * 2008-11-05 2010-05-14 Nxp B.V. Body biasing
US7911261B1 (en) 2009-04-13 2011-03-22 Netlogic Microsystems, Inc. Substrate bias circuit and method for integrated circuit device
US8072237B1 (en) 2009-06-04 2011-12-06 Altera Corporation Computer-aided design tools and memory element power supply circuitry for selectively overdriving circuit blocks
US8181147B2 (en) * 2009-06-29 2012-05-15 Lsi Corporation Parametric data-based process monitoring for adaptive body bias control
JP5529450B2 (ja) * 2009-07-15 2014-06-25 スパンション エルエルシー ボディバイアス制御回路及びボディバイアス制御方法
KR101695493B1 (ko) 2009-07-15 2017-01-11 엘지전자 주식회사 조리기기 및 제어방법
US9256265B2 (en) 2009-12-30 2016-02-09 Nvidia Corporation Method and system for artificially and dynamically limiting the framerate of a graphics processing unit
US9830889B2 (en) 2009-12-31 2017-11-28 Nvidia Corporation Methods and system for artifically and dynamically limiting the display resolution of an application
US8839006B2 (en) 2010-05-28 2014-09-16 Nvidia Corporation Power consumption reduction systems and methods
US8907678B2 (en) * 2010-12-10 2014-12-09 Raritan Americas, Inc. Methods and apparatus for sensing ground leakage and automated self testing thereof
US9495503B2 (en) * 2011-04-06 2016-11-15 Qualcomm Incorporated Method and apparatus to enable a selective push process during manufacturing to improve performance of a selected circuit of an integrated circuit
US8816470B2 (en) 2011-04-21 2014-08-26 International Business Machines Corporation Independently voltage controlled volume of silicon on a silicon on insulator chip
US8456187B2 (en) 2011-04-21 2013-06-04 International Business Machines Corporation Implementing temporary disable function of protected circuitry by modulating threshold voltage of timing sensitive circuit
US8525245B2 (en) 2011-04-21 2013-09-03 International Business Machines Corporation eDRAM having dynamic retention and performance tradeoff
US8492207B2 (en) 2011-04-21 2013-07-23 International Business Machines Corporation Implementing eFuse circuit with enhanced eFuse blow operation
WO2012157532A1 (en) 2011-05-16 2012-11-22 Semiconductor Energy Laboratory Co., Ltd. Programmable logic device
US8779799B2 (en) 2011-05-19 2014-07-15 Semiconductor Energy Laboratory Co., Ltd. Logic circuit
JP5892852B2 (ja) 2011-05-20 2016-03-23 株式会社半導体エネルギー研究所 プログラマブルロジックデバイス
US8669781B2 (en) 2011-05-31 2014-03-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR101318423B1 (ko) * 2011-06-24 2013-10-15 위니맥스 주식회사 정수필터 어셈블리 및 이를 구비한 냉장고 및 정수기
US8416009B2 (en) 2011-07-13 2013-04-09 International Business Machines Corporation Solutions for controlling bulk bias voltage in an extremely thin silicon-on-insulator (ETSOI) integrated circuit chip
US8633731B1 (en) 2011-08-09 2014-01-21 Altera Corporation Programmable integrated circuit with thin-oxide passgates
US8461869B1 (en) * 2011-08-19 2013-06-11 Altera Corporation Apparatus for configuring performance of field programmable gate arrays and associated methods
US8730713B2 (en) 2011-09-12 2014-05-20 Qualcomm Incorporated SRAM cell writability
US9436250B1 (en) 2011-12-19 2016-09-06 Altera Corporation Apparatus for improving power consumption of communication circuitry and associated methods
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
KR102013607B1 (ko) 2012-12-10 2019-08-23 삼성전자주식회사 반도체 장치 및 그것의 바디 바이어스 방법
US9201994B1 (en) 2013-03-13 2015-12-01 Calypto Design Systems, Inc. Flexible power query interfaces and infrastructures
US9100002B2 (en) * 2013-09-12 2015-08-04 Micron Technology, Inc. Apparatus and methods for leakage current reduction in integrated circuits
US9444460B1 (en) 2013-11-22 2016-09-13 Altera Corporation Integrated circuits with programmable overdrive capabilities
US9177096B2 (en) * 2014-03-26 2015-11-03 Freescale Semiconductor, Inc. Timing closure using transistor sizing in standard cells
KR102140787B1 (ko) * 2014-07-07 2020-08-03 삼성전자주식회사 저항성 메모리 장치, 저항성 메모리 시스템 및 저항성 메모리 장치의 동작방법
US9628081B2 (en) * 2014-08-12 2017-04-18 Xilinx, Inc. Interconnect circuits having low threshold voltage P-channel transistors for a programmable integrated circuit
US9496871B1 (en) * 2014-08-18 2016-11-15 Xilinx, Inc. Programmable power reduction technique using transistor threshold drops
US9893725B2 (en) * 2014-08-27 2018-02-13 Nxp Usa, Inc. Low side and high side drivers for a motor
US9361994B1 (en) * 2014-09-04 2016-06-07 Cypress Semiconductor Corporation Method of increasing read current window in non-volatile memory
CN105677932A (zh) * 2014-11-19 2016-06-15 复旦大学 用于带后硅可调寄存器电路的统计时序分析方法
US9625924B2 (en) * 2015-09-22 2017-04-18 Qualcomm Incorporated Leakage current supply circuit for reducing low drop-out voltage regulator headroom
JP2017079037A (ja) * 2015-10-22 2017-04-27 富士通株式会社 演算装置及びその方法
US9678150B2 (en) * 2015-10-27 2017-06-13 Xilinx, Inc. Methods and circuits for debugging circuit designs
US9934341B2 (en) 2015-11-11 2018-04-03 International Business Machines Corporation Simulation of modifications to microprocessor design
US10121534B1 (en) 2015-12-18 2018-11-06 Altera Corporation Integrated circuit with overdriven and underdriven pass gates
US10591946B2 (en) * 2017-07-13 2020-03-17 Realtek Semiconductor Corp. Electronic device, power circuit applied to the electronic device, and associated method
IT201900001941A1 (it) * 2019-02-11 2020-08-11 St Microelectronics Des & Appl Circuito con l'utilizzo di mosfet e procedimento corrispondente

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61160960A (ja) * 1985-01-08 1986-07-21 Matsushita Electric Ind Co Ltd 半導体集積回路
JPH04247653A (ja) * 1991-02-04 1992-09-03 Ricoh Co Ltd 半導体集積回路装置の遅延補正装置
JPH05108194A (ja) * 1991-10-17 1993-04-30 Hitachi Ltd 低消費電力型半導体集積回路
JP2000101416A (ja) * 1998-09-14 2000-04-07 Texas Instr Inc <Ti> Ｍｏｓ集積回路の特性を改良するためのボディ電圧のパルス動作
JP2001156261A (ja) * 1999-09-13 2001-06-08 Hitachi Ltd 半導体集積回路装置
JP2001345693A (ja) * 2000-05-30 2001-12-14 Hitachi Ltd 半導体集積回路装置
JP2003110028A (ja) * 2001-10-01 2003-04-11 Hitachi Ltd データ処理装置
JP2003168735A (ja) * 2001-11-30 2003-06-13 Hitachi Ltd 半導体集積回路装置

Family Cites Families (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS601071A (ja) 1983-06-18 1985-01-07 三菱電機株式会社 電気機関車の中間台車用揺れ枕装置
JPH0335473A (ja) 1989-06-30 1991-02-15 Mitsubishi Electric Corp 磁気記録再生装置
JPH03269248A (ja) 1990-03-19 1991-11-29 Fujitsu Ltd 物体検査装置
DE4221575C2 (de) * 1992-07-01 1995-02-09 Ibm Integrierter CMOS-Halbleiterschaltkreis und Datenverarbeitungssystem mit integriertem CMOS-Halbleiterschaltkreis
US5341034A (en) * 1993-02-11 1994-08-23 Benchmarq Microelectronics, Inc. Backup battery power controller having channel regions of transistors being biased by power supply or battery
KR0169157B1 (ko) * 1993-11-29 1999-02-01 기다오까 다까시 반도체 회로 및 mos-dram
US5422591A (en) * 1994-01-03 1995-06-06 Sgs-Thomson Microelectronics, Inc. Output driver circuit with body bias control for multiple power supply operation
US5689209A (en) * 1994-12-30 1997-11-18 Siliconix Incorporated Low-side bidirectional battery disconnect switch
JP3641511B2 (ja) * 1995-06-16 2005-04-20 株式会社ルネサステクノロジ 半導体装置
US5689144A (en) * 1996-05-15 1997-11-18 Siliconix Incorporated Four-terminal power MOSFET switch having reduced threshold voltage and on-resistance
US6118302A (en) * 1996-05-28 2000-09-12 Altera Corporation Interface for low-voltage semiconductor devices
KR100189752B1 (ko) * 1996-06-01 1999-06-01 구본준 독립적인 웰 바이어스 전압을 가진 전압 펌프회로
JP3264622B2 (ja) * 1996-07-16 2002-03-11 株式会社東芝 半導体装置
US5880620A (en) * 1997-04-22 1999-03-09 Xilinx, Inc. Pass gate circuit with body bias control
US6593799B2 (en) * 1997-06-20 2003-07-15 Intel Corporation Circuit including forward body bias from supply voltage and ground nodes
US6411156B1 (en) * 1997-06-20 2002-06-25 Intel Corporation Employing transistor body bias in controlling chip parameters
US5841694A (en) * 1997-07-30 1998-11-24 Programmable Silicon Solutions High performance programmable interconnect
US6535034B1 (en) * 1997-07-30 2003-03-18 Programmable Silicon Solutions High performance integrated circuit devices adaptable to use lower supply voltages with smaller device geometries
US6097242A (en) * 1998-02-26 2000-08-01 Micron Technology, Inc. Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits
US6147508A (en) * 1998-08-20 2000-11-14 International Business Machines Corp. Power consumption control mechanism and method therefor
US6826730B2 (en) * 1998-12-15 2004-11-30 Texas Instruments Incorporated System and method for controlling current in an integrated circuit
US6038194A (en) * 1998-12-28 2000-03-14 Philips Electronics North America Corporation Memory decoder with zero static power
US6484265B2 (en) * 1998-12-30 2002-11-19 Intel Corporation Software control of transistor body bias in controlling chip parameters
US6271713B1 (en) * 1999-05-14 2001-08-07 Intel Corporation Dynamic threshold source follower voltage driver circuit
JP2001034040A (ja) * 1999-07-21 2001-02-09 Sharp Corp 接触帯電装置ならびにそれを備えたプロセスカートリッジおよび画像形成装置
US6448840B2 (en) * 1999-11-30 2002-09-10 Intel Corporation Adaptive body biasing circuit and method
KR100347140B1 (ko) * 1999-12-31 2002-08-03 주식회사 하이닉스반도체 전압 변환 회로
KR20010077099A (ko) * 2000-01-31 2001-08-17 윤종용 자기 정렬된 웰 바이어스 영역을 갖는 모스 트랜지스터 및그 제조방법
US20020140496A1 (en) * 2000-02-16 2002-10-03 Ali Keshavarzi Forward body biased transistors with reduced temperature
US6549032B1 (en) * 2000-08-22 2003-04-15 Altera Corporation Integrated circuit devices with power supply detection circuitry
TW463466B (en) * 2000-08-30 2001-11-11 Silicon Integrated Sys Corp Current A/D converter and the unit cell thereof
TW448617B (en) * 2000-09-15 2001-08-01 Silicon Integrated Sys Corp N-well bias preset circuit for CMOS and the method thereof
US6343044B1 (en) * 2000-10-04 2002-01-29 International Business Machines Corporation Super low-power generator system for embedded applications
US6744301B1 (en) * 2000-11-07 2004-06-01 Intel Corporation System using body-biased sleep transistors to reduce leakage power while minimizing performance penalties and noise
JP2002164544A (ja) * 2000-11-28 2002-06-07 Sony Corp 半導体装置
KR100385230B1 (ko) * 2000-12-28 2003-05-27 삼성전자주식회사 불휘발성 반도체 메모리 장치의 프로그램 방법
US6373281B1 (en) * 2001-01-22 2002-04-16 International Business Machines Corporation Tri-state dynamic body charge modulation for sensing devices in SOI RAM applications
US6429726B1 (en) * 2001-03-27 2002-08-06 Intel Corporation Robust forward body bias generation circuit with digital trimming for DC power supply variation
US6469572B1 (en) * 2001-03-28 2002-10-22 Intel Corporation Forward body bias generation circuits based on diode clamps
US6670655B2 (en) * 2001-04-18 2003-12-30 International Business Machines Corporation SOI CMOS device with body to gate connection
US6605981B2 (en) * 2001-04-26 2003-08-12 International Business Machines Corporation Apparatus for biasing ultra-low voltage logic circuits
JP2002343083A (ja) * 2001-05-18 2002-11-29 Mitsubishi Electric Corp 半導体装置
US6554249B2 (en) * 2001-05-30 2003-04-29 Fmc Technologies, Inc. Plug valve having seal segments with booster springs
US6483375B1 (en) * 2001-06-28 2002-11-19 Intel Corporation Low power operation mechanism and method
US6518826B2 (en) * 2001-06-28 2003-02-11 Intel Corporation Method and apparatus for dynamic leakage control
US6763484B2 (en) * 2001-06-28 2004-07-13 Intel Corporation Body bias using scan chains
US6559702B2 (en) * 2001-07-19 2003-05-06 Texas Instruments Incorporated Bias generator and method for improving output skew voltage
US6529421B1 (en) * 2001-08-28 2003-03-04 Micron Technology, Inc. SRAM array with temperature-compensated threshold voltage
US6621325B2 (en) * 2001-09-18 2003-09-16 Xilinx, Inc. Structures and methods for selectively applying a well bias to portions of a programmable device
US6630700B2 (en) * 2001-10-05 2003-10-07 Motorola, Inc. NMOS circuit in isolated wells that are connected by a bias stack having pluralirty of diode elements
US6781409B2 (en) * 2001-10-10 2004-08-24 Altera Corporation Apparatus and methods for silicon-on-insulator transistors in programmable logic devices
JP4090231B2 (ja) * 2001-11-01 2008-05-28 株式会社ルネサステクノロジ 半導体集積回路装置
US6614301B2 (en) * 2002-01-31 2003-09-02 Intel Corporation Differential amplifier offset adjustment
US20030151428A1 (en) * 2002-02-12 2003-08-14 Ouyang Paul H. 5 Volt tolerant input/output buffer
US6525559B1 (en) * 2002-04-22 2003-02-25 Pericom Semiconductor Corp. Fail-safe circuit with low input impedance using active-transistor differential-line terminators
JP4401621B2 (ja) * 2002-05-07 2010-01-20 株式会社日立製作所 半導体集積回路装置
US6870213B2 (en) * 2002-05-10 2005-03-22 International Business Machines Corporation EEPROM device with substrate hot-electron injector for low-power
US6731158B1 (en) * 2002-06-13 2004-05-04 University Of New Mexico Self regulating body bias generator
WO2004015867A1 (en) * 2002-08-08 2004-02-19 Koninklijke Philips Electronics N.V. Circuit and method for controlling the threshold voltage of transistors
US6809550B2 (en) * 2002-09-20 2004-10-26 Atmel Corporation High speed zero DC power programmable logic device (PLD) architecture
US6784722B2 (en) * 2002-10-09 2004-08-31 Intel Corporation Wide-range local bias generator for body bias grid
US7120804B2 (en) * 2002-12-23 2006-10-10 Intel Corporation Method and apparatus for reducing power consumption through dynamic control of supply voltage and body bias including maintaining a substantially constant operating frequency
US20060132218A1 (en) * 2004-12-20 2006-06-22 Tschanz James W Body biasing methods and circuits

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61160960A (ja) * 1985-01-08 1986-07-21 Matsushita Electric Ind Co Ltd 半導体集積回路
JPH04247653A (ja) * 1991-02-04 1992-09-03 Ricoh Co Ltd 半導体集積回路装置の遅延補正装置
JPH05108194A (ja) * 1991-10-17 1993-04-30 Hitachi Ltd 低消費電力型半導体集積回路
JP2000101416A (ja) * 1998-09-14 2000-04-07 Texas Instr Inc <Ti> Ｍｏｓ集積回路の特性を改良するためのボディ電圧のパルス動作
JP2001156261A (ja) * 1999-09-13 2001-06-08 Hitachi Ltd 半導体集積回路装置
JP2001345693A (ja) * 2000-05-30 2001-12-14 Hitachi Ltd 半導体集積回路装置
JP2003110028A (ja) * 2001-10-01 2003-04-11 Hitachi Ltd データ処理装置
JP2003168735A (ja) * 2001-11-30 2003-06-13 Hitachi Ltd 半導体集積回路装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007243178A (ja) * 2006-03-06 2007-09-20 Altera Corp 調整可能なトランジスタボディバイアス回路網
JP2013046068A (ja) * 2011-08-19 2013-03-04 Altera Corp フィールドプログラマブルゲートアレイの性能を向上させるための装置および関連方法
JPWO2021251206A1 (enExample) * 2020-06-09 2021-12-16
WO2021251206A1 (ja) * 2020-06-09 2021-12-16 三菱電機株式会社 学習装置、推論装置、およびプログラマブルロジックデバイスの開発用ツールチェーン
JP7466643B2 (ja) 2020-06-09 2024-04-12 三菱電機株式会社 学習装置、推論装置、学習方法、および推論方法

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