WO2007096913A1

WO2007096913A1 - Method for designing a complex integrated electronic circuit architecture

Info

Publication number: WO2007096913A1
Application number: PCT/IT2006/000104
Authority: WO
Inventors: Carlo Dallavalle; Salvatore Conigliaro
Original assignee: Stmicroelectronics S.R.L.
Priority date: 2006-02-24
Filing date: 2006-02-24
Publication date: 2007-08-30

Abstract

The present invention relates to a method for designing a complex circuit architecture (1) including a plurality of circuit portions interconnected one to the other in said architecture, each circuit portions including a VLSI number of on-board transistors of both NMOS and PMOS type and wherein a circuit architecture core (2) is associated to at least a couple of body bias generators (3), one for said NMOS and one for said PMOS transistors; characterized by the following steps: - providing said circuit architecture core by a library of basic transistor cells having N and P MOS substrates separated from their corresponding source terminals; - monitoring the active current (Ion) in said transistors; - comparing the monitored current with a predetermined current value corresponding to standard or typical working conditions of said transistors according to the result of the comparison phase providing a reverse bias for those cells of the circuit architecture core to be compensated because of a possible excess of current leakage.

Description

Method for designing a complex integrated electronic circuit architecture.

DESCRIPTION Field of the Invention

The present invention relates to a method for designing a complex integrated electronic circuit architecture including a plurality of circuit portions integrated into a single chip structure.

More specifically, the invention relates to a method for designing a digital System on Chip (System on Chip) architecture and the following description will be based on this specific technical field with the only purpose of reducing the complexity of its explanation.

The invention further relates to an integrated electronic circuit architecture comprising a plurality of circuit portions each including a high number of on-board transistors; said transistors including both types of NMOS and PMOS transistors. Background Art

As is well known in this specific technical filed, one of the major problems to be faced in handling the design of a System on Chip is the high number of on-board transistors.

The current technology allows manufacturing very complex integrated electronic circuits (ICs) including hundreds millions of transistors. These ICs are better known as System on Chip and this is a definition aimed to indicate their huge level of complexity.

An IC of this kind is disclosed for instance in the European patent Application No 1 430 405. The current technology in the manufacturing of integrated circuits pushes toward a continuous decrease in the transistor size, but this fact causes leakage currents to become relatively larger.

The presence of leakage currents results in a significant amount of power consumption even if a large part of the device is totally inactive. In other words, the chip warms up even if it is in the turned off state. In the last years designers have seen a dramatic increase in the static power consumption as transistors shrink in size. This problem is even more remarkable since today's ICs approach tens of millions of gates.

So, power consumption due to leakage currents has become a critical issue especially for nanometer technology.

For example, in the design of very high-speed circuits working at fixed frequencies, approaching to 1 Ghz and even more, the timing requirements of the circuit is certainly the main goal, but the related amount of leakage currents is not tolerated anymore. Several techniques have been used to address the leakage problem such as those using only high performance circuits including SVT (Small Voltage Threshold) in the critical path and using slower circuits including HVT (High Voltage Threshold), thus having a minor leakage, elsewhere on the chip. Circuit libraries are available in several variations of Voltage Thresholds that can be mixed and matched throughout the chip.

Very complex chip design methodologies are used to determine where a HVT circuit should be used in place of a standard SVT circuit to increase performance. To this regard, here below is reported a list of known methodologies currently applied to address the leakage problem.

In particular, the following patents disclose the minimization of dynamic power, either in combination with delay minimization or not:

- US patent N° 5,880,967 to Jyu having the following title "Minimization of circuit delay and power through transistor sizing";

- US patent N° US 6,209, 122 to Henry Horng-Fei Jyu et al. and concerning the minimization of circuit delay and power through transistor sizing;

- US patent N° 6,711,719 concerning a method and apparatus for reducing power consumption in VLSI circuit designs; US patent N° 6,711,720 concerning a method of optimizing high performance CMOS integrated circuit designs for power consumption and speed through genetic optimization;

- US patent N° 6,687,888 concerning a method of optimizing high performance CMOS integrated circuit designs for power consumption and speed;

- US patent N° 6,327,552 to Baez Franklin et al. concerning a method and system for determining optimal delay allocation to data path blocks based on area-delay and power-delay curves. In particular this patent discloses a method, system and computer program product for automatically determining optimal design parameters of- a subsystem to meet design constraints. The subsystem comprises a plurality of circuits. The optimal design parameters are determined by performing a parameter-delay curve optimization of the subsystem design parameters. Coming again to the problem of leakage currents, it worthwhile to note that a Sub-threshold Leakage Current Ioff, that is a current flowing through a MOS transistor in its inactive state, might weight few picoAmps/u for a single device at room Temperature, but the whole leakage current of the chip is easily brought up to hundreds of mAmps due to the combination of the number of devices with the silicon junction temperature.

As a consequence, in many System on Chip the static current is not negligible already at 130nm lithography. Such a static current is comparable if not larger than the dynamic current. Moreover since the sub-threshold current Ioff is dependent on temperature in an exponential way, a System on Chip operating at very high clock rates in a non-cooled environment can experience rapid growth of junction temperature and if such a growth is not limited by very low thermal resistances packages, that are highly expensive, the System on Chip may burn up.

This situation is known in literature as "thermal runaway" and happens when there is a junction temperature instability created by silicon thermal heating connected to the package thermal resistance and combined with the chip total electrical power. This instability results in a positive thermal feedback, due to the static power of the chip which grows as silicon junction temperature grows. When this growth is not compensated by the package ability to dissipate power the positive loop is established and it ends only (without external intervention) with the chip destruction. Therefore the leakage current in all portable electronic equipments realized at 130nm technology represents a severe threats for the operation reliability of the integrated circuit and will be even more relevant for the next coming technologies at 90nm and 65nm.

Hence sub-threshold leakage current is at the moment the common enemy for all System on Chip Designers.

The aim of the present invention is that of providing a new method for designing a complex integrated electronic circuit architecture including a plurality of circuit portions integrated into a single chip structure but dramatically reducing the problems connected with the sub-threshold leakage current.

A further aim of the present invention is that of obtaining the above results during the electrically wafer sorting phase of the circuit architecture.

Another aim of the invention is that of reducing the global quiescent current of the integrated chip during inactivity conditions.

Summary of the Invention

The basic idea on which the invention is based is that of monitoring the current Ion of the MOS transistors in active (ON) state of the architecture core to determine the possible presumed value of the leakage current Ioff when the circuit will be inactive and to provide a reverse body biasing to those transistors requiring a compensation.

According to a first embodiment of the invention a method is provided for designing a complex circuit architecture including a plurality of circuit portions interconnected one to the other in said architecture, each circuit portions including a VLSI number of on-board transistors of both NMOS and PMOS type and wherein a circuit architecture core is associated to at least a couple of body bias generators, one for said NMOS and one for said PMOS transistors; characterized by the following steps: - providing said circuit architecture core by a library of basic transistor cells having N and P MOS substrates separated from their corresponding source terminals;

- monitoring the active current (Ion) in said transistors; - comparing the monitored current with a predetermined current value corresponding to standard or typical working conditions of said transistors;

- according to the result of the comparison phase providing a reverse bias for those cells of the circuit architecture core to be compensated because of a possible excess of current leakage.

Another embodiment of the invention relates to an integrated electronic circuit comprising a complex digital architecture including:

- a plurality of circuit portions interconnected in said architecture and , each including a VLSI of on-board transistors; said transistors including both types of NMOS and PMOS transistors;

- an architecture core including at least some of said circuit portions; said circuit portions including at least a couple of body bias generators, one for said NMOS and one for said PMOS transistors;

- characterized in that: - said circuit portions of the architecture core are formed by transistors taken from a library of basic transistor cells having N and P MOS substrates separated from their corresponding source terminals; and that

- said architecture comprising: - a monitoring circuit portion including sensors of the active current

(Ion) of said transistors;

- contact pads for providing the monitored or measured value of said active current (Ion) of said transistors to an external testing equipment (5) comparing the monitored current with a predetermined current value corresponding to standard or typical working conditions of said transistors; said body bias generators providing a reverse bias for those cells of the architecture core to be compensated according to the result of the comparison to reduce a possible excess of current leakage. The features and advantages of the method and the integrated circuit architecture according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.

Brief description of the drawings - Figure 1 schematically shows a current vs. current diagram reporting in an elliptic domain the characteristic points corresponding to about 99,7% of a population in a Gaussian distribution of basic transistor cells obtained by a given technology; - Figure 2 schematically shows a current vs. current diagram reporting the elliptic domain of Figure 1 shifted by a predetermined amount of the σ parameter of the Gaussian distribution;

- Figure 3 schematically shows an automatic testing equipment used for performing an Electric Wafer Sorting (EWS) testing procedure on a semiconductor wafer incorporating multiple integrated circuits realized according to the present invention;

Figure 4 is a schematic view of a detail of a circuit portion incorporated into an integrated circuit according to the present invention;

Figure 5 is a schematic view of a detail of another circuit portion incorporated into an integrated circuit according to the present invention;

- Figure 6 schematically shows another current vs. current diagram reporting in the elliptic domain of Figure 2 some preferred points corresponding to transistor cells selected according to the different working condition of the integrated device under test. Detailed Description

Making reference to the embodiment of Figure 3 with 1 is globally and schematically shown an integrated electronic circuit comprising a complex digital architecture. The circuit 1 may be considered a so-called System on Chip that is to say a complex circuit architecture including a plurality of circuit portions interconnected one with the other on the same chip or on a same semiconductor substrate.

Each circuit portion includes a very high number of on-board transistors. We might consider that each circuit portion is equivalent to chip of reduced complexity for instance to a VLSI circuit portion including some millions of transistors.

Each circuit portion includes MOS transistors of both types, i.e. NMOS and PMOS transistors. The circuit 1 comprises an architecture core 2 including at least some of said circuit portions.

The circuit 1 further comprises at least a couple of body bias generators, generally indicated with 3.

The circuit 1 includes at least one body bias generator for said NMOS transistors and at least one body bias generator for said PMOS transistors. A different number of body bias generators may be adopted according to the need of the designer or the final user of the circuit 1.

According to the invention, the circuit portions of the architecture core 2 are formed by transistors taken from a library of basic transistor cells having N and P MOS substrates separated from their corresponding source terminals.

Those transistors of said library may be selected for instance from the transistors structured according to the disclosure of the US Patent No. 5,763,907 granted on June 9,1998 and assigned to the same Applicant. Those dedicated libraries are better known by those skilled in the art as Split Ground (GND) or Supply Rails from Substrate. Advantageously the circuit 1 comprises a monitoring circuit portion 4 including sensors of the active current Ion of said transistors selected from said libraries.

The circuit 1 must be seen or considered as being part of a wafer structure (not shown being of a conventional type) including dozens or hundreds of such integrated circuits.

While the circuit 1 is still incorporated into the wafer an automatic testing equipment or machine, indicated with the number 5 in Figure 3, is temporarily connected to the circuit 1 through a wafer probe 6 to submit the circuit 1 to an Electrical Wafer Sorting (EWS) testing procedure.

The probe 6 and the testing machine 5 are linked by connections 7 and 8.

The machine 5 contacts the architecture core 2 of each device under test trough the connection 8 and, at the same time, the monitor structure 4 and the body bias generators are linked to the machine 5 through the connection 7.

An example of a sensor 10 included into said monitoring circuit structure 4 is shown in Figure 4 for the NMOS transistors.

A MOS transistor Ml has a drain terminal coupled to the voltage supply potential reference Vdd and the source terminal coupled to a second potential reference, for instance a ground reference.

The gate terminal GM 1 of such a NMOS transistor M 1 is connected to the drain terminal, while the body terminal is connected to a body bias generator 11 providing a possible biasing voltage Vbs for the P-WeIl region of the NMOS transistor under sensing. A similar sensor structure 20 is provided for the PMOS transistors and it is shown in Figure 5. A PMOS transistor PMl is presented with its source terminal coupled to the voltage supply potential reference Vdd and the drain terminal coupled to a second potential reference, for instance a ground reference. The gate terminal GPl of such a PMOS transistor Pl is connected to the drain terminal, while the body terminal is connected to a body bias generator 21 providing a possible biasing voltage Vbs for the N-WeIl region of the PMOS transistor under sensing. Each sensor 10 or 20 may be used to detect the active current Ion flowing trough a MOS transistor of the architecture core 2.

Advantageously, the testing machine 5 includes comparator means for comparing the monitored or measured active current Ion of the selected transistors in the architecture core 2 with a predetermined current value corresponding to standard or typical working conditions of said transistors in absence of any body bias..

Moreover, the monitoring and comparing phases are performed preferably at room temperature even if this is not mandatory. According to the result of such a comparison, the body bias generators 3 may be driven to provide a reverse bias for those cells of the architecture core 2 to be compensated for reducing a possible excess of leakage current.

Therefore, the invention suggests to combine in a single integrated circuit architecture the following features:

A) circuit portions of the architecture core 2 taken from a dedicated library of basic transistor cells having N and P MOS substrates separated from their corresponding source terminals;

B) a monitoring circuit portion 4 including sensors, 10 or 20, of the active current (Ion) of said transistor cells;

C) body bias generators 3 providing a reverse bias for those cells of the architecture core 2 to be compensated according to the result of a comparison between the monitored current and a predetermined current value corresponding to standard or typical working conditions of said transistors in absence of any body bias, thus reducing a possible excess of current leakage.

One of the advantages of the present invention is due on the fact that the adjustment of the possible excess of leakage current is provided during the testing phase of the integrated circuit architecture when it is still at wafer level, that is to say during the Electrical Wafer Sorting (EWS) testing procedure.

This allows a routinely controlled reduction of the Ion current on every chip under EWS, thus resulting in a global static current reduction and a in a smaller chip die size. This last feature is mainly obtained through the last step of the inventive method.

The invention provided further advantages that are: a less expensive package structure; and, a lower reliability concern.

The use of on board reverse body bias generators, at least one for the P- WeIl substrate of NMOS transistors and at least another one for the N- WeIl substrate of PMOS transistors allows increasing the MOS thresholds.

This feature taken in combination with the availability of the dedicated hardware described at points (A) (B) and (C) will give to designers an important flexibility according to the System on Chip speed-timing constraints.

A further optional feature of the inventive method is provided through the availability of a shadow offset process phase that will be described in detail hereinafter according to the technology currently available for the design of Systems on Chip.

In this respect and for a better understanding of the method steps of the present invention it should be first considered the way how the digital designers approach the design work of a new circuit architecture to guarantee that the System on Chip can operate at the fixed Clock Frequency.

This approach is mainly based on the slow corner values of the active current Ion that is schematically shown in Figure 1.

The digital synthesis of the logic networks is generally done in presence of the slowest process transistors and the worst environmental conditions. This situation is equivalent to a minimum supply voltage combined with the maximum environment temperature.

The consequence of this working habitat is the following: the primitives logic functions extracted from the cell library are formed in most of the cases with MOS transistors having non minimum channel width W. It is well known that the larger is the width W of the MOS inside the primitive, the smaller is their associated propagation delay. Moreover, the currents Ion and Ioff for every MOS Transistor are directly proportional to the transistor channel width W.

Now, when a chip is synthesized to guarantee it works in presence of worst case process and environmental conditions it happens that the sub- threshold conduction currents Ioff, that are the leakage currents, are at their highest levels.

In other words, in the case of a fast device having features defined in the slow corner, that corresponds to the maximum supply voltage and the maximum environment temperature, the sub-threshold conduction currents Ioff are between ten and twenty times the ones in worst case corners conditions.

The consequence of this beaviour of the MOS transistor cells forces an exponential raising of the global quiescent current of the chip and the combination of main process parameters variations (such as: gate length CD, MOS transistor threshold voltages) leads to large Ion/Ioff variations and globally to high associated global quiescent current.

To solve this problem let's first consider what every designer who has to start a new System on Chip design based on the current integration technology, for instance a sub-micrometric technology based on a lithography lower limit of 90nm, should be aware.

We have already seen that a control of the System on Chip static power may be obtained through the combination of features (A), (B) and (C).

A further improvement of the circuit architecture performances may be obtained through a first optional method step. First optional step

As is well known, the statistical distribution of process parameters appears to be a Gaussian distribution. While statisticians and mathematicians uniformly use the term "normal distribution" for this distribution, physicists sometimes call it a Gaussian distribution and, because of its curved flaring shape, social scientists refer to it as the "bell curve."

In any case, the transistors obtained through a manufacturing process performed according to the current sub-micrometric technology present active currents (i.e IonP, IonN) characteristics that are distributed around a typical Gaussian curve having a central value X' of 600 microAmper/ micron for the NMOS and 270 microAmper/ micron for the PMOS and a standard deviation identified by a σ value of 20 microAmper/ micron for the NMOS and 12 microAmper/ micron for the PMOS, as shown in Figure 1.

Obviously those values are not mandatory and may vary according to the sub-micrometric technology process.

When the process is stable and well controlled the standard deviation σ of the Gaussian distribution (and its multiples) are used to indicate the percentage of the measurements which falls aside the center value of a Gaussian distribution. For instance in a range of +/-1 σ from the Gaussian center X' is contained the 68.26% of the population, while in a range of +/-3 σ there is the 99.7% of the population. Of course, other σ ranges might be taken in consideration but the range of +/-3 σ is generally the best compromise in the selection of the largest part of the statistic population. The higher is the σ value the larger is the Gaussian distribution and lower the mass production control of the process parameter measured. Moreover, in this statistical distribution the opposite corners of the two process parameters (i.e IonP, IonN) represent the extreme points where the two parameters have both minimum or maximum value.

Looking at Figure 1 it might be appreciated that the so-called fast process corner, indicated with FPC, is the point located at +3 σ values of the two process parameters defining the FPC corner itself.

On the contrary, the slow process corner, indicated with SPC, is the point located at -3 σ value of the two process parameters defining the SPC corner itself.

A typical process center is indicated by X' and it's the point located at the coincidence of two process parameters average values of their respective Gaussian distributions.

The ellipse El shown in Figure 1 having a center in the X' point and opposite extremes in the points FCP and SCP presents a major axis DPP that measure the just distance between the process points according to the following formula:

Now, if we compare Figure 1 and Figure 2 we may appreciate that a second ellipse E2 is shown in Figure 2 having the center X" shifted or offset by an amount corresponding to the distance DPP/ 2.

This second ellipse E2 has the center X" in a point that substantially coincide with the FCP point of the ellipse El.

We will take in consideration hereinafter this second ellipse as a group of points corresponding to a shadow offset process technology that may be considered an optional process technology to be compared with an available standard technology. The MOS transistors obtained implementing a shadow offset process technology present an active current Ions that differs from the active current of the standard process by a Δ current improved by three σ (+3σ) or, as an alternative, by one half of the distance DPP.

Now, according to the method of the present invention, as a preliminary step the designer might adopt a shadow process for implementing the synthesis of the integration technology allowing the System on Chip to be based on a group of library cell formed by MOS devices having a Ion active current higher of about 1/2 DPP more with respect to the Ion current of the transistors obtained by the standard technology. In other words, the selection of a circuit architecture core using a library of basic transistor cells having N and P MOS substrates separated from their corresponding source terminals may be focused on cells having an improved active current Ion. More particularly, such an improved active current may be set to an increase of 1/2 DPP if compared to the active current of the corresponding standard transistors.

Referring again to the three σ distribution of the shadow process shown in Figure 2, the active currents Ions are represented as points of an ellipse E2 shifted of an amount of three σ. Obviously, this Ion currents shifted by- three σ produces an increase in the Ion currents.

Due to this three σ shift, a typical shadow process provides for an active current Ion that will be coincident with the FCP point of a standard or original process.

A similar coincidence will occur for the SCP and the center point X of a standard process of Figure 1 , so that:

Ion (Shadow) N_/p-iyp = Ion (Original) N_/PFast Ion (Shadow) N/P slow = Ion (Original) N_/PTyp

When using a shadow process for designing a complex circuit architecture such a System on Chip the transistors respecting the characteristics of the slow corner will be used to guarantee the operating frequency and the critical paths. Those transistors form primitive or basic circuits having a lower width W with respect to the width that they would have had through the original process (unless the frequency/ timing constraints are so mild they resulted already satisfied by minimum W libraries in the original process).

So, a circuit synthesis based on the offset process previously disclosed will lead to the use of cells having a smaller width W and this will results in a smaller die size of the circuit architecture thus achieving a further advantage in the global reduction of the chip size. What's more, the smaller size of chip will have positive impact on its dynamic power therefore reducing it's silicon junction temperature Tj for the same external conditions (environment temperature, supply voltage, package).

This has a great synergic impact on the static power because of a reduced junction temperature Tj and so that the leakage current will be even lower because of the further lower equilibrium between static power and junction temperature Tj. Whenever the Ion currents associated to the offset process will occur in the high side of the DPP offset process distribution, a further process step will be implemented and soon disclosed hereinafter.

From Figure 1 it is evident how the larger is the DPP (for a given integration technology) the higher is the global leakage current associated with the fast corner of the ellipse.

So, a possible overdesign of the chip, that correspond to a selection of transistor cells still proportional to the DPP, would produce a higher silicon junction temperature thus increasing the risk of thermal runaway. An overdesign generally indicates an excess of MOS Transistor dimension, i.e. an excess of channel width W, versus the minimum dimension theoretically needed to achieve the design objectives.

This is just avoided by the method steps according to the invention.

The benefits of limiting the silicon junction temperature has the further advantages of rendering inappropriate the need expensive heat sinks or packages or even wider supply metal layers; so, this provides less die and board areas and, in addition, lower device reliability concerns.

Regular process steps

As already seen, according to the method of the present invention the circuit architecture core 2 is formed by a library of basic transistor cells having N and P MOS substrates separated from their corresponding source terminals.

Those transistor cells may be selected according to the first optional step disclosed above. Then, a further procedure is adopted for applying a reverse body bias to those cells requiring a reduction of a possible excess of current leakage, at least a reduction enough to shift down the active current Ions to a maximum of 1/2 DPP.

So, even when the Ion currents falls in the region of fast offset process, the circuit leakage current is returned to the leakage current of the fast original process, but strongly reduced thanks to the Global width W reduction obtained during the synthesis phase of the previous process step. Now, having adopted an architecture core 2 structured by a hardware based on a dedicated library of transistor cells properly designed to have the N and P MOS substrates electrically separated from their respective sources terminals, allows applying to their substrate proper reverse biasing.

So every cell of the architecture core 2 might receive from the body bias generators 3 a proper biasing adapting the leakage current.

When those hardware structures are used in a complex circuit architecture and properly connected together, they allow to compensate the excess of leakage current.

We have also seen that this advantage can be exploited during a very specific point of the IC fabrication process that is the Electrical Wafer Sorting.

At the EWS step every dice or device under test is probed and tested by the automatic testing equipment 5.

At this point the next process step is applied to only those devices under test which have passed the entire test program, that are the perfectly working devices.

The monitoring phase allowed by the presence of the monitoring circuit portion 4, that is embedded into the circuit 1 just with the purpose to extract the Ion (IonN and IonP) MOS currents through the testing equipment 5, allows comparing the measurement with the typical values of the standard transistor cells of the library and deciding whether or not applying the reverse biasing to the transistor cells of the architecture core 2.

The use of the active current Ion to control the leakage current Ioff is particularly effective since it is possible to provide a very simple and accurate measure of the Ion while the measure of the Ioff would be very complex and inaccurate. In addition the transistor cells libraries are characterized by the worst typical and best typical situations, for a dynamic simulations, and their active currents Ion are spread out within the process distributions given by +/- 3 σ from the center point of the Gaussian curve used as a model of the cell libraries.

In other words, the automatic testing equipment 5 is in charge to perform the measurements allowed by the presence in the circuit 1 of the monitoring structure 4. Those measurements are performed when the body bias generators are in power down condition, that is to say: when the N-WeIl substrares of all the PMOS transistors are at the Vdd potential and the P-WeIl substrates of all the NMOS are at a virtual ground GND potential. Let's now evaluate in greater detail these possible measurements that are performed at environment temperature and feeding the circuit with a typical supply voltage:

Ion_N~Monitor Ion_p-Monitor

As shown in Figures 4 and 5, the sensor portion 10, 20 of the monitoring structure 4 will provide a measured value of the current Ion flowing across the NMOS or the PMOS transistor of the architecture core 2 during their active (ON) state.

The automatic testing equipment will then compare these measured values with typical values well known inside the integration technology domain.

For instance, in the current technology at 130 nm typical values of Ion_N and Ion_p are within the following range from 540 to 660 microAmper/ micron for the NMOS and from 235 to 305 microAmper/ micron for the PMOS.

Let's identify these typicals values with:

IonN-Typ IonP-Typ

The result of the comparison between Ion-Monitor and Ion-Typ will provides an information for deciding whether or not applying a reverse body bias to the architecture core 2 , with the only exception of the circuit portions of the input/ output (I/O) that are not structured with transistor cells taken from the libraries primitives.

More in detail: if IonN-Monitor > IonN-Typ then > a negative voltage potential is applied to the P-WeIl body terminals of the NMOS transistors of the architecture core 2.

For instance a possible value of body bias could be:

VBS = -0.4V # (Negative voltage referred to GND). Even if other voltage values could be applied according to the design needs. if I IonP-Monitor | > | IonP-Typ | then > a positive voltage potential is applied to the N-WeIl body terminals of the PMOS transistors of the architecture core 2.

For instance a possible value of this positive body bias could be:

VBS = VDD+0.4V # (Positive voltage referred to GND). Again, other voltage values could be applied according to the design needs.

It's worthwhile to note that the 0.4 volts value is only indicative of the level of magnitude the body bias generators 3 could provide. A more precise level will be set according the MOS devices architecture inside the integration technology, taking into account some constraints due to gate induced drain leakage and the reliability which limit the absolute value of |VBS | .

Whether both the body bias generators 3 are involved for biasing their respective substrate or not, depends from where the active currents Ion of the device under test are located inside their natural distribution. In this respect let's consider the example of Figure 6 wherein different working points are reported according to the different working condition of the device under test that is identified by the reference DUT.

Whenever the active currents Ions of the DUT lays in the right-upper part of the elliptical curve, both the body bias generators 3 are activated and maintained on to provide the +/-0.4V voltage value to the respective N or P substrate. The body bias voltage is selected properly in order that, due to its effect, the active current Ion sensed by the monitoring structure 4 is reduced.

However, this reduction is advantageously limited to no more than 1/2 of DPP, that is to say: the distance between two opposite process corners reported in Figures 1, 2 or 6.

In this way the global leakage current of the whole circuit architecture 1 is reduced (between four and ten times when both the generators 3 are active) while the System on Chip performance in term of speed/ delays are guaranteed by being always far away from the slow corner process points. We might say that according to the method and circuit of the present invention a sort of virtuous triangle is put in place during the System on Chip digital synthesis and this is obtained through the combination of first optional method step previously seen and the regular process steps considered after. Briefly the major benefits of the invention are the following:

1) Chip size reduction thanks to global reduction of the channel width W of the involved transistors and overall overdesign reduction (1/2 of DPP);

2) Consequent dynamic power reduction because of a lower Tj;

3) Consequent lower Leakage (lower Tj) and further lower leakage because of lower global reduction of the channel width W;

4) Improved noise margins and lower voltage drops;

5) Higher use of low leakage cells versus high (Ion) current (or high leakage) cells in the Synthesis phase.

Again, just to summarize, one of the main advantages of the invention is that of limiting the sub-threshold leakage current associated to Systems on Chip combining the presence of reverse substrate bias together with a proper selection of transistor cells in the architecture core. Moreover, the invention teaches how to obtain such a leakage reduction during the testing phase of the chip at wafer level.

Claims

1. Method for designing a complex circuit architecture (1) including a plurality of circuit portions interconnected one to the other in said architecture, each circuit portions including a VLSI number of on-board transistors of both NMOS and PMOS type and wherein a circuit architecture core (2) is associated to at least a couple of body bias generators (3), one for said NMOS and one for said PMOS transistors; characterized by the following steps: providing said circuit architecture core by a library of basic transistor cells having N and P MOS substrates separated from their corresponding source terminals;

- monitoring the active current (Ion) in said transistors;

- comparing the monitored current with a predetermined current value corresponding to standard or typical working conditions of said transistors according to the result of the comparison phase providing a reverse bias for those cells of the circuit architecture core to be compensated because of a possible excess of current leakage.

2. Method according to claim 1 wherein the phase of monitoring the active current (Ion) in said transistors is performed when said body bias generators (3) are in a power down state.

3. Method according to claim 1 wherein said comparing phases is performed by an automatic testing equipment (5) at wafer level.

4. Method according to claim 1 wherein said monitoring and comparing phases are performed at room temperature.

5. Method according to claim 1 wherein said reverse bias is provided through a bias voltage forcing a reduction of said active current (Ion) .

6. Method according to claim 1 wherein said basic transistor cells are selected implementing an offset process and choosing transistor cells having active currents (Ions) that differs from the active current of the standard process by a Δ value improved with respect to a value of active current reported in a statistical Gaussian distribution for said basic transistor cells and for a given technology.

7. Method according to claim 6 wherein said current Δ value is improved by at least three σ of said statistical Gaussian distribution.

8. Method according to claim 6 wherein said basic transistor cells are formed by MOS devices having a active current (Ion) higher of about half of the distance between two extreme process points of said offset process if compared with the active current of the transistors obtained by the standard process in the same technology.

9. Method according to claim 1 wherein said predetermined current value corresponding to standard or typical working conditions of said transistors is referred to a situation in absence of any body bias.

10. Method according to claim 6 wherein said basic transistor cells are taken from primitive or basic circuits libraries of said offset process and having a lower width W with respect to the width of the transistors obtained by a standard process.

11. Integrated electronic circuit comprising a complex digital architecture including:

- a plurality of circuit portions interconnected in said architecture and each including a VLSI of on-board transistors; said transistors including both types of NMOS and PMOS transistors;

- an architecture core including at least some of said circuit portions;

- said circuit portions including at least a couple of body bias generators (3), one for said NMOS and one for said PMOS transistors;

- characterized in that:

- said circuit portions of the architecture core are formed by transistors taken from a library of basic transistor cells having N and P MOS substrates separated from their corresponding source terminals; and that

- said architecture comprises: - a monitoring circuit portion (10, 20) including sensors (11, 21) of the active current (Ion) of said transistors;

- contact pads for providing the monitored or measured value of said active current (Ion) of said transistors to an external testing equipment (5) comparing the monitored current with a predetermined current value corresponding to standard or typical working conditions of said transistors; said body bias generators providing a reverse bias for those cells of the architecture core to be compensated according to the result of the comparison to reduce a possible excess of current leakage.

12. Integrated electronic circuit according to claim 11 wherein said predetermined current value corresponding to standard or typical working conditions of said transistors is referred to a situation in absence of any body bias.

13. Integrated electronic circuit according to claim 11 wherein said monitoring circuit portion (10, 20) is structured with at least one sensor (11) NMOS transistor for an associated body bias generator for the NMOS transistors and at least one sensor (21) PMOS transistor for an associated body bias generator for the PMOS transistors.

14. Integrated electronic circuit according to claim 11 wherein the reverse biasing of said body bias generators (3) is activated when the integrated circuit is associated to an automatic testing equipment (5).