JP2007527115A - コンプリメンタリ横型窒化物トランジスタ - Google Patents

コンプリメンタリ横型窒化物トランジスタ Download PDF

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Publication number
JP2007527115A
JP2007527115A JP2006553314A JP2006553314A JP2007527115A JP 2007527115 A JP2007527115 A JP 2007527115A JP 2006553314 A JP2006553314 A JP 2006553314A JP 2006553314 A JP2006553314 A JP 2006553314A JP 2007527115 A JP2007527115 A JP 2007527115A
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Japan
Prior art keywords
semiconductor
pillar
semiconductor pillar
semiconductor device
support surface
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Application number
JP2006553314A
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English (en)
Japanese (ja)
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JP2007527115A5 (enExample
Inventor
ビーチ ロバート
ブリジャー ポール
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Americas Corp
Original Assignee
International Rectifier Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Rectifier Corp USA filed Critical International Rectifier Corp USA
Publication of JP2007527115A publication Critical patent/JP2007527115A/ja
Publication of JP2007527115A5 publication Critical patent/JP2007527115A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements
    • H10D89/713—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Thin Film Transistor (AREA)
  • Bipolar Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2006553314A 2004-02-12 2005-02-14 コンプリメンタリ横型窒化物トランジスタ Pending JP2007527115A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US54491004P 2004-02-12 2004-02-12
US11/056,833 US7205657B2 (en) 2004-02-12 2005-02-11 Complimentary lateral nitride transistors
PCT/US2005/004609 WO2005079365A2 (en) 2004-02-12 2005-02-14 Complimentary lateral nitride transistors

Publications (2)

Publication Number Publication Date
JP2007527115A true JP2007527115A (ja) 2007-09-20
JP2007527115A5 JP2007527115A5 (enExample) 2011-05-26

Family

ID=34840655

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006553314A Pending JP2007527115A (ja) 2004-02-12 2005-02-14 コンプリメンタリ横型窒化物トランジスタ

Country Status (5)

Country Link
US (2) US7205657B2 (enExample)
JP (1) JP2007527115A (enExample)
KR (1) KR100772730B1 (enExample)
DE (1) DE112005000353T5 (enExample)
WO (1) WO2005079365A2 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5008317B2 (ja) * 2006-02-27 2012-08-22 株式会社豊田中央研究所 ユニポーラダイオード

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02306668A (ja) * 1989-05-22 1990-12-20 Nippon Telegr & Teleph Corp <Ntt> 量子細線を有する半導体装置及びその製造方法
JPH06140346A (ja) * 1992-04-02 1994-05-20 Thomson Csf ヘテロエピタキシアルの薄い層と電子デバイスの製造法
JPH07183541A (ja) * 1993-12-22 1995-07-21 Oki Electric Ind Co Ltd 半導体微細構造の形成方法
JP2001358075A (ja) * 2000-06-16 2001-12-26 Univ Meijo 半導体素子の製造方法及び半導体素子
WO2002067333A1 (fr) * 2001-02-21 2002-08-29 Mitsubishi Denki Kabushiki Kaisha Dispositif semi-conducteur et procede de fabrication correspondant
JP2003124573A (ja) * 2001-10-12 2003-04-25 Sumitomo Electric Ind Ltd 半導体発光素子の製造方法、半導体素子の製造方法、素子の製造方法、窒化物系ｉｉｉ−ｖ族化合物半導体層の成長方法、半導体層の成長方法および層の成長方法
JP2003152177A (ja) * 2001-11-19 2003-05-23 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2350926A (en) * 1999-05-27 2000-12-13 Seiko Epson Corp Monolithic,semiconductor light emitting and receiving device
US6617226B1 (en) * 1999-06-30 2003-09-09 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US6498372B2 (en) * 2001-02-16 2002-12-24 International Business Machines Corporation Conductive coupling of electrical structures to a semiconductor device located under a buried oxide layer
WO2002080242A1 (fr) * 2001-03-29 2002-10-10 Toyoda Gosei Co., Ltd. Procede de fabrication d'un semi-conducteur a base d'un compose nitrure du groupe iii et dispositif semi-conducteur a base d'un compose nitrure du groupe iii
US6686604B2 (en) * 2001-09-21 2004-02-03 Agere Systems Inc. Multiple operating voltage vertical replacement-gate (VRG) transistor
US6743291B2 (en) * 2002-07-09 2004-06-01 Chartered Semiconductor Manufacturing Ltd. Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth
US6822301B2 (en) * 2002-07-31 2004-11-23 Infineon Technologies Ag Maskless middle-of-line liner deposition
US6800904B2 (en) * 2002-10-17 2004-10-05 Fuji Electric Co., Ltd. Semiconductor integrated circuit device and method of manufacturing the same
KR100632036B1 (ko) * 2002-12-30 2006-10-04 동부일렉트로닉스 주식회사 반도체 메모리 소자의 제조 방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02306668A (ja) * 1989-05-22 1990-12-20 Nippon Telegr & Teleph Corp <Ntt> 量子細線を有する半導体装置及びその製造方法
JPH06140346A (ja) * 1992-04-02 1994-05-20 Thomson Csf ヘテロエピタキシアルの薄い層と電子デバイスの製造法
JPH07183541A (ja) * 1993-12-22 1995-07-21 Oki Electric Ind Co Ltd 半導体微細構造の形成方法
JP2001358075A (ja) * 2000-06-16 2001-12-26 Univ Meijo 半導体素子の製造方法及び半導体素子
WO2002067333A1 (fr) * 2001-02-21 2002-08-29 Mitsubishi Denki Kabushiki Kaisha Dispositif semi-conducteur et procede de fabrication correspondant
JP2003124573A (ja) * 2001-10-12 2003-04-25 Sumitomo Electric Ind Ltd 半導体発光素子の製造方法、半導体素子の製造方法、素子の製造方法、窒化物系ｉｉｉ−ｖ族化合物半導体層の成長方法、半導体層の成長方法および層の成長方法
JP2003152177A (ja) * 2001-11-19 2003-05-23 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

Also Published As

Publication number Publication date
US20070077689A1 (en) 2007-04-05
WO2005079365A2 (en) 2005-09-01
US7205657B2 (en) 2007-04-17
US20050180231A1 (en) 2005-08-18
US7510957B2 (en) 2009-03-31
WO2005079365A3 (en) 2007-04-12
KR100772730B1 (ko) 2007-11-02
DE112005000353T5 (de) 2007-02-01
KR20060115763A (ko) 2006-11-09

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