Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
  • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
  • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
  • H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements
  • H10D89/713—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices

Definitions

• the present invention relates to semiconductor devices and more particularly to power semiconductor devices and methods for fabricating power semiconductor devices.
• a typical semiconductor fabrication process includes steps for deposition and or growth of a thin semiconductor film over a substrate and then forming features within the thin semiconductor film by a series of diffusion and deposition steps. For example, it is common to epitaxially grow a thin layer of silicon over a silicon substrate, which is usually cut out of an ingot, and then forming PN junctions within the thin layer to form the basic parts of a semiconductor device. Depending on the device other parts of the device can then be formed by a series of deposition and etching steps. For example, in a typical field effect transistor channel regions may be formed by implantation and diffusion dopants and the gate structures are formed adjacent the channel region by growing a gate oxide and deposition and patterning a conductive material to form the gate electrodes.
• the conventional methods often include masking steps to define the areas that are to be implanted. The masks are formed lithographically and often include dimensional errors, even in well controlled processes.
• PN junction by diffusion involves implanting dopants of one conductivity in a semiconductor body of another conductivity and driving the same at a high temperature to activate and diffuse the dopants to a desired depth and lateral extent. The diffusion process usually results in a tub-shaped region of one conductivity, in a region of another conductivity.
• the corners of such tub-shaped regions develop high electric fields and breakdown at voltages much lower than the theoretical " breakdown limits for a PN junction having a radius of curvature of infinity, (i.e. an ideal PN junction).
• concentration of dopants or the thicknesses of the semiconductor regions must be increased to compensate for the lowering of the breakdown voltage.
• diffusion results in a concentration gradient, which may become a factor in the design of the device.
• a concentration gradient in the channel region may have an adverse effect on the threshiold voltage and thus the turn on characteristics of a field effect transistor.
• a semiconductor according to the present invention includes a common support having a support surface, a lateral semiconductor stack extending laterally along the support surface, the stack including a first semiconductor column formed over the support surface, and a second semiconductor column formed over the support surface lateral to the first semiconductor region, a first electrical contact electrically connected to the first semiconductor column, and a second electrical contact electrically connected to the second semiconductor column.
• a semiconductor device according to the present invention can be a field effect transistor which includes a third semiconductor column of a conductivity opposite to the first semiconductor column and the second semiconductor column formed over the support surface and disposed laterally adjacent to the first semiconductor column and the second semiconductor column, and further comprising a gate structure adjacent the third semiconductor column.
• a semiconductor device can also be a pin diode in winch the first semiconductor column is of a first conductivity and the second semiconductor column is of a second conductivity.
• the first semiconductor column is comprised of a region of one resistivity and another region of lower resistivity that is laterally adjacent the region of one resistivity both regions being disposed over the support surface.
• a drain region of lower resistivity may be laterally adjacent to a drift region of higher resistivity, or in a pin diode according to the present invention a drift region of higher resistivity may be laterally adjacent a cathode or anode region of lower resistivity.
• the semiconductor columns are formed from conductive GaN or any other IE-nitride semiconductor material, h one variation of the preferred embodiment, a semiconductor layer having a different bad gap is formed over at least one of the semiconductor columns. In another variation, the semiconductor layer is formed over the first and the second semiconductor columns.
• the preferred material for the semiconductor layer is AlGaN, which, when used in combination with GaN as the material for forming the semiconductor columns, may improve mobility.
• a semiconductor device may include a common support having a support surface, a first semiconductor component and a second semiconductor component each including:
• a lateral semiconductor stack formed over the support surface, the stack including a first semiconductor column formed over the support surface, and a second semiconductor column formed over the support surface lateral to the first semiconductor region, whereby the stack extends laterally along the support surface, a first electrical contact electrically connected to the first semiconductor column, and [0014] a second electrical contact electrically connected to the second semiconductor column; and [0015] an insulating semiconductor column interposed between and laterally adjacent the first semiconductor component and the second semiconductor component.
• the lateral semiconductor stack may further include a third semiconductor column of a conductivity opposite to the first semiconductor column and the second semiconductor column formed over the support surface and disposed laterally adjacent to the first semiconductor column and the second semiconductor column, and a gate structure adjacent the third semiconductor column.
• a semiconductor device is fabricated by a method which includes forming a growth preventative layer over a major surface of a substrate, such as SiC, Si, or Sapphire, and then removing portions of the growth preventative layer to expose at least one selected portion of the major surface of the substrate, while leaving another portion of the major surface covered with the growth preventative layer. Thereafter, in an epitaxial growth step or the like, a first semiconductor column is formed on the exposed portion of the substrate.
• a substrate such as SiC, Si, or Sapphire
• the first semiconductor column is only formed vertically only over the exposed portion.
• the first semiconductor so formed includes an exposed sidewalk
• another semiconductor column is formed on the exposed sidewall of the first semiconductor device, resulting in two laterally adjacent semiconductor columns. This process can be repeated as many times as desired to obtain a lateral stack of semiconductor columns of one or variable conductivities with different resistivities.
• the columns so formed can then serve as conductive regions for semiconductor devices such as diodes or field effect transistors.
• a base region in a device according to the present invention may have a more uniform concentration
• a PN junction in a device according to the present invention may have less curvature (i.e. a larger radius of curvature) and thus able to have a reverse breakdown voltage that is closer to the theoretical breakdown voltage of an ideal PN.
• a method according to the present invention allows for the fabrication of diverse devices in a common die. That is, it allows for the fabrication of integrated devices in which different devices are formed over a common substrate.
• devices which may be fabricated according to the present invention are NPN, PNP, N-channel, or P-channel devices.
• a method according to the present invention can be adapted for fabrication of complimentary devices.
• Figure 1 is a top plan view of a device according to a first embodiment of the present invention.
• Figure 2 is a cross-sectional view of a device according to the -first embodiment of the present invention along line 2-2 and viewed in the direction of the arrows.
• Figures 3A-3C illustrate an embodiment of a method for fabricating a device according to the present invention.
• Figure 4 is a cross-sectional view of a second embodiment of a device according to the present invention.
• Figure 5 is a cross-sectional view of a third embodiment of a device according to the present invention.
• a device according to the first embodiment of the present invention includes a plurality of semiconductor devices formed on a common substrate 10.
• Substrate 10 maybe composed of Sapphire, SiC, Si or any other suitable material.
• First semiconductor device 12 in a device according to the present invention is an NPN field effect transistor which includes first conductive region 14 that is preferably composed of N+ GaNT, base region 16 that is preferably composed of P+ GaN and laterally adjacent first conductive region 14, second conductive region 18 that is preferably composed of N or N- GaN and laterally adjacent base region 16 and third conductive region 20 that is preferably composed of N+ GaHNT and laterally adjacent second conductive region 18.
• First conductive region 14 is tire source region
• second conductive region 18 is the drift region
• third conductive region 20 is the drain region of first semiconductor device 12.
• each region of first device 12 is a vertically oriented column and thus extends in a direction away from the surface of substrate 10 over which it is disposed. That is, each conductive region is a vertical column which is supported over a support surface of substrate 10.
• First semiconductor device 12 further includes first ohmic contact 22 (source contact) which is ohmically connected to first conductive region 14, second ohmic contact 24 (drain contact) whicli is ohmically comiected to third conductive region 20, and gate structure 26 which is disposed over base region 16.
• Gate structure 26 includes gate insulation 28 composed of SiO 2 or any suitable insulator, and gate electrode 30.
• Second semiconductor device 15 in a device according to the first embodiment of the present invention is a pin rectifier which includes first conductive region 32 that is preferably composed of P+ GaN, second conductive region 34 that is preferably composed of P- GaN and is laterally adjacent first conductive region 32 of second semiconductor device 14, and third conductive region 36 that is preferably composed of N+ GaN and is laterally adjacent to second conductive region 34.
• First region 32 is the anode region
• second conductive region 34 is the drift region
• the third conductive region 36 is the cathode region of second semiconductor device 15.
• Second semiconductor device 14 further includes first ohmic contact 38 (anode contact) which is ohmically connected to first conductive region 32 and second ohmic contact 40 (cathode contact) which is ohmically connected to third cond ⁇ ctive region.
• a device further includes third semiconductor device 42, which is preferably a PNP field effect transistor.
• Third semiconductor device 42 includes first conductive region 44 or the source region, which is preferably composed of P+ GaN, base region 46, which is preferably composed of N+ GaN and is laterally adjacent first conductive region 44, second conductive region 48 or the drift region which is composed of P- GaN and laterally adjacent base region 46, and third conductive region 50 or the drain region, which is preferably composed of P+ GaN and laterally adjacent second conductive region 48.
• Third semiconductor device 42 further includes first ohmic contact 52 (source contact), which is ohmically connected to its first conductive region 44, second ohmic contact 54 (drain contact), which is ohmically connected to third semiconductor region 54, and gate structure 56 which is disposed over base region 46.
• Gate structure 56 includes gate insulator 58 which is composed of SiO 2 or any other suitable insulator and gate electrode 60.
• a device further includes fourth semiconductor device 62, which is preferably also a pin rectifier.
• Fourth semiconductor device 62 includes first conductive region 64 or the cathode region, which is preferably composed of N+ GaN, second conductive region 66 or the drift region, which is preferably composed of N or N- GaN and is laterally adjacent first semiconductor region 64, and third semiconductor region 68 or the anode region, which is preferably composed of P+ GaN and is laterally adjacent second conductive region 66 thereof.
• Fourth semiconductor device 62 further includes first ohmic contact 70 (cathode contact) which is ohmically connected to first conductive region 64 thereof, and second ohmic contact 72 (anode contact) which is ohmically connected to third conductive region 68 thereof.
• first semiconductor device 12 is disposed lateral to, but spaced from second semiconductor device
• second semicondxictor device 15 is disposed lateral to, but spaced from third semiconductor device 42
• third semiconductor device 42 is disposed lateral to, but spaced from fourth semiconductor device 62.
• Each semiconductor device is also electrically insulated from a laterally spaced semiconductor device by an insulating body 74, which in the preferred embodiment may be insulating GaN.
• growth inhibition layer 7 ⁇ is formed over substrate 10 by first depositing a layer growth inhibiting material such as, HfO or SiO2, over a single major surface of substrate 10 and then etching selected regions thereof to ready selected regions 76 for growth of conductive regions.
• a layer growth inhibiting material such as, HfO or SiO2
• N+ GaN regions which will constitute conductive region 20 and 64 in first semiconductor device 12 and fourth semiconductor device 62 respectively, are epitaxially grown over selected regions 78 of substrate 10 which are not covered by grown inhibition layer 76. As seen in Figure 3B, each conductive region rises above grown inhibition layer 76 and includes open surfaces 80.
• the semiconductor regions which will constitute conductive regions in semiconductor devices 12, 15, 42, 62 and non-conductive -regions 74 are formed in consecutive epitaxial steps. Specifically, regions 18 and 66 are formed to a desired thickness over open surfaces 80 of regions 20 and 64, respectively.
• regions 18 and 66 will grow laterally on open surfaces 80 of conductive regions 20, 64, respectively, and once the growth process is terminated (when a desired thickness is reached), region 8 will have a surface opposite to surface 80 of region 20 ready to receive a semiconductor layer, and region 66 will have a surface opposite to surface 80 of region 64 ready to receive a semiconductor layer. Thereafter, the semiconductor regions for a device according to the present invention are formed in the same manner until preferably gap 82 between regions 20 and 64 is filled. Thereafter, ohmic contacts and gate structures are formed where appropriate to obtain a device according to the present invention as seen, for example, in Figure 2.
• the columns need not be at a 90° angle with respect to substrate 10, but can be tilted to be at an angle other then 90° without deviating from the present invention.
• a device according to the second embodiment further includes semiconductor layers 84, 86 added to first semiconductor device 12 and fourth semiconductor device 62.
• Semiconductor layers 84, 86 are preferably composed of AlGaN. Due to the piezoelectric polarization effect a two dimensional electron gas (2DEG) is formed just below the jun_ction between AlGaN region 84 and GaN in regions 18 and 20 of first semiconductor device 12, and the junction between AlGaN region 86 and GaN regions 64 and 66.
• 2DEG two dimensional electron gas
• AlGaN regions are formed after the formation of laterally adjacent regions is completed (i.e. after the conclusion of the process described with reference to Figures 3A-3C). Thereafter, ohmic contacts and gate structures are formed to obtain a device according to the second embodiment of the present invention.
• a device may include a column of insulating GaN 74 below gate structures 26, 56, which in combination with single semiconductor layer 88 that is formed from AlGaN replicate the characteristics of a standard AlGaN/GaN HFET. That is, a 2DEG is formed between AlGaN layer 88 and the insulating GaN 74 below the same.
• a third embodiment of the present invention includes a single semiconductor layer 88 extending over all of the laterally adjacent conductive regions.
• Single semiconductor layer 88 is preferably composed of AlGaN and is included to increase the mobility of carriers. AlGaN can be fonned to take advantage of piezoelectric polarization effect.
• Single semiconductor layer 88 can be epitaxially grown after the conclusion of the process described with reference to Figures 3A-3C. Thereafter, the ohmic contacts and the gate structures are formed to obtain a device according to the third embodiment of the present invention.

Landscapes

• Junction Field-Effect Transistors (AREA)
• Thin Film Transistor (AREA)
• Bipolar Transistors (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Electrodes Of Semiconductors (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Priority Applications (2)

Applications Claiming Priority (4)

Publications (2)

Family

ID=34840655

Family Applications (1)

Country Status (5)

Cited By (1)

Family Cites Families (16)

• 2005
  • 2005-02-11 US US11/056,833 patent/US7205657B2/en not_active Expired - Lifetime
  • 2005-02-14 JP JP2006553314A patent/JP2007527115A/ja active Pending
  • 2005-02-14 WO PCT/US2005/004609 patent/WO2005079365A2/en not_active Ceased
  • 2005-02-14 KR KR1020067015753A patent/KR100772730B1/ko not_active Expired - Lifetime
  • 2005-02-14 DE DE112005000353T patent/DE112005000353T5/de not_active Withdrawn
• 2006
  • 2006-12-04 US US11/633,304 patent/US7510957B2/en not_active Expired - Lifetime

Also Published As

Similar Documents

Legal Events