CN112490278B - 具有减少的缺陷的半导体外延结构 - Google Patents

具有减少的缺陷的半导体外延结构 Download PDF

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CN112490278B
CN112490278B CN201910862592.0A CN201910862592A CN112490278B CN 112490278 B CN112490278 B CN 112490278B CN 201910862592 A CN201910862592 A CN 201910862592A CN 112490278 B CN112490278 B CN 112490278B
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layer
epitaxial structure
semiconductor epitaxial
reduced defects
substrate
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CN112490278A (zh
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张峻铭
侯俊良
廖文荣
卢明昌
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United Microelectronics Corp
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Abstract

本发明公开一种具有减少的缺陷的半导体外延结构，包含一基底，该基底上具有一凹槽、一岛状绝缘体，设置在该凹槽的底面上、间隔壁，设置在该凹槽的侧壁上、一缓冲层，设置在该凹槽中并盖住该岛状绝缘体、一通道层，设置在该凹槽中以及该缓冲层上、以及一阻障层，设置在该凹槽中以及该通道层上，其中该通道层中形成二维电子气或是二维空穴气。

Description

具有减少的缺陷的半导体外延结构
技术领域
本发明涉及一种半导体外延结构，更具体言之，其涉及一种具有二维电子气或是二维空穴气且缺陷较少的半导体外延结构。
背景技术
形成异质结(接面)的能力使得氮化镓成为了用来制作高电子移动率晶体管(highelectron mobility transistor,HEMT)或是高空穴移动率晶体管(high hole mobilitytransistor,HHMT)的优异材料。这种晶体管的优点包含高载流子浓度以及因为其游离杂质散射较少所导致的高载流子移动率。高载流子浓度与高载流子移动率的结合也导致了其具备高电流密度与低通道电阻的特性，此两特性在高频运作与电源切换的应用方面都十分重要。
在空乏(depletion)模式的高电子移动率晶体管场合，栅极所产生的电场会用来耗尽半导体宽带隙与窄带隙界面处的二维电子气(two-dimension electron gas,2DEG)通道，如氮化铝/氮化镓(AlN/GaN)或氮化铝镓/氮化镓(AlGaN/GaN)之间的界面，在栅极施加控制电压可直接影响与控制流经该通道的电流量。空乏型晶体管在作为开关时是以正常开启(normally-on)元件的型态运作的。在增强(enhance)模式下的高电子移动率晶体管，其晶体管在被施加偏压运作之前不会有通道与电流存在，其特别之处在于晶体管会被施加偏压来使其二维电子气通道移动到费米能阶以下，此时一旦源极与漏极之间有施加电压，二维电子气通道中的电子就会从源极移动到漏极。增强型晶体管一般用在数字与模拟集成电路中作为正常关闭(normally-off)元件。增强型晶体管在模拟电路应用方面也很有用处，例如作为射频/微波功率放大器或开关。
然而，上述的高电子移动率晶体管或是高空穴移动率晶体管通常是以多层的外延结构构成的，其容易有高应力与缺陷多等问题，导致元件的特性会大幅受到外延品质的影响，故此，相关领域与业界仍然在持续改善这类元件的结构与制作方法。
发明内容
有鉴于前述现有技术中的外延结构容易有缺陷的问题，本发明于此提出了一种具有减少的缺陷的半导体外延结构，其特点在于使用选择性的外延生长方式来减少应力与缺陷，其中并设置岛状绝缘体来进一步改善侧向击穿电压，以及设置间隔壁来达到反平台隔离式的元件绝缘功效。
本发明提出一种具有减少的缺陷的半导体外延结构，包含一基底，该基底上具有一凹槽、一岛状绝缘体，设置在该凹槽的底面上、间隔壁，设置在该凹槽的侧壁上、一缓冲层，设置在该凹槽中并盖住该岛状绝缘体、一通道层，设置在该凹槽中以及该缓冲层上、以及一阻障层，设置在该凹槽中以及该通道层上，其中该阻障层、该通道层以及该缓冲层都为该间隔壁所围绕，且该通道层中形成二维电子气或是二维空穴气。
本发明另提出一种具有减少的缺陷的半导体外延结构，包含一硅基底、一绝缘层，设置在该基底上，其中该绝缘层中具有一凹槽裸露出该基底、一岛状绝缘体，设置在该凹槽中的该基底上、间隔壁，设置在该凹槽的侧壁上、一缓冲层，设置在该凹槽中并盖住该岛状绝缘体、一通道层，设置在该凹槽中以及该缓冲层上、以及一阻障层，设置在该凹槽中以及该通道层上，其中该阻障层、该通道层以及该缓冲层都为该间隔壁所围绕，且该通道层中形成二维电子气或是二维空穴气。
本发明的这类目的与其他目的在阅者读过下文中以多种附图与绘图来描述的优选实施例的细节说明后应可变得更为明了显见。
附图说明
本说明书含有附图并于文中构成了本说明书的一部分，使阅者对本发明实施例有进一步的了解。该些附图描绘了本发明一些实施例并连同本文描述一起说明了其原理。在该些附图中：
图1为本发明实施例的半导体外延结构的细部层结构的截面示意图；
图2～图6为本发明实施例的半导体外延结构的制作流程的截面示意图；
图7为本发明另一实施例的半导体外延结构的截面示意图；
图8～图11为本发明另一实施例的半导体外延结构的制作流程的截面示意图；以及
图12为本发明另一实施例的半导体外延结构的截面示意图。
需注意本说明书中的所有附图都为图例性质，为了清楚与方便附图说明之故，附图中的各部件在尺寸与比例上可能会被夸大或缩小地呈现，一般而言，图中相同的参考符号会用来标示修改后或不同实施例中对应或类似的元件特征。
主要元件符号说明
100 半导体外延结构
102 基底
104 成核层
106 超晶格叠层
108 碳掺杂氮化镓层
110 缓冲层
112 通道层
114 阻障层
116 栅极层
118 硬掩模
120 光致抗蚀剂
122 凹槽
124 氧化硅层
124a 岛状绝缘体
124b 间隔壁
126 光致抗蚀剂
128 绝缘层
130 光致抗蚀剂
132 光致抗蚀剂
具体实施方式
现在下文将详细谈述本发明的实施范例，其绘示在随附的附图中让阅者得以了解与施作本发明揭露，并知晓其技术功效。需注意下文仅是以范例的方式来进行说明，其并未要限定本发明的揭露内容。本发明中的多种实施例以及该些实施例中的各种特征在不互相冲突抵触的情况下可以多种不同的方式来加以组合与重设。在不悖离本发明的精神与范畴的原则下，各种对于本发明揭露内容的修改、对应物、或是改良手段等应都能为本技术领域的相关技术人士所理解，且意欲含括在本发明揭露的范畴内。
应该容易理解的是，本文中的「在...上面」、「在...之上」及「在...上方」的含义应该以最宽义的方式来解释，使得「在...上面」不仅意味着「直接在某物上」，而且还包括在某物上且两者之间具有中间特征或中间层，并且「在...之上」或「在...上方」不仅意味着在某物之上或在某物上方的含义，而且还可以包括两者之间没有中间特征或中间层(即直接在某物上)的含义。
此外，为了便于描述，可以在说明书使用诸如「在...下面」、「在...之下」、「较低」、「在...之上」、「较高」等空间相对术语来描述一个元件或特征与另一个或多个元件或特征的关系，如附图中所表示者。除了附图中描绘的方向之外，这些空间相对术语旨在涵盖使用或操作中的装置的不同方位或方向。该装置可以其他方式定向(例如以旋转90度或以其它方向来定向)，并且同样能相应地以说明书中所使用的空间相关描述来解释。
如本文所使用的，术语「层」是指一材料部分，其一区域具有一厚度。一层的范围可以在整个下层或上层结构上延伸，或者其范围可以小于下层或上层结构的范围。此外，一层可以为均匀或不均匀连续结构的一区域，其厚度可小于该连续结构的厚度。例如，一层可以位于该连续结构的顶表面及底表面之间或在该连续结构的顶表面及底表面之间的任何一对水平平面之间。一层可以水平地、垂直地及/或沿着渐缩表面延伸。一基底可以为一层，其可以包括一层或多层，及/或可以在其上面及/或下面具有一层或多层。一层可以包含多层。例如，互连层可以包括一个或多个导体及接触层(其中形成有接点、互连线及/或通孔)以及一个或多个介电层。
现在下文将说明根据本发明实施例的半导体外延结构及其制作方法，其中图1绘示出了此半导体外延结构100的细部层结构，图2～图6则绘示出了此半导体外延结构100的制作流程。
请参照图1，首先提供一基底102。基底102可以硅或是其他半导体材料制成。在一些实施例中，基底102是硅晶片，其上具有一〈111〉晶格结构的硅层。硅〈111〉层可对上层提供理想的晶格匹配，如对上层的氮化镓(GaN)层或是超晶格层。在一些实施例中，基底102也可以半导体化合物来制成，如碳化硅(SiC)、砷化镓(GaAs)、砷化铟(InAs)、或是磷化铟(InP)。在一些实施例中，基底102也可以半导体合金来制成，如硅锗、碳化硅锗、磷化砷镓、或是磷化铟镓。
一成核层104形成在基底102上。在本发明实施例中，成核层104用来补偿基底102与上层结构之间晶格结构与/或热膨胀系数不匹配的情况，以提供良好的外延生长基础。在一些实施例中，成核层104的材料可为氮化铝(AlN)。成核层104的晶格结构可逐步改变，以促成基底102与上层结构之间晶格结构与/或热膨胀系数的逐步转变。例如在一些实施例中，成核层104包含一成分梯度转变的氮化铝镓(AlXGa1-XN)，其中x是氮化铝镓中的铝成分比例，x介于0至1之间。较佳来说，x值从靠近成核层104的底面往顶面逐渐下降。
复参照图1，一超晶格叠层106形成在成核层104上，例如氮化铝镓/氮化镓的交互叠层或是氮化铝镓/氮化铟镓的交互叠层。在本发明实施例中，超晶格叠层106结构的功用在于可通过其水平方向的应变消除三维半导体结构的层结构在生长时垂直方向上的应力，如此较不会产生错位、断裂等缺陷，进而影响到层结构的品质。
一碳掺杂氮化镓层108形成在超晶格叠层106上。在本发明实施例中，碳掺杂氮化镓层108的存在有助于大幅提高后续使用半导体外延结构100所制作出的元件的击穿电压，并减少其垂直漏电流。碳掺杂氮化镓层108的厚度越厚，其功效越佳。
在上述实施例中，成核层104、超晶格叠层106、以及碳掺杂氮化镓层108都可归类为是半导体外延结构100中缓冲层110的一部分，其逐步改变了基底102与后续外延结构之间晶格结构与热膨胀系数不匹配情况，以减少缺陷的产生，进而改善所制作出的元件的电性。
复参照图1，一通道层112形成在缓冲层110上。在本发明实施例中，通道层112的电阻值会低于缓冲层110的电阻值，如此后续制作出的元件会有较佳的电流表现。在一些实施例中，通道层112含有一或多个III-V族化合物层。这类III-V族化合物材料的例子包括但不限定是氮化镓(GaN)、氮化铝镓(AlGaN)、氮化铟镓(InGaN)、氮化铟铝镓(InAlGaN)等，特别是未掺杂的氮化镓层。
一阻障层114形成在通道层112之上。在本发明实施例中，阻障层114设置来与通道层112产生一异质结，其间存在着带隙不连续性。在一些实施例中，阻障层114的带隙会大于通道层112的带隙，阻障层114中因为压电极化效应产生的电子会落入通道层112中，从而产生出一高移动传导性的电子薄层，此即通道层112中的二维电子气(two-dimensionelectron gas,2DEG)，其位置邻近与阻障层114相接的界面处。在n型半导体的情况下，二维电子气2DEG中的电子是通道层112中的电荷载体。后续在阻障层114上形成出栅极与源/漏极等结构即可制作出高电子移动率晶体管(high electron mobility transistor,HEMT)。在其他实施例中，例如在阻障层114与通道层112掺有碳、铁、镁、或锌等p型掺质的情况下，阻障层114与通道层112之间所形成的电荷载体会是二维空穴气(two-dimension holegas,2DHG)，后续在阻障层114上形成出栅极与源/漏极等结构即可制作出高空穴移动率晶体管(high hole mobility transistor,HHMT)。高电子移动率晶体管与高空穴移动率晶体管是一种场效晶体管，其结合了不同带隙的材料之间的结(即异质结)来作为通道，而非使用一般如金属氧化物半导体场效晶体管(MOSFET)的掺杂区。
承上述实施例，由于二维电子气2DEG的通道载体是在没有栅极结构的情况下自然产生的，其不用对栅极施加电压即为导通态。因此，其所制作出的高电子移动率晶体管在负临限电压的场合下会是正常开启(normally-on)元件。这样的正常开启状态在功率元件应用的设计考虑下是不利的，因为其要避免或是在很大的程度上抑止电流流经或流入高电子移动率晶体管。在一些实施例中，为了要将正常开启态的高电子移动率晶体管元件转变成正常关闭态(normally-off)，阻障层114上方还会形成一栅极层116来制作栅极，以耗尽栅极下方的二维电子气2DEG形成正常关闭态通道。在本发明实施例中，栅极层116的材料包含但不限定是p型掺杂的氮化镓(p-GaN)。
上述实施例中所提到的各层都可以外延生长制作工艺来形成，其例子包含但不限定是金属有机物化学气相沉积(MOCVD)、分子束外延(MBE)制作工艺、以及氢化物气相外延(HVPE)制作工艺等。上述实施例所提到的各层也都可以在相同的制作工艺腔体中临场(in-situ)进行，不需换腔体，以节省成本与时间并降低污染。
在说明完本发明实施例的半导体外延结构的细部层结构特征后，接下来请参照图2～图6，其将依序说明本发明实施例半导体外延结构100的制作步骤。首先请参照图1，同样是提供硅基底102，使用图案化光致抗蚀剂120与硬掩模118进行一光刻制作工艺，进而在硅基底102上形成一凹槽122。在本发明实施例中，形成凹槽122的目的是希望能将外延结构选择性地只形成在凹槽122中，其有别于现有技术中整个基底上毯覆式外延生长的作法。
接下来请参照图3，在凹槽122形成后，将光致抗蚀剂120移除，并在整个基底102包括凹槽122上形成一层氧化硅层124。在本发明实施例中，氧化硅层124形成来在后续制作工艺中制作出岛状绝缘体与间隙壁结构。氧化硅层124可以现有的沉积制作工艺来形成，包括化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)、高密度等离子体化学气相沉积(HDPCVD)、金属有机物化学气相沉积(MOCVD)、等离子体辅助化学气相沉积(PECVD)、或其他可应用的沉积制作工艺。
接下来请参照图4，氧化硅层124形成后，在氧化硅层124上形成另一图案化光致抗蚀剂126。如图4所示，一部分的光致抗蚀剂126会形成在凹槽122内的氧化硅层124上，用以界定出后续所要形成的岛状绝缘体的形状与位置。另一部分的光致抗蚀剂126则形成在凹槽外的氧化硅层124上，需注意为了要制作出间隔壁结构，此部分的光致抗蚀剂126不会盖住氧化硅层124位于凹槽122侧壁上的部位。
接下来请参照图5。光致抗蚀剂126形成后，进行一蚀刻制作工艺将未被光致抗蚀剂126覆盖的氧化硅层124部分移除。如此，凹槽122底面的中央部位上会形成一预定的岛状绝缘体124a，而凹槽122的侧壁上则会有氧化硅层124的间隔壁124b部位余留。需注意在本发明实施例中，此蚀刻制作工艺的参数会被调控成具有些许的等向性质，使得蚀刻所形成的岛状绝缘体124a与间隔壁124b具有从基底102向上渐缩的特征。此特征的功效在后续实施例中将有进一步的说明。
接下来请参照图6。岛状绝缘体124a与间隔壁124b形成后，如图1所述般，在基底102的凹槽122中依序形成缓冲层、通道层112、以及阻障层114等层结构。为了附图简明之故，前述缓冲层110的子层中仅有超晶格叠层106与碳掺杂氮化镓层108会在图中示出，且栅极层116不予示出。其中，超晶格叠层106会形成在岛状绝缘体124a的侧边，碳掺杂氮化镓层108则是盖覆在整个岛状绝缘体124a与超晶格叠层106上。该些层都可以外延生长制作工艺在机台的同一制作工艺腔体中临场(in-situ)形成，其例子包含但不限定是金属有机物化学气相沉积(MOCVD)、分子束外延(MBE)制作工艺、以及氢化物气相外延(HVPE)制作工艺等。另一方面，在本发明实施例中，由于凹槽122侧壁上具有间隔壁124b的缘故，所生长形成的缓冲层、通道层112、以及阻障层114等层结构都会为该间隔壁124b所围绕。最后，将位于凹槽外部的硬掩模118与氧化硅层124移除，如此即完成了本发明半导体外延结构100之制作。实作中，后续可在半导体外延结构100上进行栅极、源/漏极、接触结构、金属绕线的制作，如此即能构成高电子移动率晶体管或是高空穴移动率晶体管。由于该些制作工艺并非本发明的重点，此处将省略其细节说明。
在本发明实施例中，具有渐缩特征的岛状绝缘体124a与间隔壁124b可以改善提高整个外延结构的侧向击穿电压。例如，在整体外延结构因为晶格或是热膨胀系数不匹配而产生压应力的情况下，向上渐缩的岛状绝缘体124a与间隔壁124b特征舒缓了外延叠层的侧向压应力，使得所生长出的外延叠层缺陷较少，提升层结构的品质。特别是超晶格叠层106位于岛状绝缘体124a的两侧，由于岛状绝缘体124a中介其间，两侧的超晶格叠层106原有释放应力的功效可望进一步提升。另一方面，只将外延叠层形成在凹槽中的选择性生长由于是各个独立单元小面积的生长方式，相较于现有技术中在整面基底上毯覆式的生长，其不会累积大量的应力，进一步舒缓了应力问题。再者，在本发明实施例中，岛状绝缘体124a与间隔壁124b的制作工艺简单相当，选择性的外延生长也可降低制作工艺成本。
另一方面，凹槽122与间隔壁124b的搭配在本发明中达成了反平台隔离式(anti-mesa)的元件隔离功效。一般现有技术中的元件采用平台隔离作法，即使用光刻制作工艺将各元件/晶体管彼此分离，并在其间填入绝缘材料如浅沟渠隔离结构(STI)来提供电性绝缘效果。本发明的作法结合选择性外延生长所带来的凹槽特征，以此在凹槽122侧壁上形成具有绝缘性质的间隔壁124b，其同样能达到元件隔离功效，且相较于平台隔离式作法具有更优异的平坦化特性。故综合上述所言，本发明提出了一兼具多项优点的新颖半导体外延结构。
现在请参照图7。在其他实施例中，例如在整体外延结构因为晶格或是热膨胀系数不匹配而产生张应力的情况下，岛状绝缘体124a与间隔壁124b可修改成是具有向下渐缩至基底102的特征，如图7所示。这样的特征可以透过调控制蚀刻制作工艺的参数来达成。向下渐缩的岛状绝缘体124a与间隔壁124b特征，与图6相反地，舒缓了外延叠层的侧向张应力，使得所生长出的外延叠层缺陷较少，提升层结构的品质。在本发明实施例中，岛状绝缘体124a与间隔壁124b的渐缩型态端视外延层的材料组成与实际需求而定。
接下来请参照图8～图11，其为根据本发明另一实施例的半导体外延结构的制作步骤。首先请参照图8，同样是提供硅基底102，与图1不同的是，此实施例的凹槽122是形成在一绝缘层128而非基底102中。如图8所示，使用图案化光致抗蚀剂130进行一光刻制作工艺在绝缘层128中形成凹槽122并裸露出基底102。
接下来请参照图9，在凹槽122形成后，将光致抗蚀剂120移除，并在整个基底102包括凹槽122上形成一层氧化硅层124。在本发明实施例中，氧化硅层124形成来在后续制作工艺中制作出岛状绝缘体与间隙壁结构。氧化硅层124可以现有的沉积制作工艺来形成，包括化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)、高密度等离子体化学气相沉积(HDPCVD)、金属有机物化学气相沉积(MOCVD)、等离子体辅助化学气相沉积(PECVD)、或其他可应用的沉积制作工艺。
接下来请参照图10，氧化硅层124形成后，在氧化硅层124上形成另一图案化光致抗蚀剂132。如图所示，一部分的光致抗蚀剂132形成在凹槽122内的氧化硅层124上，用以界定出后续所要形成的岛状绝缘体。另一部分的光致抗蚀剂132则形成在凹槽122外的氧化硅层124上，须注意为了要制作出间隔壁结构，此部分的光致抗蚀剂132不会盖住氧化硅层124位于凹槽122侧壁上的部位。光致抗蚀剂132形成后，进行一蚀刻制作工艺移除未被光致抗蚀剂132覆盖的氧化硅层124部分。如此，凹槽122底面的中央部位上会形成一预定的岛状绝缘体124a，而凹槽122的侧壁上会有氧化硅层124的间隔壁124b部位余留。须注意在本发明实施例中，此蚀刻制作工艺的参数会被调控成具有些许的等向性质，使得蚀刻所形成的岛状绝缘体124a与间隔壁124b具有从基底102向上渐缩的特征，如图10所示。
接下来请参照图11。岛状绝缘体124a与间隔壁124b形成后，如图1所述般，在基底102的凹槽122中依序形成缓冲层、通道层112、以及阻障层114等层结构。为了附图简明之故，前述缓冲层110的子层中仅有超晶格叠层106与碳掺杂氮化镓层108会在图中示出，且栅极层116不予示出。其中，超晶格叠层106会形成在岛状绝缘体124a的侧边，碳掺杂氮化镓层108则是盖覆在整个岛状绝缘体124a与超晶格叠层106上。该些层都可以外延生长制作工艺在机台相同的制作工艺腔体中临场(in-situ)形成，其例子包含但不限定是金属有机物化学气相沉积(MOCVD)、分子束外延(MBE)制作工艺、以及氢化物气相外延(HVPE)制作工艺等。另一方面，在本发明实施例中，由于凹槽122侧壁上具有间隔壁124b的缘故，所生长形成的缓冲层、通道层112、以及阻障层114等层结构都会为该间隔壁124b所围绕。最后，将位于凹槽外部的氧化硅层124移除，如此即完成了本发明半导体外延结构100的制作。
在本实施例中，与图6实施例不同的是，半导体外延结构100是形成在绝缘层128而非硅质基底102中。搭配间隔壁124b，元件与元件之间的隔离效果更佳，且同样制作工艺简单，可达到选择性外延生长的目的。再者，所形成的绝缘层128也可在蚀刻凹槽122的阶段产生如间隔壁124b般的向上渐缩特征，来进一步强化应力释放的功效。
现在请参照图12。在其他实施例中，例如在整体外延结构因为晶格或是热膨胀系数不匹配而产生张应力的情况下，岛状绝缘体124a与间隔壁124b可变成是具有向下渐缩至基底102的特征，如图12所示。这样的特征可以透过调控制蚀刻制作工艺的参数来达成。向下渐缩的岛状绝缘体124a与间隔壁124b特征，与图11相反地，舒缓了外延叠层的侧向张应力，使得所生长出的外延叠层缺陷较少，提升层结构的品质。再者，所形成的绝缘层128也可在蚀刻凹槽122的阶段产生如间隔壁124b般的向下渐缩特征，来进一步强化应力释放的功效。在本发明实施例中，岛状绝缘体124a、间隔壁124b、以及绝缘层128的渐缩型态端视外延层的材料组成与实际需求而定。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种具有减少的缺陷的半导体外延结构，其特征在于，该具有减少的缺陷的半导体外延结构包含：
基底，该基底上具有凹槽；
岛状绝缘体，设置在该凹槽的底面上；
间隔壁，设置在该凹槽的侧壁上；
缓冲层，设置在该凹槽中并盖住该岛状绝缘体；
通道层，设置在该凹槽中以及该缓冲层上；以及
阻障层，设置在该凹槽中以及该通道层上，其中该阻障层、该通道层以及该缓冲层都为该间隔壁所围绕，且该通道层中形成二维电子气或是二维空穴气。
2.根据权利要求1所述的具有减少的缺陷的半导体外延结构，其中该岛状绝缘体从该基底向上渐缩。
3.根据权利要求1所述的具有减少的缺陷的半导体外延结构，其中该岛状绝缘体向下渐缩至该基底。
4.根据权利要求1所述的具有减少的缺陷的半导体外延结构，其中该间隔壁从该基底向上渐缩。
5.根据权利要求1所述的具有减少的缺陷的半导体外延结构，其中该间隔壁向下渐缩至该基底。
6.根据权利要求1所述的具有减少的缺陷的半导体外延结构，其中该缓冲层由下而上依序包括成核层、超晶格层、以及碳掺杂氮化镓层。
7.根据权利要求6所述的具有减少的缺陷的半导体外延结构，其中该成核层的材料为氮化铝镓或氮化铝。
8.根据权利要求6所述的具有减少的缺陷的半导体外延结构，其中该超晶格层为氮化铝镓/氮化镓的交互叠层或是氮化铝镓/氮化铟镓的交互叠层。
9.根据权利要求1所述的具有减少的缺陷的半导体外延结构，其中该通道层的材料为未掺杂氮化镓。
10.根据权利要求1所述的具有减少的缺陷的半导体外延结构，其中该阻障层的材料为氮化铝镓。
11.一种具有减少的缺陷的半导体外延结构，其特征在于，该具有减少的缺陷的半导体外延结构包含：
基底；
绝缘层，设置在该基底上，其中该绝缘层中具有一凹槽裸露出该基底；
岛状绝缘体，设置在该凹槽中的该基底上；
间隔壁，设置在该凹槽的侧壁上；
缓冲层，设置在该凹槽中并盖住该岛状绝缘体；
通道层，设置在该凹槽中以及该缓冲层上；以及
阻障层，设置在该凹槽中以及该通道层上，其中该阻障层、该通道层以及该缓冲层都为该间隔壁所围绕，且该通道层中形成二维电子气或是二维空穴气。
12.根据权利要求11所述的具有减少的缺陷的半导体外延结构，其中该岛状绝缘体从该基底向上渐缩。
13.根据权利要求11所述的具有减少的缺陷的半导体外延结构，其中该岛状绝缘体向下渐缩至该基底。
14.根据权利要求11所述的具有减少的缺陷的半导体外延结构，其中该间隔壁从该基底向上渐缩。
15.根据权利要求11所述的具有减少的缺陷的半导体外延结构，其中该间隔壁向下渐缩至该基底。
16.根据权利要求11所述的具有减少的缺陷的半导体外延结构，其中该缓冲层由下而上依序包括成核层、超晶格层、以及碳掺杂氮化镓层。
17.根据权利要求16所述的具有减少的缺陷的半导体外延结构，其中该成核层的材料为氮化铝镓或氮化铝。
18.根据权利要求16所述的具有减少的缺陷的半导体外延结构，其中该超晶格层为氮化铝镓/氮化镓的交互叠层或是氮化铝镓/氮化铟镓的交互叠层。
19.根据权利要求11所述的具有减少的缺陷的半导体外延结构，其中该通道层的材料为未掺杂氮化镓。
20.根据权利要求11所述的具有减少的缺陷的半导体外延结构，其中该阻障层的材料为氮化铝镓。
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