JP2007500953A - 不揮発性メモリデバイス - Google Patents
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
Description
本発明の他の実施形態によれば、図7Aに示すように、多数のフィンを備えたメモリデバイスが形成される。図7Aには、半導体デバイス700は、基板(図示しない)上に形成された埋め込み酸化層710と、この埋め込み酸化層710上に形成されたシリコンフィン730とを備えるシリコン・オン・インシュレータ(SOI:Silicon-On-Insulator)構造を備えることが示されている。シリコンフィン730は、図1及び図2Aに関して上述したフィン210と同様な方法で、シリコン層を選択的にエッチングすることによって形成される。
Claims (10)
- 基板(110)、
前記基板(110)の上に形成された絶縁層(120)、
前記絶縁層(130)の上に形成されたフィン構造(210)、
前記のフィン構造(210)を覆うように形成され、少なくとも一つがメモリデバイスの電荷格納誘電体として機能する複数の誘電層(310〜330)、及び、
前記複数の誘電層(310〜330)の上に形成された制御ゲート(510)、
を備える
メモリデバイス。 - 前記絶縁層(120)の上に形成され、前記フィン構造(210)の第1端部に隣接して配置されるソース領域(220)、及び、
前記絶縁層(120)の上に形成され、前記フィン構造(210)の第2端部に隣接して配置されるドレイン領域(230)をさらに備え、前記複数の誘電層(310−330)は、前記フィン構造(210)の上に形成された第1酸化層(310)、前記酸化層(310)の上に形成された窒化層(320)、及び、前記窒化層(320)の上に形成された第2酸化層(330)を有し、前記窒化層(320)は、浮遊ゲート電極として機能する
請求項1記載のメモリデバイス(100)。 - 前記第1酸化層(310)は、約15Å〜約150Åの範囲の膜厚を有し、前記窒化層(320)は、約10Å〜約180Åの範囲の膜厚を有し、及び、前記第2酸化層(330)は、約15Å〜約200Åの範囲の膜厚を有する、
請求項2記載のメモリデバイス(100)。 - 前記複数の誘電層(310−330)は、全体で約40Å〜約530Åの範囲の膜厚を有する、
請求項1記載のメモリデバイス(100)。 - 前記制御ゲート(510)は、ポリシリコンを含み、約300Å〜約4000Åの範囲の膜厚を有する、
請求項1記載のメモリデバイス(100)。 - 前記絶縁層(120)は、埋め込み層を含み、前記フィン構造(210)は、シリコンとゲルマニウムのうちの少なくとも一つを含み、前記フィン構造(210)は、約100Å〜約3000Åの範囲の幅を有する、
請求項1記載のメモリデバイス(100)。 - 不揮発性メモリデバイス(100)を製造する方法であって、
絶縁層(120)の上に前記不揮発メモリデバイス(100)の基板及びビットラインとして機能する、フィン(210)を形成する工程、
前記フィン(210)の上に配置され、電荷格納誘電体として機能する、複数の誘電層(310−330)を形成する工程、
ソース領域及びドレイン領域(220/230)を形成する工程、
前記複数の誘電層(310−330)の上にゲート材料(410)を堆積する工程、及び、
制御ゲート(510/520)を形成するために、前記ゲート材料(410)をパターニングして、エッチングする工程、
を備える方法。 - 前記複数の誘電層(310〜330)を形成する工程は、
前記フィン(210)の上に第1酸化層(310)を形成する工程、
前記第1酸化層(310)の上に窒化層(320)を堆積する工程、及び、
前記窒化層(320)の上に第2酸化層(330)を形成する工程、
を有する請求項7記載の方法。 - 前記第1酸化層(310)は、約15Å〜約150Åの範囲の膜厚を有し、前記窒化層(320)は、約10Å〜約180Åの範囲の膜厚を有し、前記第2酸化層(330)は、約15Å〜約200Åの範囲の膜厚を有する、
請求項8記載の方法。 - 基板、及び、前記基板上に形成された絶縁層を備える不揮発性メモリアレイ(600)であって、前記不揮発性メモリアレイ(600)は、
前記絶縁層上に形成され、前記不揮発メモリアレイ(600)のビットラインとして機能する複数の導電フィン(610)、
前記複数のフィン(610)の上に形成された複数の誘電層(620)、及び、
前記複数の誘電層(620)の上に形成され、不揮発性メモリアレイ(600)のワードラインとして機能する複数のゲート(630)、
によって特徴付けられる不揮発性メモリアレイ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/459,576 | 2003-06-12 | ||
US10/459,576 US6963104B2 (en) | 2003-06-12 | 2003-06-12 | Non-volatile memory device |
PCT/US2004/017726 WO2004112042A2 (en) | 2003-06-12 | 2004-06-05 | Non-volatile memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007500953A true JP2007500953A (ja) | 2007-01-18 |
JP4927550B2 JP4927550B2 (ja) | 2012-05-09 |
Family
ID=33510833
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006533566A Active JP4927550B2 (ja) | 2003-06-12 | 2004-06-05 | 不揮発性メモリデバイス、不揮発性メモリデバイスを製造する方法、および不揮発性メモリアレイ |
Country Status (8)
Country | Link |
---|---|
US (1) | US6963104B2 (ja) |
JP (1) | JP4927550B2 (ja) |
KR (1) | KR20060028765A (ja) |
CN (1) | CN1806334A (ja) |
DE (1) | DE112004001049B4 (ja) |
GB (1) | GB2418535B (ja) |
TW (1) | TWI344692B (ja) |
WO (1) | WO2004112042A2 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2009119527A1 (ja) * | 2008-03-26 | 2009-10-01 | 株式会社 東芝 | 半導体メモリ及びその製造方法 |
JP2011507231A (ja) * | 2007-12-07 | 2011-03-03 | エージェンシー フォー サイエンス,テクノロジー アンド リサーチ | シリコン−ゲルマニウムナノワイヤ構造およびその形成方法 |
JP2013504221A (ja) * | 2009-09-08 | 2013-02-04 | シリコン ストーリッジ テクノロージー インコーポレイテッド | Fin−FET型不揮発性メモリ・セル及びアレイ並びにその製造方法 |
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US6963104B2 (en) | 2005-11-08 |
JP4927550B2 (ja) | 2012-05-09 |
WO2004112042A2 (en) | 2004-12-23 |
CN1806334A (zh) | 2006-07-19 |
DE112004001049B4 (de) | 2011-02-24 |
DE112004001049T5 (de) | 2006-05-11 |
GB2418535A (en) | 2006-03-29 |
TW200503255A (en) | 2005-01-16 |
TWI344692B (en) | 2011-07-01 |
GB0525079D0 (en) | 2006-01-18 |
US20040251487A1 (en) | 2004-12-16 |
WO2004112042A3 (en) | 2005-03-17 |
GB2418535B (en) | 2007-11-07 |
KR20060028765A (ko) | 2006-04-03 |
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