JP2007266081A - 半導体装置及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000000576 coating method Methods 0.000 claims abstract description 56
- 239000011248 coating agent Substances 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000003860 storage Methods 0.000 claims description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 41
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 41
- 238000000151 deposition Methods 0.000 claims description 29
- 238000002955 isolation Methods 0.000 claims description 26
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 12
- 229920001709 polysilazane Polymers 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 abstract description 29
- 238000004299 exfoliation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 36
- 238000005530 etching Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 12
- 239000011344 liquid material Substances 0.000 description 7
- 239000000945 filler Substances 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 239000002131 composite material Substances 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 239000003960 organic solvent Substances 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000011049 filling Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- UHOVQNZJYSORNB-UHFFFAOYSA-N Benzene Chemical compound C1=CC=CC=C1 UHOVQNZJYSORNB-UHFFFAOYSA-N 0.000 description 3
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 3
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910008051 Si-OH Inorganic materials 0.000 description 2
- 229910006358 Si—OH Inorganic materials 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 230000006386 memory function Effects 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- DURPTKYDGMDSBL-UHFFFAOYSA-N 1-butoxybutane Chemical compound CCCCOCCCC DURPTKYDGMDSBL-UHFFFAOYSA-N 0.000 description 1
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 description 1
- 229910003814 SiH2NH Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 150000001298 alcohols Chemical class 0.000 description 1
- 150000007824 aliphatic compounds Chemical class 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 150000001491 aromatic compounds Chemical class 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002148 esters Chemical class 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002576 ketones Chemical class 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 239000008096 xylene Substances 0.000 description 1
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Abstract
【解決手段】半導体装置1において、基板10上に配設された堆積型絶縁膜121と、堆積型絶縁膜121の表面上に配設され、堆積型絶縁膜121の膜密度に比べて膜密度が低い塗布型絶縁膜123と、堆積型絶縁膜121と塗布型絶縁膜123との間に配設され、堆積型絶縁膜121の膜密度と塗布型絶縁膜123の膜密度との中間の膜密度を有する中間絶縁膜122とを備える。中間絶縁膜122にはOH終端処理が行われる。塗布型絶縁膜123にはメガソニック処理が行われる。
【選択図】図1
Description
図1乃至図3に示すように、本発明の一実施の形態に係る半導体装置1は、基板10表面部に配設されたチャネル形成領域20と、チャネル形成領域20上に配設された第1のゲート絶縁膜21と、第1のゲート絶縁膜21上に配設された電荷蓄積層(フローティングゲート電極)22と、電荷蓄積層22上に配設された第2のゲート絶縁膜23と、第2のゲート絶縁膜23上に配設された制御電極(コントロールゲート電極)24と、ソース領域及びドレイン領域として使用される一対の主電極領域26とを有する不揮発性記憶素子(メモリセル)Mとを有するNAND型EEPROMを備えている。更に、半導体装置1は、基板10表面のチャネル形成領域20を挟む対向位置に配設され、基板10表面からその深さ方向に向かって配設されたトレンチ(素子間分離用溝)11と、トレンチ11の内壁表面上に配設された堆積型絶縁膜121と、堆積型絶縁膜121の表面上に配設され、堆積型絶縁膜121の膜密度に比べて膜密度が低い塗布型絶縁膜123と、堆積型絶縁膜121と塗布型絶縁膜123との間に配設され、堆積型絶縁膜121の膜密度と塗布型絶縁膜123の膜密度との中間の膜密度を有する中間絶縁膜122とを有する絶縁分離領域(素子間分離領域)13とを備えている。
前述の半導体装置1の製造方法つまりNAND型EEPROM及び絶縁分離領域の製造方法を説明する。
本発明は、前述の一実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において種々変形可能である。例えば、前述の実施の形態はNAND型EEPROMを備えた半導体装置に本発明を適用した例を説明したが、本発明は、NAND型EEPROM以外の記憶装置の素子間を分離する絶縁分離領域を備えた半導体装置、論理素子間を分離する絶縁分離領域を備えた半導体装置等に適用することができる。
Claims (7)
- 基板上に配設された堆積型絶縁膜と、
前記堆積型絶縁膜の表面上に配設され、前記堆積型絶縁膜の膜密度に比べて膜密度が低い塗布型絶縁膜と、
前記堆積型絶縁膜と前記塗布型絶縁膜との間に配設され、前記堆積型絶縁膜の膜密度と前記塗布型絶縁膜の膜密度との中間の膜密度を有する中間絶縁膜と、
を備えたことを特徴とする半導体装置。 - 基板表面からその深さ方向に向かって配設されたトレンチと、
前記トレンチの内壁表面上に配設された堆積型絶縁膜と、
前記堆積型絶縁膜の表面上に配設され、前記堆積型絶縁膜の膜密度に比べて膜密度が低い塗布型絶縁膜と、
前記堆積型絶縁膜と前記塗布型絶縁膜との間に配設され、前記堆積型絶縁膜の膜密度と前記塗布型絶縁膜の膜密度との中間の膜密度を有する中間絶縁膜と、
を有する絶縁分離領域を備えたことを特徴とする半導体装置。 - 基板表面部に配設されたチャネル形成領域と、
前記チャネル形成領域上に配設された第1のゲート絶縁膜と、
前記第1のゲート絶縁膜上に配設された電荷蓄積層と、
前記電荷蓄積層上に配設された第2のゲート絶縁膜と、
前記第2のゲート絶縁膜上に配設された制御電極と、を有する不揮発性記憶素子と、
前記基板表面の前記チャネル形成領域を挟む対向位置に配設され、前記基板表面からその深さ方向に向かって配設されたトレンチと、
前記トレンチの内壁表面上に配設された堆積型絶縁膜と、
前記堆積型絶縁膜の表面上に配設され、前記堆積型絶縁膜の膜密度に比べて膜密度が低い塗布型絶縁膜と、
前記堆積型絶縁膜と前記塗布型絶縁膜との間に配設され、前記堆積型絶縁膜の膜密度と前記塗布型絶縁膜の膜密度との中間の膜密度を有する中間絶縁膜と、を有する絶縁分離領域と、
を備えたことを特徴とする半導体装置。 - 基板上に絶縁膜を堆積させる工程と、
前記絶縁膜上にポリシラザンを溶解した絶縁膜材料を塗布する工程と、
前記絶縁膜材料に熱処理を行い、シリコン酸化膜を形成する工程と、
前記シリコン酸化膜にメガソニック処理を行い、前記シリコン酸化膜の残留応力を減少させる工程と、
を備えたことを特徴とする半導体装置の製造方法。 - 基板上に第1の絶縁膜を堆積させる工程と、
前記第1の絶縁膜上に、第2の絶縁膜を形成する工程と、
前記第2の絶縁膜上に、ポリシラザンを溶解した絶縁膜材料を塗布する工程と、
前記絶縁膜材料に熱処理を行い、シリコン酸化膜を形成する工程とを備え、
前記第2の絶縁膜は、前記第1の絶縁膜の膜密度と前記シリコン酸化膜の膜密度との中間の膜密度を有することを特徴とする半導体装置の製造方法。 - 前記第2の絶縁膜を形成する工程は、前記第1の絶縁膜上にシリコン系絶縁膜を堆積させ、このシリコン系絶縁膜にOH終端処理を行うことを特徴とする請求項5に記載の半導体装置の製造方法。
- 前記シリコン酸化膜にメガソニック処理を行う工程を更に備えたことを特徴とする請求項5又は請求項6に記載の半導体装置の製造方法。
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KR1020060084012A KR100770820B1 (ko) | 2006-03-27 | 2006-09-01 | 반도체 장치 및 그 제조 방법 |
US11/685,984 US7803721B2 (en) | 2006-03-27 | 2007-03-14 | Semiconductor device and method of manufacturing same |
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US7651924B2 (en) | 2007-09-20 | 2010-01-26 | Kabushiki Kaisha Toshiba | Method of fabricating semiconductor memory device in which an oxide film fills a trench in a semiconductor substrate |
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JP2008010537A (ja) * | 2006-06-28 | 2008-01-17 | Toshiba Corp | Nand型不揮発性半導体記憶装置およびnand型不揮発性半導体記憶装置の製造方法 |
KR20100027388A (ko) * | 2008-09-02 | 2010-03-11 | 삼성전자주식회사 | 반도체 소자의 절연막 및 그를 이용한 반도체 소자의 형성방법 |
US8080463B2 (en) * | 2009-01-23 | 2011-12-20 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing method and silicon oxide film forming method |
US11600628B2 (en) * | 2020-01-15 | 2023-03-07 | Globalfoundries U.S. Inc. | Floating gate memory cell and memory array structure |
US11222825B2 (en) | 2020-03-10 | 2022-01-11 | Micron Technology, Inc. | Integrated circuitry, memory arrays comprising strings of memory cells, methods used in forming integrated circuitry, and methods used in forming a memory array comprising strings of memory cells |
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KR100770820B1 (ko) | 2007-10-26 |
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US7803721B2 (en) | 2010-09-28 |
US20070284649A1 (en) | 2007-12-13 |
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