JP2007235137A - 発光素子パッケージ及びその製造方法 - Google Patents
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B62—LAND VEHICLES FOR TRAVELLING OTHERWISE THAN ON RAILS
- B62D—MOTOR VEHICLES; TRAILERS
- B62D1/00—Steering controls, i.e. means for initiating a change of direction of the vehicle
- B62D1/02—Steering controls, i.e. means for initiating a change of direction of the vehicle vehicle-mounted
- B62D1/16—Steering columns
- B62D1/18—Steering columns yieldable or adjustable, e.g. tiltable
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01M—TESTING STATIC OR DYNAMIC BALANCE OF MACHINES OR STRUCTURES; TESTING OF STRUCTURES OR APPARATUS, NOT OTHERWISE PROVIDED FOR
- G01M17/00—Testing of vehicles
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Combustion & Propulsion (AREA)
- Transportation (AREA)
- Mechanical Engineering (AREA)
- Led Device Packages (AREA)
- Led Devices (AREA)
Abstract
【解決手段】第1面上に傾斜する側面を有する実装用溝110が形成されたパッケージ構造物100と、パッケージ構造物100上に備わり、互いに電気的に分離された2個の拡散層121、122と、絶縁膜130を介してパッケージ構造物100と絶縁され、2個の拡散層121、122にそれぞれ電気的に接続された第1及び第2電極141、142と、実装用溝110に備わり、第1及び第2電極141、142と電気的に接続された発光素子300と、を含んで発光素子パッケージを構成する。
【選択図】図3
Description
110 実装用溝
121 拡散層
122 拡散層
130 絶縁膜
141 第1電極
142 第2電極
300 発光素子
440 半田
450 モルディング部
Claims (19)
- パッケージ構造物と、
前記パッケージ構造物上に備えられ、互いに電気的に分離された2個の拡散層と、
絶縁膜を介して前記パッケージ構造物と絶縁され、前記2個の拡散層にそれぞれ電気的に接続された第1電極及び第2電極と、
を含んで構成されることを特徴とする発光素子パッケージ。 - 前記パッケージ構造物は、シリコン、セラミックまたはプラスチックからなることを特徴とする請求項1に記載の発光素子パッケージ。
- 前記パッケージ構造物は、第1面上に傾斜した側面を有する実装用溝が形成されたことを特徴とする請求項1に記載の発光素子パッケージ。
- 前記2個の拡散層は、互いに同一極性を有することを特徴とする請求項1に記載の発光素子パッケージ。
- 前記第2個の拡散層は、前記パッケージ構造物において拡散層が形成されていない領域の極性と異なる極性を有することを特徴とする請求項4に記載の発光素子パッケージ。
- 前記実装用溝に備わり、前記第1及び第2電極と電気的に接続された発光素子をさらに含む請求項3に記載の発光素子パッケージ。
- 前記実装用溝上に備えられた前記第1電極及び前記第2電極は、前記発光素子から放出される光を反射することを特徴とする請求項6に記載の発光素子パッケージ。
- 前記発光素子は、半田を介して前記実装用溝にフリップチップボンディングによって接合されていることを特徴とする請求項6に記載の発光素子パッケージ。
- 前記発光素子は、前記第1電極及び前記第2電極に並列に接続されていることを特徴とする請求項6に記載の発光素子パッケージ。
- 前記発光素子と前記実装用溝との間の空間を充填することで前記パッケージ構造物を密封するモルディング部をさらに含む請求項6に記載の発光素子パッケージ。
- 前記モルディング部は、複合樹脂粉末と、蛍光体パウダーと、を混合して構成されていることを特徴とする請求項10に記載の発光素子パッケージ。
- 前記絶縁膜は、前記2個の拡散層が形成されていない前記パッケージ構造物の表面全体に形成されていることを特徴とする請求項1に記載の発光素子パッケージ。
- パッケージ構造物と、
前記パッケージ構造物上に備えられた一つの拡散層と、
絶縁膜を介して前記パッケージ構造物と絶縁された第1電極及び第2電極と、
を含んで構成され、
前記第1電極は、前記拡散層に電気的に接続されていることを特徴とする発光素子パッケージ。 - 前記第2電極は、前記構造物と電気的に接続されていることを特徴とする請求項13に記載の発光素子パッケージ。
- 基板の第1面上に、少なくとも一つの拡散層を形成する段階と、
前記基板と絶縁され、前記拡散層に電気的に接続された第1電極及び第2電極を形成する段階と、を含んで構成されることを特徴とする発光素子パッケージの製造方法。 - 前記基板の第2面上にマスクを配置して露光した後、前記基板を選択的にエッチングし、傾斜した側面を有する実装用溝を形成する段階と、をさらに含む請求項15に記載の発光素子パッケージの製造方法。
- 前記第1電極及び前記第2電極と電気的に接続されるように、前記実装用溝に発光素子を半田を介してフリップチップボンディングによって接合する段階をさらに含む請求項16に記載の発光素子パッケージの製造方法。
- 複数個の発光素子パッケージを、前記基板上にウェハ単位で形成する段階と、
前記複数個の発光素子パッケージを個別の発光素子パッケージに分離する段階と、をさらに含む請求項15に記載の発光素子パッケージの製造方法。 - 前記基板をバルクマイクロマシニング工程で湿式エッチングすることで、前記基板を個別の発光素子パッケージに区分する貫通用ホールを形成し、前記各発光素子パッケージ上に実装用溝を形成する段階をさらに含む請求項18に記載の発光素子パッケージの製造方法。
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KR1020060019562A KR100746783B1 (ko) | 2006-02-28 | 2006-02-28 | 발광소자 패키지 및 그 제조방법 |
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JP2012250021A Pending JP2013034025A (ja) | 2006-02-28 | 2012-11-14 | 発光素子パッケージ及びその製造方法 |
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US (1) | US7738764B2 (ja) |
EP (1) | EP1826834B1 (ja) |
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KR (1) | KR100746783B1 (ja) |
CN (1) | CN101030617B (ja) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010534413A (ja) * | 2007-07-25 | 2010-11-04 | エルジー イノテック カンパニー リミテッド | 発光素子パッケージ及びその製造方法 |
JP2011502356A (ja) * | 2007-11-01 | 2011-01-20 | エルジー イノテック カンパニー リミテッド | 発光素子パッケージ及びその製造方法 |
JP2011223000A (ja) * | 2010-04-12 | 2011-11-04 | Lg Innotek Co Ltd | 発光素子、発光素子パッケージ |
JP2013141122A (ja) * | 2012-01-04 | 2013-07-18 | Nippon Telegr & Teleph Corp <Ntt> | 故障切り分け手順生成装置、故障切り分け手順生成方法、および故障切り分け手順生成プログラム |
WO2013187318A1 (ja) * | 2012-06-12 | 2013-12-19 | 株式会社村田製作所 | 発光装置 |
WO2013187319A1 (ja) * | 2012-06-12 | 2013-12-19 | 株式会社村田製作所 | 実装基板及び発光装置 |
WO2022244583A1 (ja) * | 2021-05-20 | 2022-11-24 | スタンレー電気株式会社 | 半導体装置及び半導体装置の製造方法 |
Families Citing this family (18)
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KR100767681B1 (ko) | 2006-12-04 | 2007-10-17 | 엘지전자 주식회사 | 발광 소자 패키지 및 그 제조방법 |
KR100877881B1 (ko) * | 2007-09-06 | 2009-01-08 | 엘지이노텍 주식회사 | 발광다이오드 패키지 및 그 제조방법 |
KR101349409B1 (ko) | 2007-11-05 | 2014-02-13 | 엘지이노텍 주식회사 | 발광장치 및 그 제조방법 |
KR100999760B1 (ko) | 2008-09-26 | 2010-12-08 | 엘지이노텍 주식회사 | 발광소자 패키지 및 그 제조방법 |
KR101114592B1 (ko) * | 2009-02-17 | 2012-03-09 | 엘지이노텍 주식회사 | 발광 디바이스 패키지 및 그 제조방법 |
KR101064098B1 (ko) * | 2009-02-23 | 2011-09-08 | 엘지이노텍 주식회사 | 발광소자 패키지 및 그 제조방법 |
KR20100097434A (ko) * | 2009-02-26 | 2010-09-03 | 삼성전자주식회사 | 색 온도를 조절할 수 있는 발광 패키지 및 그 제조 방법, 상기 발광 패키지의 색 온도 조절 방법 |
DE102009032486A1 (de) | 2009-07-09 | 2011-01-13 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauelement |
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Also Published As
Publication number | Publication date |
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US20070200131A1 (en) | 2007-08-30 |
US7738764B2 (en) | 2010-06-15 |
EP1826834A2 (en) | 2007-08-29 |
CN101030617A (zh) | 2007-09-05 |
EP1826834B1 (en) | 2020-05-06 |
KR100746783B1 (ko) | 2007-08-06 |
EP1826834A3 (en) | 2013-11-27 |
CN101030617B (zh) | 2011-05-18 |
JP2013034025A (ja) | 2013-02-14 |
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