JP2007227720A - 半導体装置とその製造方法 - Google Patents
半導体装置とその製造方法 Download PDFInfo
- Publication number
- JP2007227720A JP2007227720A JP2006048131A JP2006048131A JP2007227720A JP 2007227720 A JP2007227720 A JP 2007227720A JP 2006048131 A JP2006048131 A JP 2006048131A JP 2006048131 A JP2006048131 A JP 2006048131A JP 2007227720 A JP2007227720 A JP 2007227720A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- semiconductor device
- film
- wiring
- porous silica
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000011229 interlayer Substances 0.000 claims abstract description 53
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000004020 conductor Substances 0.000 claims abstract description 24
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000001257 hydrogen Substances 0.000 claims abstract description 22
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 22
- 238000012545 processing Methods 0.000 claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 126
- 239000000377 silicon dioxide Substances 0.000 claims description 57
- 239000000758 substrate Substances 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 11
- 230000001678 irradiating effect Effects 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 239000007858 starting material Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 27
- 230000008569 process Effects 0.000 abstract description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 51
- 229910052802 copper Inorganic materials 0.000 description 51
- 239000010949 copper Substances 0.000 description 51
- 210000002381 plasma Anatomy 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 11
- 238000009832 plasma treatment Methods 0.000 description 11
- 238000006243 chemical reaction Methods 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 238000004132 cross linking Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 230000002265 prevention Effects 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 238000011049 filling Methods 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910021426 porous silicon Inorganic materials 0.000 description 3
- 239000000523 sample Substances 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 101100434207 Arabidopsis thaliana ACT8 gene Proteins 0.000 description 1
- 229910008051 Si-OH Inorganic materials 0.000 description 1
- 229910020177 SiOF Inorganic materials 0.000 description 1
- 229910020175 SiOH Inorganic materials 0.000 description 1
- 229910006358 Si—OH Inorganic materials 0.000 description 1
- 238000004873 anchoring Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003197 catalytic effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 150000005622 tetraalkylammonium hydroxides Chemical class 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
- H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31695—Deposition of porous oxides or porous glassy oxides or oxide based porous glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
層間絶縁膜に用いる低誘電率膜の機械的強度を増加する。
【解決手段】
半導体装置の製造方法は、(a)複数の半導体素子を形成した半導体基板上方に下層絶縁膜を塗布する工程と、(b)前記下層絶縁膜を処理して機械的強度を増加させる工程と、(c)前記下層絶縁膜上方に、上層絶縁膜を塗布する工程と、(d)前記上層絶縁膜中に配線パターン、前記下層絶縁膜中にビア導電体を有する埋め込み配線を形成する工程と、を含む。機械的強度を増加させる処理は、紫外線照射、水素プラズマ処理を含む。
【選択図】 図1
Description
複数の半導体素子を有する半導体基板と、
前記半導体基板上方に形成された埋め込み配線であって、下層の導電体と接続するためのビア導電体と、ビア導電体上に接続された配線パターンとを有する埋め込み配線と、
前記埋め込み配線周囲を囲む層間絶縁膜であって、ビア導電体を囲む下層絶縁膜と配線パターンを囲む上層絶縁膜とを含み、前記下層絶縁膜と上層絶縁膜とは同一出発材料から形成され、前記下層絶縁膜は前記上層絶縁膜より高い機械的強度を有する層間絶縁膜と、
を有する半導体装置
が提供される。
(a)複数の半導体素子を形成した半導体基板上方に下層絶縁膜を塗布する工程と、
(b)前記下層絶縁膜を処理して機械的強度を増加させる工程と、
(c)前記下層絶縁膜上方に、上層絶縁膜を塗布する工程と、
(d)前記上層絶縁膜中に配線パターン、前記下層絶縁膜中にビア導電体を有する埋め込み配線を形成する工程と、
を含む半導体装置の製造方法
が提供される。
基板温度:350℃
UV光波長:200nm〜300nm、
照射エネルギ:220mW/cm2、
照射時間:600秒、
雰囲気:He、
圧力:1.2torr
であった。UV処理後、ヤング率、硬度、比誘電率を測定した。ヤングと硬度は、ナノインデンテーション法を用いて測定し、比誘電率は、水銀プローブを用いて測定した。ヤング率と硬度は膜の機械的強度を示す特性と考えられる。比誘電率は低誘電率の誘電体の本来の特徴であり、処理により余り増大しないことが望まれる。
ヤング率は10から12に増大し、硬度は0.9から1.1に増大した。層間クラックを防止するのに効果のある機械的強度の増加と考えられる。比誘電率は、2.2から2.3に増加した。
基板温度:400℃、
H2流量:4000sccm、
圧力:2.3torr、
投入電力(13.56MHz):100W(投入電力から反射電力を引いた実効値)、
プラズマ処理時間:80秒、
であった。
複数の半導体素子を有する半導体基板と、
前記半導体基板上方に形成された埋め込み配線であって、下層の導電体と接続するためのビア導電体と、ビア導電体上に接続された配線パターンとを有する埋め込み配線と、
前記埋め込み配線周囲を囲む層間絶縁膜であって、ビア導電体を囲む下層絶縁膜と配線パターンを囲む上層絶縁膜とを含み、前記下層絶縁膜と上層絶縁膜とは同一出発材料から形成され、前記下層絶縁膜は前記上層絶縁膜より高い機械的強度を有する層間絶縁膜と、
を有する半導体装置。
前記下層絶縁膜と前記上層絶縁膜との間に配置され、エッチストッパとして機能する材質の中層絶縁膜をさらに有する付記1記載の半導体装置。
前記中層絶縁膜は、SiCで形成された付記2記載の半導体装置。
前記下層絶縁膜と前記上層絶縁膜は、ポーラス絶縁膜で形成された付記1〜3のいずれか1項記載の半導体装置。
前記ポーラス絶縁膜がポーラスシリカで形成された付記5記載の半導体装置。
前記下層絶縁膜は前記上層絶縁膜より1GPa以上大きいヤング率を有する付記5記載の半導体装置。
前記埋め込み配線は、バリア層と銅層との積層で形成された付記1〜6のいずれか1項記載の半導体装置。
前記下層絶縁膜の下に形成された絶縁性銅拡散防止膜をさらに含む付記7記載の半導体装置。
(a)複数の半導体素子を形成した半導体基板上方に下層絶縁膜を塗布する工程と、
(b)前記下層絶縁膜を処理して機械的強度を増加させる工程と、
(c)前記下層絶縁膜上方に、上層絶縁膜を塗布する工程と、
(d)前記上層絶縁膜中に配線パターン、前記下層絶縁膜中にビア導電体を有する埋め込み配線を形成する工程と、
を含む半導体装置の製造方法。
前記工程(b)は、前記下層絶縁膜内で架橋反応を生じさせる付記9記載の半導体装置の製造方法。
前記工程(b)は、紫外光を照射することを含む付記9または10記載の半導体装置の製造方法。
前記紫外光は、波長200nm〜300nmの成分を含む付記11記載の半導体装置の製造方法。
前記工程(b)は、水素プラズマで処理することを含む付記9または10記載の半導体装置の製造方法。
前記工程(a)と(c)とは、同一ポーラス絶縁材料を塗布する付記9〜13のいずれか1項記載の半導体装置の製造方法。
前記ポーラス絶縁材料はポーラスシリカである付記14記載の半導体装置の製造方法。
前記工程(a)と(c)とは、塗布膜を次第に昇温する複数のベーク温度でベークする工程を含む付記14または15記載の半導体装置の製造方法。
前記工程(b)は、前記下層絶縁膜のベーク後、前記複数のベーク温度の内、最高のベーク温度以上に基板を加熱して行う付記16記載の半導体装置の製造方法。
(e)前記工程(b)と(c)の間に、エッチストッパとして機能する中層絶縁膜を前記下層絶縁膜の上に形成する工程をさらに含み、
前記工程(d)は、前記上層絶縁膜から前記下層絶縁膜まで貫通するビア孔を形成する工程と、前記中層絶縁膜をエッチストッパとして用いて少なくとも前記上層絶縁膜に配線パターン用トレンチを形成する工程と、を含む付記9〜17のいずれか1項記載の半導体装置の製造方法。
(f)前記工程(d)の後、前記埋め込み配線を覆って前記上層絶縁膜の上に絶縁性銅拡散防止膜を形成する工程をさらに含む付記9〜18のいずれか1項記載の半導体装置の製造方法。
2 ポーラスシリカ膜、
21 シリコン基板、
22 素子分離領域(STI)、
23 ゲート絶縁膜、
24 ゲート電極、
25 エクステンション領域、
26 サイドウォールスペーサ、
27 ソース/ドレイン領域、
28 下方層間絶縁膜、
29 導電性プラグ、
NW n型ウェル、
PW p型ウェル、
NMOS nチャネルMOSトランジスタ、
ES エッチストッパ膜、
PS ポーラスシリカ膜、
CL キャップ層、
DB 銅拡散防止膜、
CW 銅配線、
UV 紫外線、
PL プラズマ、
Claims (10)
- 複数の半導体素子を有する半導体基板と、
前記半導体基板上方に形成された埋め込み配線であって、下層の導電体と接続するためのビア導電体と、ビア導電体上に接続された配線パターンとを有する埋め込み配線と、
前記埋め込み配線周囲を囲む層間絶縁膜であって、ビア導電体を囲む下層絶縁膜と配線パターンを囲む上層絶縁膜とを含み、前記下層絶縁膜と上層絶縁膜とは同一出発材料から形成され、前記下層絶縁膜は前記上層絶縁膜より高い機械的強度を有する層間絶縁膜と、
を有する半導体装置。 - 前記下層絶縁膜と前記上層絶縁膜との間に配置され、エッチストッパとして機能する材質の中層絶縁膜をさらに有する請求項1記載の半導体装置。
- 前記中層絶縁膜は、SiCで形成された請求項2記載の半導体装置。
- 前記下層絶縁膜と前記上層絶縁膜は、ポーラスシリカで形成された請求項1〜3のいずれか1項記載の半導体装置。
- 前記下層絶縁膜は、前記上層絶縁膜より1GPa以上大きいヤング率を有する請求項5記載の半導体装置。
- (a)複数の半導体素子を形成した半導体基板上方に下層絶縁膜を塗布する工程と、
(b)前記下層絶縁膜を処理して機械的強度を増加させる工程と、
(c)前記下層絶縁膜上方に、上層絶縁膜を塗布する工程と、
(d)前記上層絶縁膜中に配線パターン、前記下層絶縁膜中にビア導電体を有する埋め込み配線を形成する工程と、
を含む半導体装置の製造方法。 - 前記工程(b)は、紫外光を照射することを含む請求項6記載の半導体装置の製造方法。
- 前記工程(b)は、水素プラズマで処理することを含む請求項6記載の半導体装置の製造方法。
- 前記工程(a)と(c)とは、同一ポーラスシリカ材料を塗布する請求項6〜8のいずれか1項記載の半導体装置の製造方法。
- (e)前記工程(b)と(c)の間に、エッチストッパとして機能する中層絶縁膜を前記下層絶縁膜の上に形成する工程をさらに含み、
前記工程(d)は、前記上層絶縁膜から前記下層絶縁膜まで貫通するビア孔を形成する工程と、前記中層絶縁膜をエッチストッパとして用いて少なくとも前記上層絶縁膜に配線パターン用トレンチを形成する工程と、を含む請求項6〜9のいずれか1項記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006048131A JP4666308B2 (ja) | 2006-02-24 | 2006-02-24 | 半導体装置の製造方法 |
US11/451,506 US20070200235A1 (en) | 2006-02-24 | 2006-06-13 | Semiconductor device having reinforced low-k insulating film and its manufacture method |
US12/774,302 US8772182B2 (en) | 2006-02-24 | 2010-05-05 | Semiconductor device having reinforced low-k insulating film and its manufacture method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006048131A JP4666308B2 (ja) | 2006-02-24 | 2006-02-24 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007227720A true JP2007227720A (ja) | 2007-09-06 |
JP4666308B2 JP4666308B2 (ja) | 2011-04-06 |
Family
ID=38443191
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006048131A Expired - Fee Related JP4666308B2 (ja) | 2006-02-24 | 2006-02-24 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US20070200235A1 (ja) |
JP (1) | JP4666308B2 (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011005624A (ja) * | 2009-05-26 | 2011-01-13 | Kobelco Kaken:Kk | 被覆ソーワイヤ |
JPWO2010125682A1 (ja) * | 2009-04-30 | 2012-10-25 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
WO2016151684A1 (ja) * | 2015-03-20 | 2016-09-29 | 株式会社日立国際電気 | 半導体装置の製造方法、記録媒体及び基板処理装置 |
WO2018055730A1 (ja) * | 2016-09-23 | 2018-03-29 | 株式会社日立国際電気 | 基板処理装置、半導体装置の製造方法および記録媒体 |
JP2020505766A (ja) * | 2017-01-17 | 2020-02-20 | ツェットエフ、フリードリッヒスハーフェン、アクチエンゲゼルシャフトZf Friedrichshafen Ag | 炭化珪素上に絶縁層を製造する方法 |
JP6918386B1 (ja) * | 2020-12-09 | 2021-08-11 | 株式会社アビット・テクノロジーズ | 絶縁膜の製造方法 |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7253125B1 (en) | 2004-04-16 | 2007-08-07 | Novellus Systems, Inc. | Method to improve mechanical strength of low-k dielectric film using modulated UV exposure |
US9659769B1 (en) | 2004-10-22 | 2017-05-23 | Novellus Systems, Inc. | Tensile dielectric films using UV curing |
US8454750B1 (en) | 2005-04-26 | 2013-06-04 | Novellus Systems, Inc. | Multi-station sequential curing of dielectric films |
US8889233B1 (en) | 2005-04-26 | 2014-11-18 | Novellus Systems, Inc. | Method for reducing stress in porous dielectric films |
US8980769B1 (en) | 2005-04-26 | 2015-03-17 | Novellus Systems, Inc. | Multi-station sequential curing of dielectric films |
US10037905B2 (en) * | 2009-11-12 | 2018-07-31 | Novellus Systems, Inc. | UV and reducing treatment for K recovery and surface clean in semiconductor processing |
US8850451B2 (en) * | 2006-12-12 | 2014-09-30 | International Business Machines Corporation | Subscribing for application messages in a multicast messaging environment |
US8211510B1 (en) | 2007-08-31 | 2012-07-03 | Novellus Systems, Inc. | Cascaded cure approach to fabricate highly tensile silicon nitride films |
US9050623B1 (en) | 2008-09-12 | 2015-06-09 | Novellus Systems, Inc. | Progressive UV cure |
JP2011082308A (ja) * | 2009-10-06 | 2011-04-21 | Panasonic Corp | 半導体装置の製造方法 |
JP5529571B2 (ja) * | 2010-02-08 | 2014-06-25 | キヤノン株式会社 | 画像符号化装置及びその制御方法 |
US8889544B2 (en) * | 2011-02-16 | 2014-11-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dielectric protection layer as a chemical-mechanical polishing stop layer |
KR20120118323A (ko) * | 2011-04-18 | 2012-10-26 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
US9054110B2 (en) * | 2011-08-05 | 2015-06-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-K dielectric layer and porogen |
US9330989B2 (en) | 2012-09-28 | 2016-05-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for chemical-mechanical planarization of a metal layer |
CN104347478B (zh) * | 2013-07-24 | 2017-05-17 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
US20150340322A1 (en) * | 2014-05-23 | 2015-11-26 | Rf Micro Devices, Inc. | Rf switch structure having reduced off-state capacitance |
US9847221B1 (en) | 2016-09-29 | 2017-12-19 | Lam Research Corporation | Low temperature formation of high quality silicon oxide films in semiconductor device manufacturing |
JP6877290B2 (ja) * | 2017-08-03 | 2021-05-26 | 東京エレクトロン株式会社 | 被処理体を処理する方法 |
WO2023141150A1 (en) * | 2022-01-18 | 2023-07-27 | Ditthavong, Steiner, & Mlotkowski | Aluminum-based coupling agents |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000216153A (ja) * | 1999-01-27 | 2000-08-04 | Matsushita Electric Ind Co Ltd | 多孔質膜の形成方法、配線構造体及びその形成方法 |
JP2004260076A (ja) * | 2003-02-27 | 2004-09-16 | Fujitsu Ltd | 被膜形成用塗布液、絶縁膜及びその製造方法ならびに半導体装置 |
JP2005203794A (ja) * | 2004-01-16 | 2005-07-28 | Internatl Business Mach Corp <Ibm> | 低誘電率および超低誘電率のSiCOH誘電体膜ならびにその形成方法 |
JP2005317835A (ja) * | 2004-04-30 | 2005-11-10 | Semiconductor Leading Edge Technologies Inc | 半導体装置 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6156671A (en) * | 1999-03-10 | 2000-12-05 | United Microelectronics Corp. | Method for improving characteristic of dielectric material |
JP3990920B2 (ja) | 2001-03-13 | 2007-10-17 | 東京エレクトロン株式会社 | 膜形成方法及び膜形成装置 |
US6984892B2 (en) * | 2001-03-28 | 2006-01-10 | Lam Research Corporation | Semiconductor structure implementing low-K dielectric materials and supporting stubs |
JP3886779B2 (ja) * | 2001-11-02 | 2007-02-28 | 富士通株式会社 | 絶縁膜形成用材料及び絶縁膜の形成方法 |
JP3974023B2 (ja) | 2002-06-27 | 2007-09-12 | 富士通株式会社 | 半導体装置の製造方法 |
JP4338495B2 (ja) * | 2002-10-30 | 2009-10-07 | 富士通マイクロエレクトロニクス株式会社 | シリコンオキシカーバイド、半導体装置、および半導体装置の製造方法 |
JP4454242B2 (ja) * | 2003-03-25 | 2010-04-21 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
JP4868742B2 (ja) * | 2003-05-21 | 2012-02-01 | 富士通株式会社 | 半導体装置 |
JP4057972B2 (ja) | 2003-07-25 | 2008-03-05 | 富士通株式会社 | 半導体装置の製造方法 |
TWI285938B (en) * | 2003-08-28 | 2007-08-21 | Fujitsu Ltd | Semiconductor device |
US6924242B2 (en) * | 2003-10-23 | 2005-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | SiOC properties and its uniformity in bulk for damascene applications |
JP2006128543A (ja) * | 2004-11-01 | 2006-05-18 | Nec Electronics Corp | 電子デバイスの製造方法 |
CN1787186A (zh) * | 2004-12-09 | 2006-06-14 | 富士通株式会社 | 半导体器件制造方法 |
JP2006216746A (ja) * | 2005-02-03 | 2006-08-17 | Sony Corp | 半導体装置 |
-
2006
- 2006-02-24 JP JP2006048131A patent/JP4666308B2/ja not_active Expired - Fee Related
- 2006-06-13 US US11/451,506 patent/US20070200235A1/en not_active Abandoned
-
2010
- 2010-05-05 US US12/774,302 patent/US8772182B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000216153A (ja) * | 1999-01-27 | 2000-08-04 | Matsushita Electric Ind Co Ltd | 多孔質膜の形成方法、配線構造体及びその形成方法 |
JP2004260076A (ja) * | 2003-02-27 | 2004-09-16 | Fujitsu Ltd | 被膜形成用塗布液、絶縁膜及びその製造方法ならびに半導体装置 |
JP2005203794A (ja) * | 2004-01-16 | 2005-07-28 | Internatl Business Mach Corp <Ibm> | 低誘電率および超低誘電率のSiCOH誘電体膜ならびにその形成方法 |
JP2005317835A (ja) * | 2004-04-30 | 2005-11-10 | Semiconductor Leading Edge Technologies Inc | 半導体装置 |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2010125682A1 (ja) * | 2009-04-30 | 2012-10-25 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP5559775B2 (ja) * | 2009-04-30 | 2014-07-23 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2011005624A (ja) * | 2009-05-26 | 2011-01-13 | Kobelco Kaken:Kk | 被覆ソーワイヤ |
WO2016151684A1 (ja) * | 2015-03-20 | 2016-09-29 | 株式会社日立国際電気 | 半導体装置の製造方法、記録媒体及び基板処理装置 |
WO2018055730A1 (ja) * | 2016-09-23 | 2018-03-29 | 株式会社日立国際電気 | 基板処理装置、半導体装置の製造方法および記録媒体 |
JP2020505766A (ja) * | 2017-01-17 | 2020-02-20 | ツェットエフ、フリードリッヒスハーフェン、アクチエンゲゼルシャフトZf Friedrichshafen Ag | 炭化珪素上に絶縁層を製造する方法 |
JP6918386B1 (ja) * | 2020-12-09 | 2021-08-11 | 株式会社アビット・テクノロジーズ | 絶縁膜の製造方法 |
WO2022124199A1 (ja) * | 2020-12-09 | 2022-06-16 | 株式会社アビット・テクノロジーズ | 絶縁膜の製造方法 |
JP2022091642A (ja) * | 2020-12-09 | 2022-06-21 | 株式会社アビット・テクノロジーズ | 絶縁膜の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20100216303A1 (en) | 2010-08-26 |
US20070200235A1 (en) | 2007-08-30 |
US8772182B2 (en) | 2014-07-08 |
JP4666308B2 (ja) | 2011-04-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4666308B2 (ja) | 半導体装置の製造方法 | |
US7741224B2 (en) | Plasma treatment and repair processes for reducing sidewall damage in low-k dielectrics | |
US8716148B2 (en) | Semiconductor device manufacturing method | |
JP2006108664A (ja) | 段差被覆性を向上させた半導体ウェハー及びその製造方法 | |
JP2003332418A (ja) | 半導体装置及びその製造方法 | |
JP2004088047A (ja) | 半導体装置の製造方法 | |
KR100382376B1 (ko) | 반도체 장치 및 그의 제조방법 | |
JP2011009636A (ja) | ビアホールの形成方法 | |
JP4567587B2 (ja) | 半導体装置の製造方法 | |
TW406333B (en) | Semiconductor device and method for manufacturing same | |
JP2008060498A (ja) | 半導体装置および半導体装置の製造方法 | |
JP2003273100A (ja) | 半導体装置及びその製造方法 | |
KR101459222B1 (ko) | 반도체 장치와 그 제조 방법 | |
JP2006351732A (ja) | 半導体装置の製造方法 | |
JP2007220738A (ja) | 半導体装置の製造方法 | |
JP5396837B2 (ja) | 半導体装置の製造方法 | |
JP2008166414A (ja) | 半導体装置及びその製造方法 | |
JP2011134771A (ja) | 半導体装置及びその製造方法 | |
WO2009153857A1 (ja) | 半導体装置及びその製造方法 | |
JP2006319116A (ja) | 半導体装置およびその製造方法 | |
JP4927343B2 (ja) | 半導体チップおよびその製造方法 | |
JP4338748B2 (ja) | 半導体装置の製造方法 | |
KR100315455B1 (ko) | 반도체 소자 및 그 제조 방법 | |
JP2005109343A (ja) | 半導体装置の製造方法 | |
JP2009064858A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20080729 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20081015 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100420 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100422 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100614 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101005 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101206 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20101228 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110104 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140121 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 Ref document number: 4666308 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |