JP2007220809A - 半導体装置及びその製造方法 - Google Patents
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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Abstract
【解決手段】複数面にチャネルを有するマルチゲートMISトランジスタを有する半導体装置において、絶縁膜上12に一方向に沿って島状に形成され、一方向に沿った複数の側面を有し、該側面のうち隣接する側面の成す角が全て90度よりも大きく、一方向と垂直な断面が上下及び左右に対称性を有する半導体層21と、側面のチャネルとすべき領域上に形成されたゲート絶縁膜と、側面のチャネルとすべき領域上にゲート絶縁膜を介して形成されたゲート電極24と、半導体層21に接して形成されたソース・ドレイン電極27とを備えた。
【選択図】図2
Description
図1〜図3は、本発明の第1の実施形態に係わるマルチゲートMISFETの概略構成を説明するためのもので、図1は平面図、図2は鳥瞰図、図3(a)は図1のA−A’断面図、図3(b)は図1のB−B’断面図である。
図10及び図11は、本発明の第2の実施形態に係わるマルチゲートMISFETの概略構成を説明するためのもので、図10は平面図、図11(a)は図10のA−A’断面図、図11(b)は図10のC−C’断面図である。なお、図1乃至図3と同一部分には同一符号を付して、その詳しい説明は省略する。
なお、本発明は上述した各実施形態に限定されるものではない。
12…Si酸化膜(埋め込み絶縁膜)
13…SiGe層
15…Si層
16…Ge層
17…Si層
18…Si窒化膜(マスク材)
21…Ge層(半導体層)
22…Si酸化膜(酸化濃縮絶縁膜)
23…ゲート絶縁膜
24…ゲート電極
25…エクステンション領域
26…ゲート側壁絶縁膜
27…ソース・ドレイン電極
31…ゲート側壁絶縁膜
32…選択成長Si層
33…選択成長SiGe層
Claims (20)
- 絶縁膜上に一方向に沿って島状に形成され、前記一方向に沿った複数の側面を有し、該側面のうち隣接する側面の成す角が全て90度よりも大きく、前記一方向と垂直な断面が上下及び左右に対称性を有する半導体層と、
前記側面のチャネルとすべき領域上に形成されたゲート絶縁膜と、
前記側面のチャネルとすべき領域上に前記ゲート絶縁膜を介して形成されたゲート電極と、
前記半導体層に接して形成されたソース・ドレイン電極と、
を具備したことを特徴とする半導体装置。 - 前記絶縁膜の表面上の一部であって、前記半導体層のチャネルとすべき領域に対向する領域が除去され、前記ゲート絶縁膜及びゲート電極は、前記半導体層の一部を囲むように前記側面の全てに形成されていることを特徴とする請求項1記載の半導体装置。
- 前記半導体層は、Geであることを特徴とする請求項1又は2記載の半導体装置。
- 前記半導体層のチャネルはGeであり、前記ソース・ドレイン電極とチャネルとの間に、Si又はSiGeのエクステンション層が形成されていることを特徴とする請求項1又は2記載の半導体装置。
- 前記半導体層のチャネルはGeであり、前記ソース・ドレイン電極は、ジャーマナイド,ジャーマノシリサイド,又はシリサイドであり、前記チャネルに接して設けられていることを特徴とする請求項1又は2記載の半導体装置。
- 前記絶縁膜は面方位が(100)の単結晶半導体基板上に形成され、前記半導体層は前記基板の<110>軸方向に沿って配置されていることを特徴とする請求項1〜5の何れかに記載の半導体装置。
- 前記側面のうちの4つが、(111)面であることを特徴とする請求項1〜6の何れかに記載の半導体装置。
- 前記半導体層の前記一方向に垂直な断面は、六角形であることを特徴とする請求項1〜7の何れかに記載の半導体装置。
- 前記ゲート電極は、前記一方向と交差する方向に沿って前記絶縁膜上に配置されていることを特徴とする請求項1〜8の何れかに記載の半導体装置。
- 面方位が(100)の基板と、
前記基板上に形成された埋め込み絶縁膜と、
前記埋め込み絶縁膜上に、前記基板の<110>軸方向に沿って島状に形成され、前記<110>軸方向に沿った複数の側面を有し、該側面のうち隣接する側面の成す角が全て90度より大きく、前記<110>軸方向と垂直な断面が上下及び左右に対称性を有する六角形である半導体層と、
前記半導体層の一部を囲むように、前記<110>軸方向に沿った側面上に形成されたゲート絶縁膜と、
前記半導体層の一部を囲むように、前記ゲート絶縁膜上に形成されたゲート電極と、
前記半導体層に接して形成され、前記半導体層の前記ゲート電極で囲まれたチャネル領域を挟んで形成されたソース・ドレイン電極と、
を具備したことを特徴とする半導体装置。 - 前記絶縁膜の表面上の一部であって、前記半導体層のチャネルとすべき領域に対向する領域が除去され、前記ゲート絶縁膜及びゲート電極は、前記半導体層の一部を囲むように該半導体層の前記<110>軸方向に沿った側面の全てに形成されていることを特徴とする請求項10記載のMISトランジスタ。
- 前記半導体層は、Geであることを特徴とする請求項10又は11記載の半導体装置。
- 前記半導体層のチャネルはGeであり、前記ソース・ドレイン電極とチャネルとの間に、Si又はSiGeのエクステンション層が形成されていることを特徴とする請求項10又は11記載の半導体装置。
- 前記半導体層のチャネルはGeであり、前記ソース・ドレイン電極は、ジャーマナイド、ジャーマノシリサイド、又はシリサイドであり、前記チャネル領域に接して設けられていることを特徴とする請求項10又は11記載の半導体装置。
- 前記半導体層の前記<110>軸方向に沿った側面のうちの4つが、(111)面であることを特徴とする請求項10〜14の何れかに記載の半導体装置。
- 前記ゲート電極は、前記<110>軸方向と交差する方向に沿って前記絶縁膜上に配置されていることを特徴とする請求項10〜15の何れかに記載の半導体装置。
- 絶縁膜上にSiGe層を形成する工程と、
前記SiGe層をMISトランジスタ形成領域に合わせて選択的にエッチングすることにより、該SiGe層を一方向に沿って島状に残す工程と、
前記SiGe層に酸化処理を施すことにより、前記一方向に沿った複数の側面を有し、該側面のうち隣接する側面の成す角が全て90度よりも大きく、前記一方向と垂直な断面が上下及び左右に対称性を有するGe層を形成する工程と、
前記Ge層の側面のチャネルとすべき領域上に、ゲート絶縁膜を介してゲート電極を形成する工程と、
前記ゲート電極をマスクに用いて、前記Ge層に接してソース・ドレイン電極を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記絶縁膜は、面方位が(100)の単結晶半導体基板上に形成され、前記SiGe層は、前記基板の<110>軸方向に沿って島状に残されることを特徴とする請求項17記載の半導体装置の製造方法。
- 前記Ge層の前記<110>軸方向に垂直な断面は六角形であり、前記Ge層の前記<110>軸方向に沿った側面のうちの4つは(111)面となっていることを特徴とする請求項18記載の半導体装置の製造方法。
- 前記ソース・ドレイン電極を形成する工程の前に、前記ゲート電極をマスクに用いて前記チャネルに隣接する領域に、Si又はSiGeのエピタキシャル成長と熱処理によりSiGe層を形成することを特徴とする請求項17〜19の何れかに記載の半導体装置の製造方法。
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JP2006038252A JP4635897B2 (ja) | 2006-02-15 | 2006-02-15 | 半導体装置及びその製造方法 |
US11/705,450 US7622773B2 (en) | 2006-02-15 | 2007-02-13 | Semiconductor device including multi-gate metal-insulator-semiconductor (MIS) transistor |
DE102007007261A DE102007007261B4 (de) | 2006-02-15 | 2007-02-14 | Halbleitervorrichtung und Verfahren zum Herstellen derselben |
KR1020070015185A KR100819643B1 (ko) | 2006-02-15 | 2007-02-14 | 반도체 장치 및 이를 제조하는 방법 |
CNB2007100879678A CN100517759C (zh) | 2006-02-15 | 2007-02-15 | 半导体器件及其制造方法 |
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Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008211052A (ja) * | 2007-02-27 | 2008-09-11 | Toshiba Corp | 相補型半導体装置 |
JP2010177451A (ja) * | 2009-01-29 | 2010-08-12 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2010251459A (ja) * | 2009-04-14 | 2010-11-04 | Hitachi Ltd | 半導体装置およびその製造方法 |
WO2010131312A1 (ja) * | 2009-05-13 | 2010-11-18 | パナソニック株式会社 | 半導体装置及びその製造方法 |
JP2011507231A (ja) * | 2007-12-07 | 2011-03-03 | エージェンシー フォー サイエンス,テクノロジー アンド リサーチ | シリコン−ゲルマニウムナノワイヤ構造およびその形成方法 |
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KR100819643B1 (ko) | 2008-04-04 |
DE102007007261B4 (de) | 2010-03-18 |
US20070241399A1 (en) | 2007-10-18 |
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US7622773B2 (en) | 2009-11-24 |
CN101022132A (zh) | 2007-08-22 |
CN100517759C (zh) | 2009-07-22 |
KR20070082528A (ko) | 2007-08-21 |
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