JP2007110162A - ピン止め光ダイオードと集積されたアクティブ画素センサー - Google Patents

ピン止め光ダイオードと集積されたアクティブ画素センサー Download PDF

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JP2007110162A
JP2007110162A JP2007002103A JP2007002103A JP2007110162A JP 2007110162 A JP2007110162 A JP 2007110162A JP 2007002103 A JP2007002103 A JP 2007002103A JP 2007002103 A JP2007002103 A JP 2007002103A JP 2007110162 A JP2007110162 A JP 2007110162A
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active pixel
drain
pinned photodiode
conductivity type
transfer gate
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Paul P Lee
ピー リー ポール
Robert M Guidash
エム ガイダッシュ ロバート
Teh-Hsuang Lee
リー テー−スアン
Eric Gordon Stevens
ゴードン スティーブンス エリック
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Eastman Kodak Co
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
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    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
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    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14645—Colour imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H01L27/14831—Area CCD imagers

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Abstract

【課題】
ピン止め光ダイオードがアクティブ画素センサーの画像検知要素内に集積される２つの技術（ＣＭＯＳ及びＣＣＤ）の最適化を達成する。
【解決手段】
ピン止め光ダイオードはアクティブ画素アーキテクチャー内のプロセス段階で作られる。アクティブ画素ピン止め光ダイオード内に集積された電荷は転送ゲートにより電荷検知ノード内に転送される。浮遊拡散はそれぞれの画素のアドレッシング能力を提供するＣＭＯＳ回路に結合される。代替的に埋込チャネル光コンデンサがピン止め光ダイオードの代わりに用いられる。
【選択図】図２

Description

本発明は画像検出デバイスに関し、より詳細にはＣＭＯＳ技術への電荷結合素子（ＣＣＤ）技術の集積に関する。
アクティブ画素センサーはトランジスタのような能動デバイス内で電子画像センサーと称される。アクティブ画素センサーは同一チップ上に信号処理及び決定作成回路を容易に収容可能であるという利点を有する。従来技術のアクティブ画素センサーは典型的には能動画像検知要素としてポリシリコン光コンデンサ又は光ゲートを用いる。これらの従来技術のアクティブ画素センサーは青の応答が悪く、高い暗電流があり、画像ラグを被る。
ピン止め（pinned）光ダイオードは電荷結合デバイス内で用いられ、青い光、暗電流密度、画像ラグに対するカラー応答の領域で利点を有する。この理由でピン止め光ダイオードは通常、高性能画像センサーに関連する。これまでピン止め光ダイオードは典型的には電荷結合デバイス用の光素子として用いられてきた。そのようなピン止め光ダイオードの使用の例は非特許文献１に記載されている。しかしながら電荷結合デバイス技術はデバイス上に配置されうる回路要素の量及び型において欠如している。
上記より、改善された回路素子を提供しうる半導体技術で用いられ得るピン止め光ダイオードに対する半導体技術でニーズがなお存在することは明白である。
Ｂｕｒｋｅｙ等、「ＴＨＥ ＰＩＮＮＥＤ ＰＨＯＴＯＤＩＯＤＥ ＦＯＲ ＡＮ ＩＮＴＥＲＬＩＮＥ−ＴＲＡＮＳＦＥＲ ＣＣＤ ＩＭＡＧＥ ＳＥＮＳＯＲ」、ＩＥＤＭ８４、１９８４年，ｐ．２８−３１
本発明は２つの技術（ＣＭＯＳ及びＣＣＤ）の最適化を提供することにより従来技術の欠点を克服するものであり、ピン止め光ダイオードがアクティブ画素センサーの画像検知要素内に集積される。
ピン止め光ダイオードは通常、ＣＣＤ技術で製造される。ＣＣＤ技術からの適切なプロセス段階を導入することによりピン止め光ダイオードはアクティブ画素アーキテクチャー内に集積されうる。アクティブ画素センサーの青応答と暗電流限界を改善するために、新たなＣＭＯＳイメージャーが混合プロセス技術を用いてピン止め光ダイオードと集積される。この技術は両方の技術から最高の特徴を提供するためにＣＭＯＳ及びＣＣＤプロセスを結合する。
電荷結合デバイス（ＣＣＤ）の技術的特徴は両方の技術を用いるピン止め光ダイオードを有するアクティブ画素センサーを製造するためにＣＭＯＳ型の半導体に用いられうる。
図１は、ＣＭＯＳに基づく信号処理システム内で用いられる本発明のアクティブ画素センサーに基づくピン止め光ダイオードを示している。アクティブ画素センサーの青応答を改善し、ラグを減少し、暗電流特性を最小化するために新たなＣＭＯＳイメージャーは混合されたプロセス技術を用いてピン止め光ダイオード１２に集積される。これは両方の技術から最良の特徴を有するセンサーを提供するためにｎウエルＣＭＯＳ技術及びピン止め光ダイオードＣＣＤプロセスを結合する。ｎ×ｍのピン止め光ダイオードアクティブ画素センサーは設計され、製造され、ここでｎとｍはセンサーの端での画素の数である。本発明はＣＭＯＳアクティブセンサーに画像センサーＣＣＤ技術を組み込むことによって利点を有する。
図２は本発明のセンサーを製造するのに用いられるデバイスの断面図である。これは混合プロセス技術を用いるピン止め光ダイオード１２（ＰＰＤ）デバイスとの、相補型金属酸化物半導体（ＣＭＯＳ）内で典型的に製造されるアクティブ画素センサー（ＡＰＳ）アーキテクチャーの集積の結果である。この新たな技術はＣＭＯＳと高性能電荷結合素子（ＣＣＤ）モジュールとの混合を可能にする。ＰＰＤ１２は転送１４、浮遊拡散を介する読み取り１６、リセット１８機能に対する能動デバイスを含む各画素を有するＸＹアドレス可能な領域配列での光動作素子となる。ｎウエルＣＭＯＳ技術が両方の技術からの最良の特徴を提供するためにＣＣＤプロセスと結合されたものである。従来のＡＰＳでポリシリコン光コンデンサ又は光ゲートをピン止め光ダイオード１２で置き換えることにより悪い青の応答、画像ラグ、高い暗電流の欠点は最小化される。
集積モードでバイアスされた埋込チャネル光コンデンサ（図示せず）はＣＭＯＳ技術が有する暗電流での制限を有さない。埋込チャネル光コンデンサはＰＰＤに対する本質的に等価な暗電流特性を有する。青応答問題は透明ゲート材料を用いることによりまた除去されうる。そのような材料の例はインジウム錫酸化物（ＩＴＯ）である。故に両方を用いて透明ゲート電極を有する埋込チャネル光コンデンサはＰＰＤにより達成されたそれらと同様の青応答、暗電流に対する優れた特性を提供する。透明電極を有する埋込チャネル光コンデンサとＰＰＤの両方はＣＣＤ技術に典型的に関連するデバイスである。本発明はＣＭＯＳプロセス能力にＣＣＤ技術からのこれらのデバイスを導入する。埋込チャネル光コンデンサを用いるアクティブ画素センサーの構成は、ＰＰＤ実施例の転送ゲートと非常に類似に構造化された光コンデンサを有する図２のＰＰＤに類似である。光コンデンサ実施例の転送ゲートは、ＰＰＤ実施例により用いられる転送ゲートの埋込チャネルをなくしたものである。
プロセスの統合は従来技術の各プロセスによりそれぞれ得られるものに匹敵する性能を有する２つの技術の混合である。これは線形画像センサー及びＣＭＯＳテスト回路で示されている。
混合されたプロセス技術ではプロセスフローの概略は図３から９に示される。 図３は本発明の制御回路の一部分を形成するＰＭＯＳトランジスタを含むために用いられるｎウエル４０を形成するために本発明で用いられるパターン化及びイオンインプラントを示す。
図４、５はエピタキシャル層と共に又はなしで、ウエル構造と共に又はなしでシリコン層２上に形成される絶縁デバイスとして用いられる絶縁酸化物／フィールド酸化物のパターン化及び成長を示す。
図６は本発明の画素の転送ゲート１４を形成するために用いられるｎ型埋込チャネル１５のパターン化及びイオンインプラントを示す。埋込チャネル１５のインプラントの後にフォトレジスト層５２は除去され、ポリシリコン層２６は基板上に形成される。ポリシリコン２６は局部相互接続及びトランジスタのゲートを形成するために用いられる。ＰＭＯＳ及びＮＭＯＳトランジスタの両方はこのポリシリコン３６により形成されたそれらのゲートを有する。
図７はフォトレジスト５４でのポリシリコン２６のパターン化、及びソース及びドレイン領域を形成するためのＮ＋ドーパントのインプラントを示す。これは残余のポリシリコンに自己整合されるソース及びドレイン領域を生ずる。これは好ましい実施例でのＮＭＯＳトランジスタを形成する。
図８は２つの付加的なインプラントに対するフォトレジスト５６領域でパターン化されることによるＰＰＤの構造を示す。第一のインプラントは、上記のソース及びドレインインプラントにより先に用いられたのより深くＮ＋不純物をインプラントすることにより、フォトダイオードを作るためのものである。より深いインプラントはそれと共に入射光キャリアに対する収集路を増加するために光応答の実質的な増加を得る。それからピン止め層２２インプラントは、フォトダイオード３２の表面付近に残る高ドーズの低エネルギーＰ＋ドーパントを用いて作られる。
図９は、フォトレジスト５８でのパターン化及びそれに続くＰＭＯＳトランジスタのソース／ドレインのイオンインプラントを示す。ＮＭＯＳトランジスタに関してのように、ＰＭＯＳトランジスタに対するソース／ドレインインプラントは選択されたポリシリコンで自己整合される。Ｐ＋インプラントはＰＭＯＳトランジスタを構成するよう用いられる。
デバイスは適切な平坦化及び金属被覆化段階により完成される。
本発明のイメージャーアーキテクチャーはそれらの全体的な性能を増加するために従来技術のデバイスの信号処理回路に用いられ得る。その例は、ジェット推進研究所で実施された初期の設計への本発明の導入である。この初期の設計はＩＥＥＥ Ｔｒａｎｓａｃｔｉｏｎｓ ｏｎ Ｅｌｅｃｔｒｏｎ Ｄｅｖｉｃｅｓ，Ｖｏｌ．４１，Ｎｏ．３、１９９４年３月（以下にＪＰＬと称する）に記載される。アクティブ画素センサー内に集積された光ゲートを記載する一方でＪＰＬにより開示されたデバイスは満足できる青波長のカラー応答を有するセンサーを提供しない。付加的にＪＰＬデバイスは充分低い暗電流ノイズ特性を持たない。本発明は従来ＣＭＯＳ技術で応用されなかったピン止め光ダイオード技術を導入することによりこれらの欠点を克服する。これは青い光に対する優れた応答と改善された暗電流ノイズ特性とを有する画像センサーを提供する。
発明者に知られているベストモードが好ましい実施例により開示されてきた一方で、種々の改良は当業者に対して明らかである。これらの明らかな改良は請求項の範囲であると考えるべきものである。
本発明のアクティブ画素センサーに基づくピン止め光ダイオードを示す。 本発明のセンサーを製造するのに用いられるデバイスの断面図である。 図２のデバイスを製造するのに用いられるプロセス段階を示す図である。 図２のデバイスを製造するのに用いられるプロセス段階を示す図である。 図２のデバイスを製造するのに用いられるプロセス段階を示す図である。 図２のデバイスを製造するのに用いられるプロセス段階を示す図である。 図２のデバイスを製造するのに用いられるプロセス段階を示す図である。 図２のデバイスを製造するのに用いられるプロセス段階を示す図である。 図２のデバイスを製造するのに用いられるプロセス段階を示す図である。
符号の説明
２ 基板
４ エピタキシャル層
１０ 画素
１２ フォトダイオード
１４ 転送
１５ チャネル
１６ 拡散
１８ リセット
２２ ピン止め層
２６ ポリシリコン
３２ フォトダイオード
４０ ｎウエル
５２ フォトレジスト層
５４、５６、５８ フォトレジスト

Claims (1)

  1. 少なくとも１つのピン止め光ダイオードを有するアクティブ画素センサーであって：
    少なくとも１つの導電層を含む一連のマスク層、及び少なくとも１つの電荷検知手段を有する第１導電型の半導体材料；
    少なくとも１つの転送ゲート、及び前記導電層上の一連の局部相互接続；
    第１導電型と逆の第２導電型の第１の組のインプラント層であり、第１の組のトランジスタのソース及びドレインとして機能し、各転送ゲートの少なくとも１つのドレインを含み、該ドレインが前記転送ゲートに自己整合されている第１の組のインプラント層；
    基板内にインプラントされた前記ソースの１つから形成され、前記転送ゲートに隣接する、光ダイオードを作り出す少なくとも１つの画像検知領域であり、第１導電型の材料を有するピン止め層を該光ダイオードの頂部に具備する画像検知領域；
    画像センサーを作り出すのに使用されずに残された第１の組のトランジスタの何れかに連結されて形成され、前記局部相互接続によって前記画像センサーに結合されたＣＭＯＳ制御回路を形成する第２の組のトランジスタに対して、そのソース及びドレインとして用いられる第１導電型の第２の組のインプラント層；及び
    第１及び第２の組のソース及びドレイン上の所定のコンタクトの組；
    を有するアクティブ画素センサー。
JP2007002103A 1995-04-13 2007-01-10 ピン止め光ダイオードと集積されたアクティブ画素センサー Pending JP2007110162A (ja)

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US08/421,173 US5625210A (en) 1995-04-13 1995-04-13 Active pixel sensor integrated with a pinned photodiode

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DE69637103D1 (de) 2007-07-12
US5904493A (en) 1999-05-18
US6100551A (en) 2000-08-08
EP0738010A3 (en) 1998-10-14
US6027955A (en) 2000-02-22
US5841159A (en) 1998-11-24
EP0738010B1 (en) 2007-05-30
DE69637103T2 (de) 2008-01-24
US5625210A (en) 1997-04-29
JPH08335688A (ja) 1996-12-17

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