JP2007067107A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP2007067107A JP2007067107A JP2005250046A JP2005250046A JP2007067107A JP 2007067107 A JP2007067107 A JP 2007067107A JP 2005250046 A JP2005250046 A JP 2005250046A JP 2005250046 A JP2005250046 A JP 2005250046A JP 2007067107 A JP2007067107 A JP 2007067107A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- wiring
- manufacturing
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53233—Copper alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical Vapour Deposition (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
【解決手段】 (a1)半導体基板の上に形成された絶縁膜に凹部を形成する。(a2)凹部の内面、及び絶縁膜の上面を覆うように、CVD法により、Mnからなる第1の膜を形成する。(a3)第1の膜の上に、Cuを主成分とする導電材料を堆積させるとともに、凹部内に該導電材料を充填する。(a4)半導体基板をアニールする。
【選択図】 図3−2
Description
W.A.Lanford et al.,"Low-temperature passivation of copper by doping with Al or Mg", ThinSolid Films, 262(1995) p.234-241 T. Usui et al., "LowResistive and Highly Reliable Cu Dual-Damascene Interconnect Technology UsingSelf-Formed MnSixOy Barrier Layer", IITC 2005, Session 9.2
保護膜6の上に、低誘電率絶縁材料からなる層間絶縁膜10が形成されている。層間絶縁膜10に、その底面まで達し、導電プラグ5Bの上方を通過する配線溝が形成されている。この配線溝内に第1層目の銅配線11が充填されている。銅配線11は、導電プラグ5Bに接続される。
配線層の層間絶縁膜23に配線溝25が形成され、ビア層の層間絶縁膜21にビアホール24が形成されている。配線溝25はエッチングストッパ膜22の上面まで達する。ビアホール24は、配線溝25の底面に開口するとともに、キャップ膜20を貫通して下層の配線11の上面まで達する。
図2に、第1〜第9の実施例による方法で配線または導電部材を形成するときの下地膜及び導電部材の材料及び堆積方法の一覧を示す。一覧表中のハイフンの左側に記載された「CVD」、「スパッタ」及び「EP」は、それぞれCVD法、スパッタリング法、及び電解めっき法により膜を形成することを意味する。ハイフンの右側に記載された「Mn」、「Cu」、及び「CuMn」は、それぞれ堆積された膜の材料がMn、Cu、及びCuMn合金であることを意味する。
図5Aに示した状態は、第1の実施例による製造方法の説明で参照した図3Bの状態と同一である。
次に、図6A〜図6Cを参照して、第7の実施例による半導体装置の製造方法について説明する。
図6Bに示すように、配線層の層間絶縁膜23の上面、配線溝25の内面、及びビアホール24の内面上に、CVD法を用いて、Mnからなる厚さ2nmの第1の膜32を形成する。第1の膜32は、図3Cに示した第1の実施例における第1の膜32と同じ方法で形成される。
次に、第8の実施例による半導体装置の製造方法について説明する。上述の第7の実施例では、図6Bに示した第1の膜32をMnで形成したが、第8の実施例では、CuとMnとを含む合金で形成する。第1の膜32の成膜は、第4の実施例による第1の膜32と同様のCVD法を用いて行う。
次に、図7A及び図7Bを参照して、第9の実施例による半導体装置の製造方法について説明する。
図7Bに示すように、CVD法によりCuとMnとを含む合金を堆積させて配線溝25及びビアホール24内にCuMn合金を充填する。これによりCuMn合金からなる導電部材34が形成される。すなわち、第9の実施例は、第8の実施例の図6Bに示した第1の膜32の形成を、ビアホール24及び配線溝25内がCuMn合金で完全に充填されるまでそのまま継続して行う方法と同一であると考えることができる。なお、CVD法のみを用いて配線溝25内をCuMn合金で完全に充填することが困難である場合には、CVD法によりCuMn合金を堆積させた後、補完的にCuを電解めっきしてもよい。その後の工程は、第1の実施例の図3Dの状態以降の工程と同一である。
以上実施例に沿って本発明を説明したが、本発明はこれらに制限されるものではない。例えば、種々の変更、改良、組み合わせ等が可能なことは当業者に自明であろう。
(付記1)
(a1)半導体基板の上に形成された絶縁膜に凹部を形成する工程と、
(a2)前記凹部の内面、及び前記絶縁膜の上面を覆うように、CVD法により、Mnからなる第1の膜を形成する工程と、
(a3)前記第1の膜の上に、Cuを主成分とする導電材料を堆積させるとともに、前記凹部内に該導電材料を充填する工程と
(a4)前記半導体基板をアニールする工程と
を有する半導体装置の製造方法。
前記工程a3が、
前記第1の膜の表面を覆うように、CVD法またはスパッタリング法により、Cuからなる第2の膜を形成する工程と、
前記第2の膜を電極として、Cuを主成分とする導電材料を電解めっきする工程と
を含む付記1に記載の半導体装置の製造方法。
前記工程a3において、Cuを主成分とする導電材料をCVD法により堆積させることにより、前記凹部内に該導電材料を充填する付記1に記載の半導体装置の製造方法。
(b1)半導体基板の上に形成された絶縁膜に凹部を形成する工程と、
(b2)前記凹部の内面、及び前記絶縁膜の上面を覆うように、CVD法により、Cu及びMnを含む第1の膜を形成する工程と、
(b3)前記第1の膜の上に、Cuを主成分とする導電材料を堆積させるとともに、前記凹部内に該導電材料を充填する工程と
(b4)前記半導体基板をアニールする工程と
を有する半導体装置の製造方法。
前記工程b2において、Cu原料とMn原料とを同時に供給しながら前記第1の膜を形成する付記4に記載の半導体装置の製造方法。
前記工程b2において、Cu原料とMn原料とを交互に供給しながら前記第1の膜を形成する付記4に記載の半導体装置の製造方法。
前記工程b3において、前記第1の膜を電極として、前記導電材料を電解めっきすることにより、前記凹部内に該導電材料を充填する付記4〜6のいずれかに記載の半導体装置の製造方法。
前記工程b3において、前記工程b2でのCVD法による前記第1の膜の堆積をそのまま継続することにより、前記凹部内にCu及びMnを含む該導電材料を充填する付記4に記載の半導体装置の製造方法。
前記工程b3が、
前記第1の膜の上に、スパッタリング法により、Cuからなる第2の膜を形成する工程と、
前記第2の膜を電極として、Cuを主成分とする導電材料を電解めっきする工程と
を含む付記4に記載の半導体装置の製造方法。
(c1)半導体基板の上に形成された絶縁膜に凹部を形成する工程と、
(c2)前記凹部の内面、及び前記絶縁膜の上面を覆うように、スパッタリング法によりCu及びMnを含む第1の膜を形成する工程と、
(c3)前記第1の膜の上に、CVD法により、Cuを主成分とする導電材料からなる第2の膜を形成する工程と、
(c4)前記凹部内に、Cuを主成分とする導電材料を充填する工程と
を有する半導体装置の製造方法。
前記工程c4において、前記第2の膜を電極として、前記導電材料を電解めっきする付記10に記載の半導体装置の製造方法。
半導体基板の上に、Mn原料とCu原料とを同時に供給しながら、CVD法により、CuとMnとを含む合金を堆積させる半導体装置の製造方法。
前記Mn原料として、ビスメチルシクロペンタジエニルマンガニーズまたはビスイソプロピルシクロペンタジエニルマンガニーズを用いる付記12に記載の半導体装置の製造方法。
2 素子分離絶縁膜
3 MOSFET
4、10、21、23、51、53 層間絶縁膜
5A バリアメタル膜
5B 導電プラグ
6、20、50 キャップ膜
11 配線
22、52 エッチングストッパ膜
24、54 ビアホール
25、55 配線溝
30、60 導電部材
32 第1の膜
33 第2の膜
34 導電部材
35 バリア層
36 被覆膜
40 下地膜
100 チャンバ
101 基板ステージ
102 ヒータ
103 真空ポンプ
104 シャワーヘッド
105 気化器
106 マスフローコントローラ
110、111、112 ガス流路
116、117、118 バルブ
Claims (10)
- (a1)半導体基板の上に形成された絶縁膜に凹部を形成する工程と、
(a2)前記凹部の内面、及び前記絶縁膜の上面を覆うように、CVD法により、Mnからなる第1の膜を形成する工程と、
(a3)前記第1の膜の上に、Cuを主成分とする導電材料を堆積させるとともに、前記凹部内に該導電材料を充填する工程と
(a4)前記半導体基板をアニールする工程と
を有する半導体装置の製造方法。 - 前記工程a3が、
前記第1の膜の表面を覆うように、CVD法またはスパッタリング法により、Cuからなる第2の膜を形成する工程と、
前記第2の膜を電極として、Cuを主成分とする導電材料を電解めっきする工程と
を含む請求項1に記載の半導体装置の製造方法。 - 前記工程a3において、Cuを主成分とする導電材料をCVD法により堆積させることにより、前記凹部内に該導電材料を充填する請求項1に記載の半導体装置の製造方法。
- (b1)半導体基板の上に形成された絶縁膜に凹部を形成する工程と、
(b2)前記凹部の内面、及び前記絶縁膜の上面を覆うように、CVD法により、Cu及びMnを含む第1の膜を形成する工程と、
(b3)前記第1の膜の上に、Cuを主成分とする導電材料を堆積させるとともに、前記凹部内に該導電材料を充填する工程と
(b4)前記半導体基板をアニールする工程と
を有する半導体装置の製造方法。 - 前記工程b3において、前記工程b2でのCVD法による前記第1の膜の形成をそのまま継続することにより、前記凹部内にCu及びMnを含む該導電材料を充填する請求項4に記載の半導体装置の製造方法。
- 前記工程b3が、
前記第1の膜の上に、スパッタリング法により、Cuからなる第2の膜を形成する工程と、
前記第2の膜を電極として、Cuを主成分とする導電材料を電解めっきする工程と
を含む請求項4に記載の半導体装置の製造方法。 - (c1)半導体基板の上に形成された絶縁膜に凹部を形成する工程と、
(c2)前記凹部の内面、及び前記絶縁膜の上面を覆うように、スパッタリング法によりCu及びMnを含む第1の膜を形成する工程と、
(c3)前記第1の膜の上に、CVD法により、Cuを主成分とする導電材料からなる第2の膜を形成する工程と、
(c4)前記凹部内に、Cuを主成分とする導電材料を充填する工程と
を有する半導体装置の製造方法。 - 前記工程c4において、前記第2の膜を電極として、前記導電材料を電解めっきする請求項7に記載の半導体装置の製造方法。
- 半導体基板の上に、Mn原料とCu原料とを同時に供給しながら、CVD法により、CuとMnとを含む合金を堆積させる半導体装置の製造方法。
- 前記Mn原料として、ビスメチルシクロペンタジエニルマンガニーズまたはビスイソプロピルシクロペンタジエニルマンガニーズを用いる請求項9に記載の半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005250046A JP4236201B2 (ja) | 2005-08-30 | 2005-08-30 | 半導体装置の製造方法 |
US11/318,530 US7413977B2 (en) | 2005-08-30 | 2005-12-28 | Method of manufacturing semiconductor device suitable for forming wiring using damascene method |
US12/216,832 US7795141B2 (en) | 2005-08-30 | 2008-07-11 | Method of manufacturing semiconductor device suitable for forming wiring using damascene method |
US12/853,676 US8071474B2 (en) | 2005-08-30 | 2010-08-10 | Method of manufacturing semiconductor device suitable for forming wiring using damascene method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005250046A JP4236201B2 (ja) | 2005-08-30 | 2005-08-30 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007067107A true JP2007067107A (ja) | 2007-03-15 |
JP4236201B2 JP4236201B2 (ja) | 2009-03-11 |
Family
ID=37804778
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005250046A Expired - Fee Related JP4236201B2 (ja) | 2005-08-30 | 2005-08-30 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (3) | US7413977B2 (ja) |
JP (1) | JP4236201B2 (ja) |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008126206A1 (ja) * | 2007-03-27 | 2008-10-23 | Fujitsu Microelectronics Limited | 半導体装置の製造方法 |
JP2008261895A (ja) * | 2007-04-10 | 2008-10-30 | Tohoku Univ | 液晶表示装置及びその製造方法 |
WO2008149844A1 (ja) * | 2007-06-04 | 2008-12-11 | Tokyo Electron Limited | 成膜方法及び成膜装置 |
WO2009034865A1 (ja) * | 2007-09-10 | 2009-03-19 | Tokyo Electron Limited | 成膜装置の排気系構造、成膜装置、および排ガスの処理方法 |
WO2010004998A1 (ja) * | 2008-07-11 | 2010-01-14 | 東京エレクトロン株式会社 | 成膜方法及び処理システム |
JP2010050359A (ja) * | 2008-08-22 | 2010-03-04 | Rohm Co Ltd | 半導体装置の製造方法 |
JP2010212497A (ja) * | 2009-03-11 | 2010-09-24 | Tokyo Electron Ltd | 半導体装置の製造方法 |
WO2010116889A1 (ja) * | 2009-04-08 | 2010-10-14 | 東京エレクトロン株式会社 | 酸化マンガン膜の形成方法、半導体装置の製造方法および半導体装置 |
WO2010147140A1 (ja) * | 2009-06-16 | 2010-12-23 | 東京エレクトロン株式会社 | バリヤ層、成膜方法及び処理システム |
US8084860B2 (en) | 2007-04-10 | 2011-12-27 | Advanced Interconnect Materials, Llc | Liquid crystal display device and manufacturing method therefor |
US8125085B2 (en) | 2008-08-22 | 2012-02-28 | Renesas Electronics Corporation | Semiconductor device having wiring with oxide layer of impurity from the wiring |
KR101171587B1 (ko) | 2008-03-03 | 2012-08-07 | 도쿄엘렉트론가부시키가이샤 | 반도체 장치의 제조 방법 및 기억 매체 |
US8247321B2 (en) | 2008-01-28 | 2012-08-21 | Tokyo Electron Limited | Method of manufacturing semiconductor device, semiconductor device, electronic instrument, semiconductor manufacturing apparatus, and storage medium |
US9136132B2 (en) | 2012-12-27 | 2015-09-15 | Tokyo Electron Limited | Manganese metal film forming method, processing system, electronic device manufacturing method and electronic device |
US9153481B2 (en) | 2012-12-27 | 2015-10-06 | Tokyo Electron Limited | Manganese-containing film forming method, processing system, electronic device manufacturing method and electronic device |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1909320A1 (en) * | 2006-10-05 | 2008-04-09 | ST Microelectronics Crolles 2 SAS | Copper diffusion barrier |
JP2007305739A (ja) * | 2006-05-10 | 2007-11-22 | Nec Electronics Corp | 半導体装置 |
JP2008013848A (ja) * | 2006-06-08 | 2008-01-24 | Tokyo Electron Ltd | 成膜装置及び成膜方法 |
JP2008028058A (ja) * | 2006-07-20 | 2008-02-07 | Tokyo Electron Ltd | 半導体装置の製造方法、半導体装置の製造装置、半導体装置及び記憶媒体 |
JP5196467B2 (ja) * | 2007-05-30 | 2013-05-15 | 東京エレクトロン株式会社 | 半導体装置の製造方法、半導体製造装置及び記憶媒体 |
TW200910431A (en) * | 2007-06-22 | 2009-03-01 | Rohm Co Ltd | Semiconductor device and method for manufacturing the same |
KR20100043289A (ko) * | 2007-09-21 | 2010-04-28 | 도쿄엘렉트론가부시키가이샤 | 성막 장치 및 성막 방법 |
US20090117731A1 (en) * | 2007-11-01 | 2009-05-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor interconnection structure and method for making the same |
JP2009147137A (ja) * | 2007-12-14 | 2009-07-02 | Toshiba Corp | 半導体装置およびその製造方法 |
JP5264187B2 (ja) * | 2008-01-08 | 2013-08-14 | パナソニック株式会社 | 半導体装置及びその製造方法 |
US8106512B2 (en) * | 2008-02-29 | 2012-01-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low resistance high reliability contact via and metal line structure for semiconductor device |
US8013445B2 (en) * | 2008-02-29 | 2011-09-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low resistance high reliability contact via and metal line structure for semiconductor device |
US7932176B2 (en) * | 2008-03-21 | 2011-04-26 | President And Fellows Of Harvard College | Self-aligned barrier layers for interconnects |
JP2010245235A (ja) * | 2009-04-03 | 2010-10-28 | Panasonic Corp | 半導体装置及びその製造方法 |
WO2011050073A1 (en) * | 2009-10-23 | 2011-04-28 | President And Fellows Of Harvard College | Self-aligned barrier and capping layers for interconnects |
US8653663B2 (en) | 2009-10-29 | 2014-02-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier layer for copper interconnect |
JP5560696B2 (ja) * | 2009-12-21 | 2014-07-30 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
JP2011249678A (ja) * | 2010-05-28 | 2011-12-08 | Elpida Memory Inc | 半導体装置及びその製造方法 |
CN102347311B (zh) * | 2010-07-29 | 2013-05-01 | 台湾积体电路制造股份有限公司 | 半导体组件及其制造方法 |
US8461683B2 (en) * | 2011-04-01 | 2013-06-11 | Intel Corporation | Self-forming, self-aligned barriers for back-end interconnects and methods of making same |
US20120273949A1 (en) * | 2011-04-27 | 2012-11-01 | Globalfoundries Singapore Pte. Ltd. | Method of forming oxide encapsulated conductive features |
CN102427040A (zh) * | 2011-07-01 | 2012-04-25 | 上海华力微电子有限公司 | 一种在层间介质层中自形成含锰硅氧化合物阻挡层的方法 |
JP2014062312A (ja) * | 2012-09-24 | 2014-04-10 | Tokyo Electron Ltd | マンガンシリケート膜の形成方法、処理システム、半導体デバイスの製造方法および半導体デバイス |
JP6221074B2 (ja) * | 2013-03-22 | 2017-11-01 | パナソニックIpマネジメント株式会社 | 半導体装置 |
US9064937B2 (en) | 2013-05-30 | 2015-06-23 | International Business Machines Corporation | Substrate bonding with diffusion barrier structures |
US9224686B1 (en) * | 2014-09-10 | 2015-12-29 | International Business Machines Corporation | Single damascene interconnect structure |
US10760156B2 (en) | 2017-10-13 | 2020-09-01 | Honeywell International Inc. | Copper manganese sputtering target |
US11035036B2 (en) | 2018-02-01 | 2021-06-15 | Honeywell International Inc. | Method of forming copper alloy sputtering targets with refined shape and microstructure |
TWI801530B (zh) * | 2018-07-03 | 2023-05-11 | 南韓商三星電子股份有限公司 | 半導體裝置 |
CN109216265B (zh) * | 2018-08-31 | 2021-07-27 | 上海华力微电子有限公司 | 一种形成金属扩散阻挡层的方法 |
US10651084B1 (en) | 2019-07-18 | 2020-05-12 | Micron Technology, Inc. | Microelectronic devices comprising manganese-containing conductive structures, and related electronic systems and methods |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3403357B2 (ja) | 1999-06-03 | 2003-05-06 | 株式会社半導体先端テクノロジーズ | 配線形成方法及び配線形成装置 |
US6398929B1 (en) * | 1999-10-08 | 2002-06-04 | Applied Materials, Inc. | Plasma reactor and shields generating self-ionized plasma for sputtering |
JP4478038B2 (ja) * | 2004-02-27 | 2010-06-09 | 株式会社半導体理工学研究センター | 半導体装置及びその製造方法 |
WO2006102180A2 (en) * | 2005-03-18 | 2006-09-28 | Applied Materials, Inc. | Contact metallization methods and processes |
-
2005
- 2005-08-30 JP JP2005250046A patent/JP4236201B2/ja not_active Expired - Fee Related
- 2005-12-28 US US11/318,530 patent/US7413977B2/en active Active
-
2008
- 2008-07-11 US US12/216,832 patent/US7795141B2/en active Active
-
2010
- 2010-08-10 US US12/853,676 patent/US8071474B2/en active Active
Cited By (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8003518B2 (en) | 2007-03-27 | 2011-08-23 | Fujitsu Semiconductor Limited | Semiconductor device fabrication method |
WO2008126206A1 (ja) * | 2007-03-27 | 2008-10-23 | Fujitsu Microelectronics Limited | 半導体装置の製造方法 |
JP2008261895A (ja) * | 2007-04-10 | 2008-10-30 | Tohoku Univ | 液晶表示装置及びその製造方法 |
US8089158B2 (en) | 2007-04-10 | 2012-01-03 | Advanced Interconnect Materials, Llc | Liquid crystal display device and manufacturing method therefor |
US8084860B2 (en) | 2007-04-10 | 2011-12-27 | Advanced Interconnect Materials, Llc | Liquid crystal display device and manufacturing method therefor |
WO2008149844A1 (ja) * | 2007-06-04 | 2008-12-11 | Tokyo Electron Limited | 成膜方法及び成膜装置 |
JP2009016782A (ja) * | 2007-06-04 | 2009-01-22 | Tokyo Electron Ltd | 成膜方法及び成膜装置 |
JP2013219380A (ja) * | 2007-06-04 | 2013-10-24 | Tokyo Electron Ltd | 成膜方法及び成膜装置 |
US8242015B2 (en) | 2007-06-04 | 2012-08-14 | Tokyo Electron Limited | Film forming method and film forming apparatus |
KR101209997B1 (ko) * | 2007-09-10 | 2012-12-07 | 도쿄엘렉트론가부시키가이샤 | 성막 장치의 배기계 구조, 성막 장치 및 배기 가스의 처리 방법 |
KR101151513B1 (ko) * | 2007-09-10 | 2012-05-31 | 도쿄엘렉트론가부시키가이샤 | 성막 장치의 배기계 구조, 성막 장치 및 배기 가스의 처리 방법 |
WO2009034865A1 (ja) * | 2007-09-10 | 2009-03-19 | Tokyo Electron Limited | 成膜装置の排気系構造、成膜装置、および排ガスの処理方法 |
JP2009062599A (ja) * | 2007-09-10 | 2009-03-26 | Tokyo Electron Ltd | 成膜装置の排気系構造、成膜装置、および排ガスの処理方法 |
US8247321B2 (en) | 2008-01-28 | 2012-08-21 | Tokyo Electron Limited | Method of manufacturing semiconductor device, semiconductor device, electronic instrument, semiconductor manufacturing apparatus, and storage medium |
KR101171587B1 (ko) | 2008-03-03 | 2012-08-07 | 도쿄엘렉트론가부시키가이샤 | 반도체 장치의 제조 방법 및 기억 매체 |
KR101214704B1 (ko) * | 2008-07-11 | 2012-12-21 | 도쿄엘렉트론가부시키가이샤 | 성막 방법 및 처리 시스템 |
US8440563B2 (en) | 2008-07-11 | 2013-05-14 | Tokyo Electron Limited | Film forming method and processing system |
WO2010004998A1 (ja) * | 2008-07-11 | 2010-01-14 | 東京エレクトロン株式会社 | 成膜方法及び処理システム |
JP2010021447A (ja) * | 2008-07-11 | 2010-01-28 | Tokyo Electron Ltd | 成膜方法及び処理システム |
US8125085B2 (en) | 2008-08-22 | 2012-02-28 | Renesas Electronics Corporation | Semiconductor device having wiring with oxide layer of impurity from the wiring |
JP2010050359A (ja) * | 2008-08-22 | 2010-03-04 | Rohm Co Ltd | 半導体装置の製造方法 |
JP2010212497A (ja) * | 2009-03-11 | 2010-09-24 | Tokyo Electron Ltd | 半導体装置の製造方法 |
WO2010116889A1 (ja) * | 2009-04-08 | 2010-10-14 | 東京エレクトロン株式会社 | 酸化マンガン膜の形成方法、半導体装置の製造方法および半導体装置 |
JP2010242187A (ja) * | 2009-04-08 | 2010-10-28 | Tokyo Electron Ltd | 酸化マンガン膜の形成方法、半導体装置の製造方法および半導体装置 |
US8859421B2 (en) | 2009-04-08 | 2014-10-14 | Tokyo Electron Limited | Manganese oxide film forming method, semiconductor device manufacturing method and semiconductor device |
WO2010147140A1 (ja) * | 2009-06-16 | 2010-12-23 | 東京エレクトロン株式会社 | バリヤ層、成膜方法及び処理システム |
KR101275679B1 (ko) | 2009-06-16 | 2013-06-17 | 도쿄엘렉트론가부시키가이샤 | 배리어층, 성막 방법 및 처리 시스템 |
US8653665B2 (en) | 2009-06-16 | 2014-02-18 | Tokyo Electron Limited | Barrier layer, film forming method, and processing system |
US9136132B2 (en) | 2012-12-27 | 2015-09-15 | Tokyo Electron Limited | Manganese metal film forming method, processing system, electronic device manufacturing method and electronic device |
US9153481B2 (en) | 2012-12-27 | 2015-10-06 | Tokyo Electron Limited | Manganese-containing film forming method, processing system, electronic device manufacturing method and electronic device |
Also Published As
Publication number | Publication date |
---|---|
US20080286960A1 (en) | 2008-11-20 |
US20100323519A1 (en) | 2010-12-23 |
US7795141B2 (en) | 2010-09-14 |
US7413977B2 (en) | 2008-08-19 |
US8071474B2 (en) | 2011-12-06 |
JP4236201B2 (ja) | 2009-03-11 |
US20070048931A1 (en) | 2007-03-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4236201B2 (ja) | 半導体装置の製造方法 | |
JP4523535B2 (ja) | 半導体装置の製造方法 | |
JP4272191B2 (ja) | 半導体装置の製造方法 | |
US9112004B2 (en) | Barrier layer for copper interconnect | |
US6645847B2 (en) | Microelectronic interconnect material with adhesion promotion layer and fabrication method | |
JP5560696B2 (ja) | 半導体装置の製造方法 | |
US20020024142A1 (en) | Semiconductor device and manufacturing method of the same | |
JP2008047719A (ja) | 半導体装置の製造方法 | |
US6576543B2 (en) | Method for selectively depositing diffusion barriers | |
US5994775A (en) | Metal-filled via/contact opening with thin barrier layers in integrated circuit structure for fast response, and process for making same | |
JP5481989B2 (ja) | 半導体装置の製造方法 | |
US9382627B2 (en) | Methods and materials for anchoring gapfill metals | |
US20060154465A1 (en) | Method for fabricating interconnection line in semiconductor device | |
JP2005005383A (ja) | 半導体装置および半導体装置の製造方法 | |
KR101088813B1 (ko) | 반도체 소자의 금속배선 및 그 형성방법 | |
KR100652317B1 (ko) | 반도체 소자의 금속 패드 제조 방법 | |
JP4733804B2 (ja) | 配線の形成方法 | |
KR100815938B1 (ko) | 반도체 소자의 금속 배선 형성 방법 | |
JPH11186390A (ja) | 半導体装置の製造方法 | |
KR100891524B1 (ko) | 반도체 소자의 제조방법 | |
JP2006024667A (ja) | 半導体装置の製造方法 | |
JP2006147895A (ja) | 半導体装置の製造方法 | |
JP2006054326A (ja) | 半導体装置の製造方法及び半導体装置 | |
JP2004006541A (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20080729 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080821 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080902 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20081030 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20081202 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20081212 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4236201 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111226 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111226 Year of fee payment: 3 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111226 Year of fee payment: 3 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111226 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121226 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121226 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131226 Year of fee payment: 5 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |