JP4272191B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4272191B2 JP4272191B2 JP2005249651A JP2005249651A JP4272191B2 JP 4272191 B2 JP4272191 B2 JP 4272191B2 JP 2005249651 A JP2005249651 A JP 2005249651A JP 2005249651 A JP2005249651 A JP 2005249651A JP 4272191 B2 JP4272191 B2 JP 4272191B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physical Vapour Deposition (AREA)
Description
W.A.Lanford et al.,"Low-temperature passivation of copper by doping with Al or Mg", ThinSolid Films, 262(1995) p.234-241 T. Usui et al., "LowResistive and Highly Reliable Cu Dual-Damascene Interconnect Technology UsingSelf-Formed MnSixOy Barrier Layer", IITC 2005, Session 9.2
(a)半導体基板上に、凹部が設けられた絶縁膜を形成する工程と、
(b)前記凹部の内面及び前記絶縁膜の上面を、Cu以外に、Mn、Al、Mg、及びNiからなる群より選択された少なくとも1つの金属元素を含むCu合金からなる補助膜で覆う工程と、
(c)前記凹部内に充填されるように、前記補助膜上に、Cuを主成分とする導電部材を堆積させる工程と、
(d)P化合物、Si化合物、またはB化合物を含有する雰囲気下で熱処理を行う工程と
を有する半導体装置の製造方法が提供される。
(a)半導体基板上に、凹部が設けられた絶縁膜を形成する工程と、
(b)前記凹部の内面及び前記絶縁膜の上面を、Cu以外に、Mn、Al、Mg、及びNiからなる群より選択された少なくとも1つの金属元素である第1の金属元素を含むCu合金からなる補助膜で覆う工程と、
(c)前記凹部内に充填されるように、前記補助膜上に、Cuを主成分とする導電部材を堆積させる工程と、
(d)P化合物、Si化合物、またはB化合物を含有する雰囲気下で熱処理を行う工程と
を有し、
前記工程dで生成される前記第1の金属元素のリン化物、珪化物、酸化珪化物またはホウ化物の標準生成エンタルピーが、該第1の金属元素の酸化物の標準生成エンタルピーよりも小さい半導体装置の製造方法が提供される。
保護膜6の上に、低誘電率絶縁材料からなる層間絶縁膜10が形成されている。層間絶縁膜10に、その底面まで達し、導電プラグ5Bの上方を通過する配線溝が形成されている。この配線溝内に第1層目の銅配線11が充填されている。銅配線11は、導電プラグ5Bに接続される。
配線層の層間絶縁膜23に配線溝25が形成され、ビア層の層間絶縁膜21にビアホール24が形成されている。配線溝25はエッチングストッパ膜22の上面まで達する。ビアホール24は、配線溝25の底面に開口するとともに、キャップ膜20を貫通して下層の配線11の上面まで達する。
上記第1の実施例では、図2Eに示した工程で、ホウ化マンガン、リン化マンガン、珪化マンガン、または酸化珪化マンガンからなる被覆膜35を形成した。より一般的には、被覆膜35の材料、すなわち補助膜32を構成するCu以外の金属元素のホウ化物、リン化物、珪化物、酸化珪化物の標準生成エンタルピーが、この金属元素の酸化物の標準生成エンタルピーよりも小さくなるように、補助膜32及びアニール雰囲気中の添加物を選択すればよい。酸化物の標準生成エンタルピーが小さいため、酸素雰囲気中でアニールする場合に比べて、より低い温度で被覆膜35を形成することができる。すなわち、導電部材33内のCu以外の金属元素が、被覆膜35によって消費されやすくなり、導電部材33の純度を高めることができる。
2 素子分離絶縁膜
3 MOSFET
4、10、21、23、51、53 層間絶縁膜
5A バリアメタル膜
5B 導電プラグ
6、20、50 キャップ膜
11 配線
22、52 エッチングストッパ膜
24、54 ビアホール
25、55 配線溝
30、33、43、60 導電部材
32、36 補助膜
34 バリア層
35 被覆膜
Claims (5)
- (a)半導体基板上に、凹部が設けられた絶縁膜を形成する工程と、
(b)前記凹部の内面及び前記絶縁膜の上面を、Cu以外に、Mn、Al、Mg、及びNiからなる群より選択された少なくとも1つの金属元素を含むCu合金からなる補助膜で覆う工程と、
(c)前記凹部内に充填されるように、前記補助膜上に、Cuを主成分とする導電部材を堆積させる工程と、
(d)P化合物、Si化合物、またはB化合物を含有する雰囲気下で熱処理を行う工程と
を有する半導体装置の製造方法。 - (a)半導体基板上に、凹部が設けられた絶縁膜を形成する工程と、
(b)前記凹部の内面及び前記絶縁膜の上面を、Cu以外に、Mn、Al、Mg、及びNiからなる群より選択された少なくとも1つの金属元素である第1の金属元素を含むCu合金からなる補助膜で覆う工程と、
(c)前記凹部内に充填されるように、前記補助膜上に、Cuを主成分とする導電部材を堆積させる工程と、
(d)P化合物、Si化合物、またはB化合物を含有する雰囲気下で熱処理を行う工程と
を有し、
前記工程dで生成される前記第1の金属元素のリン化物、珪化物、酸化珪化物またはホウ化物の標準生成エンタルピーが、該第1の金属元素の酸化物の標準生成エンタルピーよりも小さい半導体装置の製造方法。
- 前記工程dにおいて、PH3、(CH3)3P、t−C4H9PH2、P(OCH3)3、SiH4、Si2H6、(CH3)4Si、Si(OC2H5)4、Si(OCH3)4、シロキサン、B2H6、B(OC2H5)3、及びB(OCH3)3からなる群より選択された少なくとも1つの化合物を含有する雰囲気下で熱処理を行う請求項1または2に記載の半導体装置の製造方法。
- 前記工程bにおいて、基板温度を100℃以上にした条件で、スパッタリングにより、前記補助膜を形成する請求項1〜3のいずれかに記載の半導体装置の製造方法。
- 前記工程bにおいて、基板温度300℃以下の条件で前記補助膜を形成する請求項4に記載の半導体装置の製造方法。
Priority Applications (2)
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JP2005249651A JP4272191B2 (ja) | 2005-08-30 | 2005-08-30 | 半導体装置の製造方法 |
US11/294,471 US7507666B2 (en) | 2005-08-30 | 2005-12-06 | Manufacture method for semiconductor device having concave portions filled with conductor containing Cu as its main composition |
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JP2005249651A JP4272191B2 (ja) | 2005-08-30 | 2005-08-30 | 半導体装置の製造方法 |
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JP2007067083A JP2007067083A (ja) | 2007-03-15 |
JP4272191B2 true JP4272191B2 (ja) | 2009-06-03 |
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Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100651602B1 (ko) * | 2005-12-14 | 2006-11-30 | 동부일렉트로닉스 주식회사 | 반도체 장치의 금속 배선 형성 방법 |
ATE553223T1 (de) * | 2006-02-28 | 2012-04-15 | Advanced Interconnect Materials Llc | Halbleitervorrichtung, herstellungsverfahren dafür und sputtern von zielmaterial zur verwendung für das verfahren |
US8372745B2 (en) * | 2006-02-28 | 2013-02-12 | Advanced Interconnect Materials, Llc | Semiconductor device, its manufacturing method, and sputtering target material for use in the method |
JP4321570B2 (ja) * | 2006-09-06 | 2009-08-26 | ソニー株式会社 | 半導体装置の製造方法 |
JP5103914B2 (ja) * | 2007-01-31 | 2012-12-19 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法及び半導体装置 |
JP2008218659A (ja) | 2007-03-02 | 2008-09-18 | Tokyo Electron Ltd | 半導体装置の製造方法、半導体製造装置及びプログラム |
US7633164B2 (en) * | 2007-04-10 | 2009-12-15 | Tohoku University | Liquid crystal display device and manufacturing method therefor |
US7782413B2 (en) * | 2007-05-09 | 2010-08-24 | Tohoku University | Liquid crystal display device and manufacturing method therefor |
JP5089244B2 (ja) * | 2007-05-22 | 2012-12-05 | ローム株式会社 | 半導体装置 |
JP5196467B2 (ja) * | 2007-05-30 | 2013-05-15 | 東京エレクトロン株式会社 | 半導体装置の製造方法、半導体製造装置及び記憶媒体 |
JP5264187B2 (ja) * | 2008-01-08 | 2013-08-14 | パナソニック株式会社 | 半導体装置及びその製造方法 |
US7932176B2 (en) * | 2008-03-21 | 2011-04-26 | President And Fellows Of Harvard College | Self-aligned barrier layers for interconnects |
JP4423379B2 (ja) * | 2008-03-25 | 2010-03-03 | 合同会社先端配線材料研究所 | 銅配線、半導体装置および銅配線の形成方法 |
JP5571887B2 (ja) * | 2008-08-19 | 2014-08-13 | アルティアム サービシズ リミテッド エルエルシー | 液晶表示装置及びその製造方法 |
US8258626B2 (en) * | 2008-09-16 | 2012-09-04 | Advanced Interconnect Materials, Llc | Copper interconnection, method for forming copper interconnection structure, and semiconductor device |
JP2010100886A (ja) * | 2008-10-22 | 2010-05-06 | Sanyo Shinku Kogyo Kk | 基板の保護膜 |
JP4441658B1 (ja) * | 2008-12-19 | 2010-03-31 | 国立大学法人東北大学 | 銅配線形成方法、銅配線および半導体装置 |
JP4415100B1 (ja) | 2008-12-19 | 2010-02-17 | 国立大学法人東北大学 | 銅配線、半導体装置および銅配線形成方法 |
US8653664B2 (en) | 2009-07-08 | 2014-02-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier layers for copper interconnect |
US8531033B2 (en) * | 2009-09-07 | 2013-09-10 | Advanced Interconnect Materials, Llc | Contact plug structure, semiconductor device, and method for forming contact plug |
KR101770538B1 (ko) * | 2009-10-23 | 2017-08-22 | 프레지던트 앤드 펠로우즈 오브 하바드 칼리지 | 상호 접속부를 위한 자기―정렬 배리어 및 캡핑 층 |
US8653663B2 (en) * | 2009-10-29 | 2014-02-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier layer for copper interconnect |
JP2011216862A (ja) * | 2010-03-16 | 2011-10-27 | Tokyo Electron Ltd | 成膜方法及び成膜装置 |
US8361900B2 (en) | 2010-04-16 | 2013-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier layer for copper interconnect |
US8461683B2 (en) * | 2011-04-01 | 2013-06-11 | Intel Corporation | Self-forming, self-aligned barriers for back-end interconnects and methods of making same |
US8618661B2 (en) * | 2011-10-03 | 2013-12-31 | Texas Instruments Incorporated | Die having coefficient of thermal expansion graded layer |
JP5835696B2 (ja) | 2012-09-05 | 2015-12-24 | 株式会社東芝 | 半導体装置およびその製造方法 |
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US6288448B1 (en) * | 1999-05-14 | 2001-09-11 | Advanced Micro Devices, Inc. | Semiconductor interconnect barrier of boron silicon nitride and manufacturing method therefor |
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