JP2007067017A - 半導体装置及びその製造方法 - Google Patents
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Abstract
【解決手段】 デバイス形成層18と電極パッド20を有する半導体素子14の電極パッド20と半導体素子14の他面側に形成された再配線パターン52とを接続する貫通電極56を有する半導体装置の製造方法であって、半導体素子14の上面側にデバイス形成層18及び電極パッド20を形成し、電極パッド20及びデバイス形成層18の表面に第1レジスト層62を形成し、電極パッド20にエッチングにより開口64を形成し、開口64に連通する位置に貫通孔54をエッチングにより半導体素子14に形成する。第1レジスト層62によりデバイス形成層18を保護すると共に、貫通電極56を設けてフリップチップ接続を可能にして小型化を図る。
【選択図】 図2
Description
図3A〜図3Fは本発明による半導体装置の製造方法の開口形成工程(その1〜6)を説明するための図である。図3Aに示す工程において、半導体素子14を形成するための平板状のシリコン材料(シリコン基板)を用意する。そして、シリコン基板(図3〜図7では、便宜上、半導体素子14として示す)の上面(表面)に絶縁膜(SiO2)60を形成し、絶縁膜60の上面にデバイス形成層18を形成する。
図4A〜図4Cは本発明による半導体装置の製造方法の絶縁層形成工程(その1〜3)を説明するための図である。図4Aに示す工程において、第2レジスト層66の上面に樹脂からなる保護フィルム70を貼着する。この保護フィルム70は、デバイス形成層18を保護すると共に、貫通孔54に連通された開口64を上面側から閉塞する。
図5A〜図5Cは本発明による半導体装置の製造方法の貫通電極形成工程(その1〜3)を説明するための図である。図5Aに示す工程において、絶縁層72の下面に導電材を貼着し、給電層80を形成する。従って、貫通孔54の下面側はこの給電層80により閉塞される。
図6A〜図6Dは本発明による半導体装置の製造方法のパッドと貫通電極の導通確保工程(その1〜4)を説明するための図である。図6Aに示す工程において、平坦化された上面にフォトレジストを塗布して第3レジスト層82を形成する。そして、第3レジスト層82のうちAl電極パッド20の上方を覆う部分を削除して開口84を形成する。この第3レジスト層82は、前述した第1レジスト層62及び第2レジスト層66よりも厚く塗布されている。
図7A〜図7Cは本発明による半導体装置の製造方法の再配線及びレジスト除去工程(その1〜3)を説明するための図である。図7Aに示す工程において、半導体素子14の下面側(裏面側)に形成された給電層80をエッチングにより除去して絶縁層72を露出させる。
18 デバイス形成層
20 Al電極パッド
50 半導体装置
54 貫通孔
52 再配線パターン
56 貫通電極
62 第1レジスト層
64 開口
66 第2レジスト層
70 保護フィルム
72 絶縁層
80 給電層
82 第3レジスト層
84 開口
86 凹部
88 金属層
Claims (9)
- 一面側にデバイス形成層と電極パッドを有する半導体素子の前記電極パッドと前記半導体素子の他面側とを接続する貫通電極を有する半導体装置の製造方法であって、
前記半導体素子の一面側の前記電極パッド及び前記デバイス形成層の表面に第1レジスト層を形成する第1工程と、
前記電極パッドにエッチングにより開口を形成する第2工程と、
一端が前記開口に連通し、他端が前記半導体素子の他面側に開口する貫通孔をエッチングにより前記基板に形成する第3工程と、
前記貫通孔に前記貫通電極を形成する第4工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記第2工程は、
前記電極パッドの前記開口の内周に第2のレジスト層を形成する工程を含むことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第1レジスト層または第2レジスト層の表面に保護フィルムを貼着する第5工程をさらに有することを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 前記半導体素子の他面側から絶縁層を形成し、前記半導体素子の一面側に延在する前記貫通孔の内周面及び前記保護フィルムの下面に絶縁層を延在する第6工程をさらに有することを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記保護フィルムを剥離させて前記貫通孔の一側を露出させる第7工程をさらに有することを特徴とする請求項4に記載の半導体装置の製造方法。
- 前記半導体素子の他面側に給電層を形成し、前記半導体素子の他面側から前記貫通孔内に貫通電極を形成する第8工程をさらに有することを特徴とする請求項5に記載の半導体装置の製造方法。
- 一面側にデバイス形成層と電極パッドを有する半導体素子の前記電極パッドと前記半導体素子の他面側とを接続する貫通電極を有する半導体装置であって、
前記デバイス形成層が形成たされた前記半導体素子の一面側に絶縁層を介して形成された電極パッドと、
前記半導体素子の一面側にレジストを被覆した状態でエッチングにより、前記電極パッド及び前記基板を貫通するように形成された貫通孔と、
前記貫通孔の内周に形成され、前記貫通孔から前記半導体素子の一面側に突出するように形成された絶縁層と、
前記絶縁層の外部に形成された前記電極パッドと前記絶縁層の内部に形成された前記貫通電極の端部とを接続する導電層と、
を備えたことを特徴とする半導体装置。 - 前記デバイス形成層は、光を受光または発光する光機能素子であることを特徴とする請求項7に記載の半導体装置。
- 前記デバイス形成層は、光を検知して画像信号を出力するイメージセンサであることを特徴とする請求項7に記載の半導体装置。
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JP2005248399A JP4758712B2 (ja) | 2005-08-29 | 2005-08-29 | 半導体装置の製造方法 |
US11/509,700 US7605080B2 (en) | 2005-08-29 | 2006-08-25 | Semiconductor device and method of manufacturing the same |
EP06018011.4A EP1760775B1 (en) | 2005-08-29 | 2006-08-29 | Semiconductor device with through electrode and method of manufacturing the same |
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JP2011109289A Division JP5313294B2 (ja) | 2011-05-16 | 2011-05-16 | 半導体装置 |
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Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008143461A2 (en) * | 2007-05-21 | 2008-11-27 | Tae-Seok Park | Wafer level chip scale package of an image sensor by means of through hole interconnection and method for manufacturing the same |
JP2009027179A (ja) * | 2007-07-23 | 2009-02-05 | Samsung Electronics Co Ltd | ユニバーサル配線ラインを含む半導体チップ、半導体パッケージ、カード及びシステム |
JP2009105376A (ja) * | 2007-10-19 | 2009-05-14 | Samsung Electro-Mechanics Co Ltd | 半導体発光素子、その製造方法及びこれを用いた半導体発光素子パッケージ |
KR100897761B1 (ko) * | 2007-05-21 | 2009-05-15 | 박태석 | 관통 비아홀 공정을 이용한 실리콘 이미지 센서의 웨이퍼레벨 패키지 및 그 제조방법 |
KR100922837B1 (ko) * | 2007-11-23 | 2009-10-23 | 박태석 | 마이크로 비아 홀 연결에 의한 실리콘 이미지 센서의웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법 |
JP2009267122A (ja) * | 2008-04-25 | 2009-11-12 | Oki Semiconductor Co Ltd | 半導体装置 |
JP2010067844A (ja) * | 2008-09-11 | 2010-03-25 | Omron Corp | 固体撮像素子の製造方法 |
JP4454689B1 (ja) * | 2009-09-10 | 2010-04-21 | 有限会社ナプラ | 発光ダイオード、発光装置、照明装置、ディスプレイ及び信号灯 |
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US7605080B2 (en) | 2009-10-20 |
JP4758712B2 (ja) | 2011-08-31 |
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