JP2007049119A - フラッシュメモリ素子およびその製造方法 - Google Patents
フラッシュメモリ素子およびその製造方法 Download PDFInfo
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- JP2007049119A JP2007049119A JP2006138672A JP2006138672A JP2007049119A JP 2007049119 A JP2007049119 A JP 2007049119A JP 2006138672 A JP2006138672 A JP 2006138672A JP 2006138672 A JP2006138672 A JP 2006138672A JP 2007049119 A JP2007049119 A JP 2007049119A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
Abstract
【解決手段】メモリセル領域Aとペリ領域Cとの境界部分にゲートライン12が通るか否かによって、ゲートライン12が通る場合には、その境界部分を素子分離膜11aで構成し、ゲートライン12が通らない場合には、ダミーアクティブ(dummy active)で構成することにより素子の信頼性を改善し、ウェルピックアップ(well pick up)領域を上記ダミーアクティブ内に構成することで集積度を向上させる。
【選択図】図1
Description
High Density plasma)酸化膜ギャップフィル時にステップカバレッジ(step coverage)が不良化する問題がある。
11a メモリセル領域の素子分離膜
11b 素子分離膜
12 ゲートライン
13 ウェルピックアップ領域
Claims (9)
- メモリセル領域およびペリ領域を有する半導体基板にゲートラインが形成された半導体素子において、
前記ゲートラインが通る前記境界部分に素子分離膜が形成され、前記ゲートラインが通らない境界部分にダミーアクティブが形成されることを特徴とするフラッシュメモリ素子。 - 前記ダミーアクティブ領域内に形成されたウェルピックアップ領域を含むことを特徴とする請求項1に記載のフラッシュメモリ素子。
- 前記半導体基板内に形成されるウェル領域を含み、前記ウェルピックアップ領域が前記ウェル領域より高濃度を有することを特徴とする請求項2に記載のフラッシュメモリ素子。
- 半導体基板上に形成されたメモリセル領域およびペリ領域間の境界部分にゲートラインが通る半導体素子の製造方法において、
前記ゲートラインが通る前記境界部分に素子分離膜を形成し、前記ゲートラインが通らない境界部分にダミーアクティブを形成する工程と、
前記記素子分離膜が形成された前記メモリセル領域と前記ペリ領域との間の境界部分を通るゲートラインを形成する工程と、
を含むことを特徴とするフラッシュメモリ素子の製造方法。 - 前記素子分離膜および前記ダミーアクティブを形成後、前記ダミーアクティブ内にウェルピックアップ領域を形成する工程を含むことを特徴とする請求項4に記載のフラッシュメモリ素子の製造方法。
- 前記ウェルピックアップ領域は、前記半導体基板内に形成されているウェル領域と同一の不純物で形成されることを特徴とする請求項5に記載のフラッシュメモリ素子の製造方法。
- 前記ウェルピックアップ領域が前記ウェル領域に比べて高濃度の不純物注入を通じて形成されることを特徴とする請求項6に記載のフラッシュメモリ素子の製造方法。
- 前記不純物は、B+あるいはBF2 +イオンであることを特徴とする請求項6に記載のフラッシュメモリ素子の製造方法。
- 前記不純物は、5E14〜5E15ions/cm2のドーズ量で注入されることを特徴とする請求項6に記載のフラッシュメモリ素子の製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050072323A KR100650870B1 (ko) | 2005-08-08 | 2005-08-08 | 플래쉬 메모리 소자 및 그의 제조방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2007049119A true JP2007049119A (ja) | 2007-02-22 |
Family
ID=37716899
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2006138672A Pending JP2007049119A (ja) | 2005-08-08 | 2006-05-18 | フラッシュメモリ素子およびその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7719061B2 (ja) |
JP (1) | JP2007049119A (ja) |
KR (1) | KR100650870B1 (ja) |
CN (1) | CN100461418C (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7804127B2 (en) | 2007-08-16 | 2010-09-28 | Oki Electric Industry Co., Ltd. | Semiconductor non-volatile memory having semiconductor non-volatile memory cell with electric charge accumulation layer, and method of producing the same |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140167206A1 (en) * | 2012-12-17 | 2014-06-19 | Macronix International Co., Ltd. | Shallow trench isolation structure and method of manufacture |
KR102282136B1 (ko) | 2017-07-07 | 2021-07-27 | 삼성전자주식회사 | 반도체 장치 |
US10157987B1 (en) | 2017-08-14 | 2018-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin-based strap cell structure |
US11239089B2 (en) | 2019-12-16 | 2022-02-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
CN112071844B (zh) * | 2020-09-18 | 2024-02-02 | 上海华虹宏力半导体制造有限公司 | 闪存器件的掩膜版及制造方法 |
CN114388018A (zh) * | 2020-12-14 | 2022-04-22 | 台湾积体电路制造股份有限公司 | 存储装置 |
Citations (6)
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JPH10173035A (ja) * | 1996-12-10 | 1998-06-26 | Hitachi Ltd | 半導体集積回路装置およびその設計方法 |
JPH10335333A (ja) * | 1997-03-31 | 1998-12-18 | Hitachi Ltd | 半導体集積回路装置およびその製造方法ならびに設計方法 |
JP2002009161A (ja) | 2000-04-19 | 2002-01-11 | Mitsubishi Electric Corp | 半導体装置およびダミーパターンの配置方法 |
JP2002151601A (ja) | 2000-11-08 | 2002-05-24 | Toshiba Corp | 半導体記憶装置 |
JP2003332415A (ja) | 2003-04-21 | 2003-11-21 | Seiko Epson Corp | 半導体装置 |
JP2004015056A (ja) * | 2002-06-05 | 2004-01-15 | Samsung Electronics Co Ltd | ライン型パターンを有する半導体素子及びそのレイアウト方法 |
Family Cites Families (12)
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US6342715B1 (en) * | 1997-06-27 | 2002-01-29 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
JP3519583B2 (ja) * | 1997-09-19 | 2004-04-19 | 株式会社東芝 | 不揮発性半導体記憶装置およびその製造方法 |
TW449939B (en) * | 2000-07-03 | 2001-08-11 | United Microelectronics Corp | Photodiode structure |
TWI277199B (en) * | 2001-06-28 | 2007-03-21 | Toshiba Corp | Semiconductor device and manufacturing method therefor |
JP4322453B2 (ja) * | 2001-09-27 | 2009-09-02 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP4152668B2 (ja) * | 2002-04-30 | 2008-09-17 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
TWI252565B (en) * | 2002-06-24 | 2006-04-01 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
KR100493025B1 (ko) | 2002-08-07 | 2005-06-07 | 삼성전자주식회사 | 반도체 메모리 장치의 제조 방법 |
US6833622B1 (en) * | 2003-02-27 | 2004-12-21 | Cypress Semiconductor Corp. | Semiconductor topography having an inactive region formed from a dummy structure pattern |
US6765260B1 (en) * | 2003-03-11 | 2004-07-20 | Powerchip Semiconductor Corp. | Flash memory with self-aligned split gate and methods for fabricating and for operating the same |
KR20050070861A (ko) * | 2003-12-31 | 2005-07-07 | 동부아남반도체 주식회사 | 반도체 소자의 더미층 및 그 제조방법 |
US6878988B1 (en) * | 2004-06-02 | 2005-04-12 | United Microelectronics Corp. | Non-volatile memory with induced bit lines |
-
2005
- 2005-08-08 KR KR1020050072323A patent/KR100650870B1/ko not_active IP Right Cessation
-
2006
- 2006-05-18 JP JP2006138672A patent/JP2007049119A/ja active Pending
- 2006-06-30 US US11/479,330 patent/US7719061B2/en active Active
- 2006-07-27 CN CNB2006101081124A patent/CN100461418C/zh not_active Expired - Fee Related
-
2010
- 2010-05-17 US US12/781,777 patent/US8252661B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10173035A (ja) * | 1996-12-10 | 1998-06-26 | Hitachi Ltd | 半導体集積回路装置およびその設計方法 |
JPH10335333A (ja) * | 1997-03-31 | 1998-12-18 | Hitachi Ltd | 半導体集積回路装置およびその製造方法ならびに設計方法 |
JP2002009161A (ja) | 2000-04-19 | 2002-01-11 | Mitsubishi Electric Corp | 半導体装置およびダミーパターンの配置方法 |
JP2002151601A (ja) | 2000-11-08 | 2002-05-24 | Toshiba Corp | 半導体記憶装置 |
JP2004015056A (ja) * | 2002-06-05 | 2004-01-15 | Samsung Electronics Co Ltd | ライン型パターンを有する半導体素子及びそのレイアウト方法 |
JP2003332415A (ja) | 2003-04-21 | 2003-11-21 | Seiko Epson Corp | 半導体装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7804127B2 (en) | 2007-08-16 | 2010-09-28 | Oki Electric Industry Co., Ltd. | Semiconductor non-volatile memory having semiconductor non-volatile memory cell with electric charge accumulation layer, and method of producing the same |
Also Published As
Publication number | Publication date |
---|---|
CN1913160A (zh) | 2007-02-14 |
US7719061B2 (en) | 2010-05-18 |
US20100291750A1 (en) | 2010-11-18 |
KR100650870B1 (ko) | 2008-07-16 |
US8252661B2 (en) | 2012-08-28 |
US20070029622A1 (en) | 2007-02-08 |
CN100461418C (zh) | 2009-02-11 |
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