JP2007048785A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2007048785A JP2007048785A JP2005228769A JP2005228769A JP2007048785A JP 2007048785 A JP2007048785 A JP 2007048785A JP 2005228769 A JP2005228769 A JP 2005228769A JP 2005228769 A JP2005228769 A JP 2005228769A JP 2007048785 A JP2007048785 A JP 2007048785A
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- dielectric constant
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
【解決手段】 基板上に形成された、開口部を有する多孔質低誘電率膜と、多孔質低誘電率膜における開口部を構成する部分の表面に形成された、各々の直径が1nm以上であって且つ2nm以下である複数の微粒子が集積されてなる微粒子体膜とを備え、多孔質低誘電率膜における開口部を構成する部分の表面に曝露する空孔には、微粒子が充填されている。
【選択図】 図2
Description
IEEE,IITC2003、P97〜99、Fig.7 IEEE,IITC2004、P175〜177、Fig.1 IEEE,IITC2004、P39〜41
101 下部配線
101a バリアメタル
101b Cu膜
102 多孔質低誘電率膜
103 フォトレジスト
104 配線溝
105 ビア孔
106 堆積膜(C元素及びF元素を含む薄膜)
107 微粒子体膜
108 バリアメタル
109 埋め込み層
110 上部配線
200 微粒子
201 空孔
202 連結部
W 孔径
300 層間絶縁膜
301 下部配線
301a バリアメタル
301b Cu膜
302 低誘電率膜
303 ビア孔
304 配線溝
305 バリアメタル
306 シード層
307 めっき層
308 上部配線
400 拡散領域
401 Cu拡散領域
R 経路
Claims (6)
- 基板上に形成された、開口部を有する多孔質低誘電率膜と、
前記多孔質低誘電率膜における前記開口部を構成する部分の表面に形成された、各々の直径が1nm以上であって且つ2nm以下である複数の微粒子が集積されてなる微粒子体膜とを備え、
前記多孔質低誘電率膜における前記開口部を構成する部分の表面に曝露する空孔には、前記微粒子が充填されていることを特徴とする半導体装置。 - 前記開口部の内部には、前記多孔質低誘電率膜との間に前記微粒子体膜が介在するように、ビア又は配線となる導電性材料が埋め込まれていることを特徴とする請求項1に記載の半導体装置。
- 少なくとも前記導電性材料と前記微粒子体膜との間には、バリア膜が介在していることを特徴とする請求項2に記載の半導体装置。
- 前記導電性材料はCuであることを特徴とする請求項2に記載の半導体装置。
- 前記微粒子は、フラーレン又は二酸化ケイ素よりなることを特徴とする請求項1に記載の半導体装置。
- 基板上に多孔質低誘電率膜を形成する工程(a)と、
前記多孔質低誘電率膜に開口部を形成する工程(b)と、
前記多孔質低誘電率膜における前記開口部を構成する部分の表面に、各々の直径が1nm以上であって且つ2nm以下である複数の微粒子を含む溶液を塗布した後、前記溶液における溶媒を除去することにより、前記複数の微粒子が集積されてなる微粒子体膜を形成する工程(c)とを備えることを特徴とする半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005228769A JP4630756B2 (ja) | 2005-08-05 | 2005-08-05 | 半導体装置及びその製造方法 |
US11/492,007 US7339270B2 (en) | 2005-08-05 | 2006-07-25 | Semiconductor device and method for fabricating the same |
US12/007,071 US7566976B2 (en) | 2005-08-05 | 2008-01-07 | Semiconductor device and method for fabricating the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005228769A JP4630756B2 (ja) | 2005-08-05 | 2005-08-05 | 半導体装置及びその製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2007048785A true JP2007048785A (ja) | 2007-02-22 |
JP2007048785A5 JP2007048785A5 (ja) | 2008-02-21 |
JP4630756B2 JP4630756B2 (ja) | 2011-02-09 |
Family
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Family Applications (1)
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JP2005228769A Expired - Fee Related JP4630756B2 (ja) | 2005-08-05 | 2005-08-05 | 半導体装置及びその製造方法 |
Country Status (2)
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US (2) | US7339270B2 (ja) |
JP (1) | JP4630756B2 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070278682A1 (en) * | 2006-05-31 | 2007-12-06 | Chung-Chi Ko | Self-assembled mono-layer liner for cu/porous low-k interconnections |
US7466027B2 (en) * | 2006-09-13 | 2008-12-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structures with surfaces roughness improving liner and methods for fabricating the same |
US7928570B2 (en) * | 2009-04-16 | 2011-04-19 | International Business Machines Corporation | Interconnect structure |
US8236645B1 (en) * | 2011-02-07 | 2012-08-07 | GlobalFoundries, Inc. | Integrated circuits having place-efficient capacitors and methods for fabricating the same |
RU2486632C2 (ru) * | 2011-07-20 | 2013-06-27 | Открытое акционерное общество "НИИ молекулярной электроники и завод "Микрон" | Способ изготовления усовершенствованной многоуровневой медной металлизации с применением диэлектриков с очень низкой диэлектрической постоянной (ultra low-k) |
US9613906B2 (en) * | 2014-06-23 | 2017-04-04 | GlobalFoundries, Inc. | Integrated circuits including modified liners and methods for fabricating the same |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003347403A (ja) * | 2002-05-30 | 2003-12-05 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2004193326A (ja) * | 2002-12-11 | 2004-07-08 | Sony Corp | 配線構造およびその製造方法 |
JP2004259753A (ja) * | 2003-02-24 | 2004-09-16 | Fujitsu Ltd | 半導体装置およびその製造方法 |
US20050077597A1 (en) * | 2003-10-10 | 2005-04-14 | Tokyo Electron Limited | Method and system for treating a dielectric film |
JP2005166716A (ja) * | 2003-11-28 | 2005-06-23 | Tokyo Electron Ltd | 絶縁膜の形成方法及び絶縁膜形成システム |
JP2005209901A (ja) * | 2004-01-23 | 2005-08-04 | Semiconductor Leading Edge Technologies Inc | 半導体装置及び半導体装置の製造方法 |
Family Cites Families (10)
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JP3888794B2 (ja) * | 1999-01-27 | 2007-03-07 | 松下電器産業株式会社 | 多孔質膜の形成方法、配線構造体及びその形成方法 |
JP3236576B2 (ja) * | 1999-03-24 | 2001-12-10 | キヤノン販売株式会社 | 層間絶縁膜の形成方法、化学的気相成長装置、及び半導体装置 |
US6396122B1 (en) * | 2000-09-08 | 2002-05-28 | Newport Fab, Llc | Method for fabricating on-chip inductors and related structure |
US6528409B1 (en) * | 2002-04-29 | 2003-03-04 | Advanced Micro Devices, Inc. | Interconnect structure formed in porous dielectric material with minimized degradation and electromigration |
US6964919B2 (en) * | 2002-08-12 | 2005-11-15 | Intel Corporation | Low-k dielectric film with good mechanical strength |
TWI257120B (en) * | 2003-06-18 | 2006-06-21 | Fujitsu Ltd | Method for manufacturing semiconductor device |
US7157373B2 (en) * | 2003-12-11 | 2007-01-02 | Infineon Technologies Ag | Sidewall sealing of porous dielectric materials |
KR100590386B1 (ko) * | 2004-04-20 | 2006-06-19 | 매그나칩 반도체 유한회사 | 반도체 소자의 금속배선 형성 방법 |
US7015150B2 (en) * | 2004-05-26 | 2006-03-21 | International Business Machines Corporation | Exposed pore sealing post patterning |
US7517791B2 (en) * | 2004-11-30 | 2009-04-14 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
-
2005
- 2005-08-05 JP JP2005228769A patent/JP4630756B2/ja not_active Expired - Fee Related
-
2006
- 2006-07-25 US US11/492,007 patent/US7339270B2/en not_active Expired - Fee Related
-
2008
- 2008-01-07 US US12/007,071 patent/US7566976B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003347403A (ja) * | 2002-05-30 | 2003-12-05 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2004193326A (ja) * | 2002-12-11 | 2004-07-08 | Sony Corp | 配線構造およびその製造方法 |
JP2004259753A (ja) * | 2003-02-24 | 2004-09-16 | Fujitsu Ltd | 半導体装置およびその製造方法 |
US20050077597A1 (en) * | 2003-10-10 | 2005-04-14 | Tokyo Electron Limited | Method and system for treating a dielectric film |
JP2007517380A (ja) * | 2003-10-10 | 2007-06-28 | 東京エレクトロン株式会社 | 誘電体膜を処理するための方法とシステム |
JP2005166716A (ja) * | 2003-11-28 | 2005-06-23 | Tokyo Electron Ltd | 絶縁膜の形成方法及び絶縁膜形成システム |
JP2005209901A (ja) * | 2004-01-23 | 2005-08-04 | Semiconductor Leading Edge Technologies Inc | 半導体装置及び半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US7566976B2 (en) | 2009-07-28 |
US20080122112A1 (en) | 2008-05-29 |
US7339270B2 (en) | 2008-03-04 |
JP4630756B2 (ja) | 2011-02-09 |
US20070032068A1 (en) | 2007-02-08 |
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