CN101523585B - 增强的互连结构 - Google Patents

增强的互连结构 Download PDF

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CN101523585B
CN101523585B CN2007800379393A CN200780037939A CN101523585B CN 101523585 B CN101523585 B CN 101523585B CN 2007800379393 A CN2007800379393 A CN 2007800379393A CN 200780037939 A CN200780037939 A CN 200780037939A CN 101523585 B CN101523585 B CN 101523585B
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C-c·杨
H·S·杨
K·K·H·沃恩格
M·G·法奥奎
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Abstract

本发明提供一种半导体互连结构，该互连结构在帽层(61)、底层电介质层(12)和扩散阻挡层(31)的界面处具有改进的机械强度。该互连结构具有嵌入在该帽层材料(61)中的扩散阻挡材料(31)的一部分(41)。该阻挡(31)可以部分或者完全嵌入在该帽层(61)中。

Description

增强的互连结构
技术领域
本发明涉及半导体集成电路(IC)，且更具体而言，涉及具有增强互连的机械强度和可靠性的改良结构的后道(BEOL)互连。本发明还涉及用于制作包含这种改良互连结构的半导体IC结构的方法。
背景技术
嵌入(Damascene)工艺是形成诸如半导体器件中的线或过孔这样的金属特征的众所周知的方法。在典型的嵌入工艺中，将电介质层沉积在衬底上且将电介质的一部分依照掩膜图形蚀刻掉。利用阻挡金属对电介质层中的蚀刻区域进行加衬且然后利用金属对其进行填充。电介质层之上沉积的过剩的衬垫和金属在平坦化工艺中去除。
过孔和线可以在已知为单嵌入的独立嵌入工艺中形成。为了在衬底上形成一层金属线，沉积电介质层且将该电介质层的一部分依照对应于所需线图形的掩膜图形蚀刻掉。然后将金属衬垫沉积在该电介质层上和该电介质层的蚀刻线区域中。然后用金属填充蚀刻的线区域且在平坦化工艺中去除该电介质层顶部上的过剩金属和衬垫。使用对应于所需过孔图形的掩膜图形，在相似的工艺中形成一层过孔或垂直连接。在单嵌入工艺中，为形成一层过孔和线，需要两个金属填充步骤和两个平坦化步骤。
过孔和线还可以在双嵌入工艺中形成。将较厚的电介质层沉积在衬底上且根据对应于所需过孔图形和所需线图形的掩膜图形蚀刻该电介质层。将衬垫沉积在该电介质层上和该层的蚀刻区域中。利用金属填充蚀刻的区域且通过平坦化工艺去除过剩的金属和衬垫。
图1A-1D示出了各种现有技术的双嵌入结构。示出的每一个双嵌入结构包括第一电介质100，该第一电介质100包括垂直于纸面延伸的金属互连或线110。互连110被(多个)扩散阻挡材料105环绕，且在第一电介质100的表面上还存在第一图形化帽层120。第二电介质130位于第一帽层120的顶部。该第二电介质130具有形成于其中的双嵌入孔径，该孔径包括下部148和上部150。下部148在本领域中称为过孔，而上部150在本领域中称为线。
每一层中使用的电介质典型地包括二氧化硅、热固性聚芳树脂、有机硅酸盐玻璃(诸如掺碳的氧化物(SiCOH))或者任意其他类型的混合相关电介质。过孔148与底层互连110接触，而线150延伸相当大的距离以根据需要通过特定设计布局与IC的其他元件接触。在附图中，过孔148底部处帽层120的部分通常通过与蚀刻第二电介质130的方法不同的蚀刻化学方法去除。图形化的硬掩膜122位于第二电介质130的顶部。
在现有技术中，通常在金属化之前在该结构的整个内部沉积衬垫140。衬垫140和105可以是如图1A和图1C所示的单层，或如图1B和图1D所示的多层140、145和105、106。在图1C和图1D中，衬垫140不位于过孔148的底部水平面上。衬垫140、145包括诸如Ta、Ti、Ru、Ir和W的难熔金属或者诸如TaN、TiN和WN的难熔金属氮化物。没有特别示出的可选的粘合层可用于增强衬垫与第二电介质层130的接合。然后沉积诸如Al、W、Cu或其合金的导电材料(没有特别示出)，使得完全填充孔径，提供导电填充的过孔和导电填充的线。
图1A-1D中示出的现有技术互连结构的一个问题在于，难以在正常芯片工作温度下获得良好的机械接触。随着Cu互连中持续的尺度缩小和低K电介质的引入，除增加工艺复杂度之外，可靠性问题变成更大的顾虑。另外，现有技术互连结构在可靠性测试中经常呈现开路或高电阻接合。
参考图1A，观察到衬垫105/帽层120/电介质界面100(“三点结”)是机械弱点，且涉及如图1E所示的可靠性相关问题。随着IC尺寸变得越来越小，任由铜扩散和短路的电介质击穿故障是变得越来越关键的可靠性顾虑。观察到，在正常电路工作条件期间，Cu原子可以扩散通过Cu/帽层界面。
该界面的弱机械强度可能导致Cu扩散到电介质中且导致电路可靠性劣化。随着相邻互连之间的间隔减小，电介质击穿变得越来越恶劣。另外，众所周知，在电场的影响下，当缺少阻挡材料时，Cu离子会容易地扩散到电介质中。已观察到，在正常电路工作条件下，Cu离子会沿着Cu/帽层界面扩散到电介质中。
因此，需要提供避免上述问题的新的和改进的互连结构。即，需要一种互连结构，其在正常芯片工作期间具有且维持良好的机械接触，且在诸如热循环和高温烘焙的各种可靠性测试期间不会失效。
因此，本发明的一个目的是提供一种增强互连的可靠性的结构。本发明的另一目的是提供一种在Cu帽层材料中嵌入有Cu扩散阻挡材料的新颖的互连结构。本发明的另一目的是提供用于创建这种新颖互连结构的制作方法。
发明内容
本发明提供一种互连结构，其包括：电介质层，其中嵌入有至少一个导电互连；扩散阻挡层，环绕该导电互连且与该电介质层和该导电互连接触；电介质帽层，与该电介质层和导电互连接触；以及延伸到该电介质帽层中的该扩散阻挡层的一部分。
在优选实施例中，延伸到该帽层中的该扩散阻挡层的部分可以仅延伸到该电介质帽层的一部分中。在另一优选实施例中，延伸到该帽层中的该扩散阻挡层的部分延伸到该电介质帽层的整个厚度中。
该导电互连特征可以是线和/或过孔且优选地是Cu、W、Al或其合金。该电介质层优选地具有约
Figure G2007800379393D00031
至约
Figure G2007800379393D00032
的厚度。该扩散阻挡层优选地是Ta、TaN、Ti、TiN、Ru、RuN、RuTa、RuTaN、W或WN。
该扩散阻挡层优选地具有约4nm至约40nm的厚度。该电介质帽层优选地是Si3N4、SiC、SiCN、SiC(N，H)或SiCH。该扩散阻挡层延伸到电介质帽层中的部分优选地具有约5nm至约100nm的高度。
本发明还提供一种用于形成互连结构的方法，该方法包括以下步骤：在电介质层上沉积牺牲电介质膜；在该电介质层中形成图形化特征；在该图形化特征中沉积扩散阻挡层；在该扩散阻挡层上沉积导电金属以形成互连特征；去除导电金属的一部分；去除该牺牲电介质膜；以及沉积电介质帽层，由此在该电介质帽层中嵌入该扩散阻挡层的一部分中。
该扩散阻挡层优选地通过物理气相沉积、原子层沉积或化学气相沉积来沉积。该导电互连特征优选地通过镀覆或溅射来沉积。部分导电金属优选地使用湿法蚀刻去除。在优选实施例中，湿法蚀刻是在由包括HNO3、HCL、H2SO4、HF及其组合的蚀刻溶液中的时间受控浸泡。
该牺牲电介质膜优选地使用湿法蚀刻去除。在优选实施例中，该湿法蚀刻是稀释的HF溶液。该电介质帽层优选地通过CVD沉积来沉积。
附图说明
相信是新颖的本发明的特征和本发明的元件特性特别在所附权利要求书中申明。附图仅用于阐释目的且没有按比例绘制。不过，通过下面结合附图的详述可以更好地理解本发明本身，无论是结构还是其工作方法，附图中：
图1A-1D是示出常规嵌入结构的示意性剖面图。
图1E是机械弱界面的示意性剖面图。
图2至图10是示出根据本发明的优选结构的示意性剖面图。
具体实施方式
参考图2，示出了沉积在层间电介质(ILD)层12上的牺牲电介质膜11(通常也称为“硬掩膜”)。在优选实施例中，牺牲电介质膜11是Si3N4或SiO2。电介质层12可以包含任意层间或层内电介质，包括无机电介质或有机电介质。电介质材料12可以是多孔或无孔的。可用作电介质材料的合适电介质的某些示例包括但不限于：SiO2、倍半硅氧烷、包括Si、C、O和H原子的掺碳氧化物(即，有机硅酸盐)、热固聚芳树脂或其多层。术语“聚芳”用于表示芳基半族或者通过键、稠环或惰性链接族(例如氧、硫、砜、亚砜、羰基等)链接在一起的惰性取代芳基半族。优选地，牺牲膜11具有
Figure G2007800379393D00051
至
Figure G2007800379393D00052
的厚度。优选地，ILD层12具有
Figure G2007800379393D00053
至的厚度。
参考图3，图形化特征21通过常规光刻和蚀刻工艺在ILD层12中形成。依赖于是使用单嵌入还是双嵌入结构，这些图形化特征将对应于后续的互连过孔或线。
光刻步骤包括：向牺牲电介质膜11的表面涂敷光致抗蚀剂，使该光致抗蚀剂曝光于所需辐射图形，以及利用常规抗蚀剂显影剂显影曝光的抗蚀剂。蚀刻步骤可以包括干法蚀刻工艺、湿法化学蚀刻工艺或其组合。术语“干法蚀刻”此处用于表示诸如反应离子蚀刻(RIE)、离子束蚀刻、等离子蚀刻或激光熔融的蚀刻技术。在蚀刻工艺中，图形首先被转移到牺牲电介质膜11且然后转移到电介质材料12。在图形被转移到牺牲电介质膜11之后，图形化光致抗蚀剂典型地但不必需地从该结构去除。
形成于电介质材料12中的图形化特征21可以包括线开口、过孔开口或者线开口与过孔开口的组合。依赖于形成的开口的类型，适当时可以使用单嵌入或双嵌入工艺。可以使用先过孔后线开口的工艺，或者可以使用先线后过孔开口的工艺。
参考图4，示出了在沉积了扩散阻挡层31和导电互连特征32并经过了化学机械抛光(CMP)之后的结构。依赖于是使用单嵌入还是双嵌入结构，导电互连特征32是互连过孔和/或线。扩散阻挡层31典型地通过物理气相沉积(PVD)、原子层沉积(ALD)或化学气相沉积(CVD)技术沉积。导电互连特征32优选地是镀覆的Cu。
可包含Ta、TaN、Ti、TiN、Ru、RuN、RuTa、RuTaN、W、WN或可用作阻挡层以防止导电材料扩散通过的任意其他材料的扩散阻挡层31通过沉积工艺形成，例如，通过原子层沉积(ALD)、化学气相沉积(CVD)、等离子增强化学气相沉积(PECVD)、溅射、化学溶液沉积或镀覆形成。扩散阻挡层31的厚度可以根据沉积工艺的具体方法以及采用的材料而变化。典型地，扩散阻挡层31具有约4nm至约40nm的厚度，更为典型地具有约7nm至约20nm的厚度。
在扩散阻挡层31形成之后，利用导电材料填充电介质材料12中的每个开口21的剩余区域，由此形成导电互连特征32。在形成导电互连特征32中使用的导电材料例如包括多晶硅、导电金属、包括至少一种导电金属的合金、导电金属硅化物或其组合。优选地，在形成导电互连特征32中使用的导电材料是诸如Cu、W或Al的导电金属，在本发明中，Cu或Cu合金(诸如AlCu)是优选实施例。使用常规沉积工艺，将导电材料填充到电介质材料12中的凹陷特征21中，该常规沉积工艺包括但不限于：CVD、PECVD、溅射、化学溶液沉积或镀覆。
在沉积导电材料之后，可以使用诸如化学机械抛光(CMP)的常规平坦化工艺来提供这样的结构，其中扩散阻挡层31和导电互连32均具有基本与电介质材料12的上表面共面的上表面。所得的结构例如在图4中示出。
参考图5，示出了在湿法蚀刻之后形成的Cu互连特征32的凹陷的结构。优选地，所述湿法蚀刻是蚀刻溶液中的时间受控浸泡。优选的蚀刻溶液包括HNO3、HCL、H2SO4、HF或其组合。如图5所示，仅Cu互连32将被蚀刻，且牺牲电介质膜11或扩散阻挡层31不被蚀刻。
现在参考图6，示出了牺牲电介质膜11的去除。优选地，这使用湿法蚀刻完成。在优选实施例中，湿法蚀刻是稀释的HF溶液。如图6的剖面图所示，Cu互连特征32将被在ILD层12之上凸出的扩散阻挡层31的部分41环绕。依赖于使用单嵌入还是双嵌入结构，该凸出部分41将环绕Cu互连过孔或线。在优选实施例中，ILD层12之上凸出的部分41的高度为约5nm至约100nm，宽度将等于扩散阻挡层31的沉积厚度。
如图5和图6所示，使第一湿法蚀刻适于蚀刻Cu互连。使第二湿法蚀刻适于仅蚀刻牺牲电介质膜11。
现在参考图7，示出了电介质帽层61的沉积。在优选实施例中，电介质帽层61是Si3N4、SiC、SiCN、SiC(N，H)或SiCH。电介质帽层61优选地通过CVD沉积或旋涂技术沉积。如图6所示，电介质帽层61的厚度大于ILD层12之上凸出的部分41的高度。这导致扩散阻挡层31的一部分即ILD层12之上凸出的部分41部分地嵌入到电介质帽层61中。
现在参考图8，示出了本发明的另一实施例。在该实施例中，执行可选的CMP步骤，以去除电介质帽层61的一部分厚度，以使得电介质帽层61的表面与ILD层12之上凸出的扩散阻挡层31的部分41齐平。这导致扩散阻挡层31的部分41完全嵌入在电介质帽层61中，如图8所示。
现在参考图9，示出了用于下一级互连构建的ILD层71的沉积。图8示出了扩散阻挡层31的一部分即ILD层12之上凸出的部分41仅部分地嵌入到电介质帽层61中的实施例。图10示出了用于下一级互连构建的ILD层71的沉积，其中ILD层12之上凸出的部分41完全嵌入到电介质帽层61中。
对于注意到本公开的本领域技术人员而言，很明显，可以在不偏离本发明的精神的情况下，做出此处特别描述的实施例之外的本发明的其他修改。因此，这些修改被视为处于仅由所附权利要求限定的本发明的范围内。
工业应用性
本发明在半导体集成电路及其制造中是有用的，且在后道(BEOL)互连结构中是尤其有用的。

Claims (20)

1.一种半导体器件，包括：
互连结构，所述互连结构具有其中嵌入有至少一个导电互连(32)的电介质层(12)；
扩散阻挡层(31)，环绕所述至少一个导电互连(32)且与所述电介质层(12)和所述至少一个导电互连(32)接触；
电介质帽层(61)，与所述电介质层(12)和所述至少一个导电互连(32)接触；以及
延伸到所述电介质帽层(61)中的所述扩散阻挡层(31)的一部分(41)。
2.根据权利要求1所述的半导体器件，其中延伸到所述帽层(61)中的所述扩散阻挡层(31)的所述部分(41)仅延伸到所述电介质帽层(61)的一部分中。
3.根据权利要求1所述的半导体器件，其中延伸到所述帽层(61)中的所述扩散阻挡层(31)的所述部分(41)延伸到所述电介质帽层(61)的整个厚度中。
4.根据权利要求1所述的半导体器件，其中所述至少一个导电互连(32)包括线和过孔。
5.根据权利要求1所述的半导体器件，其中所述至少一个导电互连(32)由选自Cu、W、Al及其合金的材料组成。
6.根据权利要求1所述的半导体器件，其中所述电介质层(12)具有
Figure FSB00000549268000011
至
Figure FSB00000549268000012
的厚度。
7.根据权利要求1所述的半导体器件，其中所述扩散阻挡层(31)由选自Ta、TaN、Ti、TiN、Ru、RuN、RuTa、RuTaN、W和WN的材料组成。
8.根据权利要求1所述的半导体器件，其中所述扩散阻挡层(31)具有4nm至40nm的厚度。
9.根据权利要求1所述的半导体器件，其中所述电介质帽层(61)由选自Si3N4、SiC、SiCN、SiC(N，H)和SiCH的材料组成。
10.根据权利要求1所述的半导体器件，其中延伸到所述电介质帽层(61)中的所述扩散阻挡层(31)的所述部分(41)具有5nm至100nm的高度。
11.一种用于形成互连结构的方法，包括以下步骤：
在电介质层(12)上沉积牺牲电介质膜(11)；
在所述电介质层(12)中形成图形化凹陷特征(21)；
在所述凹陷特征(21)中沉积扩散阻挡层(31)；
在所述扩散阻挡层(31)上沉积导电金属(32)以形成互连特征(32)；
去除所述导电金属(32)的一部分；
去除所述牺牲电介质膜(11)；以及
沉积电介质帽层(61)，由此在所述电介质帽层(61)中嵌入所述扩散阻挡层(31)的一部分(41)。
12.根据权利要求11所述的方法，其中所述扩散阻挡层(31)通过物理气相沉积来沉积。
13.根据权利要求11所述的方法，其中所述扩散阻挡层(31)通过化学气相沉积或原子层沉积来沉积。
14.根据权利要求11所述的方法，其中所述互连特征(32)通过镀覆沉积。
15.根据权利要求11所述的方法，其中所述互连特征(32)通过溅射沉积。
16.根据权利要求11所述的方法，其中所述导电金属(32)的所述部分使用湿法蚀刻去除。
17.根据权利要求16所述的方法，其中所述湿法蚀刻是在由包括HNO3、HCL、H2SO4、HF及其组合的蚀刻溶液中的时间受控浸泡。
18.根据权利要求11所述的方法，其中所述牺牲电介质膜(11)使用湿法蚀刻去除。
19.根据权利要求18所述的方法，其中所述湿法蚀刻是稀释的HF溶液。
20.根据权利要求11所述的方法，其中所述电介质帽层(61)通过CVD沉积来沉积。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7687877B2 (en) * 2008-05-06 2010-03-30 International Business Machines Corporation Interconnect structure with a mushroom-shaped oxide capping layer and method for fabricating same
US8659173B1 (en) 2013-01-04 2014-02-25 International Business Machines Corporation Isolated wire structures with reduced stress, methods of manufacturing and design structures
CN103972156B (zh) * 2013-02-06 2016-09-14 中芯国际集成电路制造(上海)有限公司 半导体互连结构及其制作方法
US20150228585A1 (en) * 2014-02-10 2015-08-13 Globalfoundries Inc. Self-forming barrier integrated with self-aligned cap
US10431464B2 (en) 2016-10-17 2019-10-01 International Business Machines Corporation Liner planarization-free process flow for fabricating metallic interconnect structures
US10672653B2 (en) 2017-12-18 2020-06-02 International Business Machines Corporation Metallic interconnect structures with wrap around capping layers
US10699945B2 (en) * 2018-10-04 2020-06-30 International Business Machines Corporation Back end of line integration for interconnects

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6096659A (en) * 1998-04-13 2000-08-01 Advanced Micro Devices, Inc. Manufacturing process for reducing feature dimensions in a semiconductor
US6475929B1 (en) * 2001-02-01 2002-11-05 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer producing diffusion to an adjacent low-k dielectric layer lowering the constant

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5098860A (en) * 1990-05-07 1992-03-24 The Boeing Company Method of fabricating high-density interconnect structures having tantalum/tantalum oxide layers
US5933753A (en) * 1996-12-16 1999-08-03 International Business Machines Corporation Open-bottomed via liner structure and method for fabricating same
US5930669A (en) * 1997-04-03 1999-07-27 International Business Machines Corporation Continuous highly conductive metal wiring structures and method for fabricating the same
US6291876B1 (en) * 1998-08-20 2001-09-18 The United States Of America As Represented By The Secretary Of The Navy Electronic devices with composite atomic barrier film and process for making same
JP3048567B1 (ja) * 1999-02-18 2000-06-05 沖電気工業株式会社 半導体装置の製造方法
JP2002329780A (ja) * 2001-04-27 2002-11-15 Hitachi Ltd 半導体装置の製造方法および半導体装置
KR20020090441A (ko) * 2001-05-25 2002-12-05 주식회사 하이닉스반도체 반도체 소자의 구리배선 형성방법
JP2003188254A (ja) * 2001-12-18 2003-07-04 Hitachi Ltd 半導体装置の製造方法および半導体装置
US7687917B2 (en) * 2002-05-08 2010-03-30 Nec Electronics Corporation Single damascene structure semiconductor device having silicon-diffused metal wiring layer
US20050239395A1 (en) 2002-08-01 2005-10-27 Gerard Delegue Method for providing a set of basic services for using a telecommunicaiton network
US20040108136A1 (en) * 2002-12-04 2004-06-10 International Business Machines Corporation Structure comprising a barrier layer of a tungsten alloy comprising cobalt and/or nickel
KR100632622B1 (ko) * 2002-12-26 2006-10-09 주식회사 하이닉스반도체 반도체 소자의 금속배선 형성방법
DE10339990B8 (de) * 2003-08-29 2013-01-31 Advanced Micro Devices, Inc. Verfahren zur Herstellung einer Metallleitung mit einer erhöhten Widerstandsfähigkeit gegen Elektromigration entlang einer Grenzfläche einer dielektrischen Barrierenschicht mittels Implantieren von Material in die Metalleitung
JP4266901B2 (ja) * 2003-09-30 2009-05-27 三洋電機株式会社 半導体装置およびその製造方法
WO2005034234A1 (ja) * 2003-10-02 2005-04-14 Fujitsu Limited 半導体装置及びその製造方法
US20050112957A1 (en) * 2003-11-26 2005-05-26 International Business Machines Corporation Partial inter-locking metal contact structure for semiconductor devices and method of manufacture
US7088003B2 (en) * 2004-02-19 2006-08-08 International Business Machines Corporation Structures and methods for integration of ultralow-k dielectrics with improved reliability
US20050239295A1 (en) * 2004-04-27 2005-10-27 Wang Pei-L Chemical treatment of material surfaces
JP2006165039A (ja) * 2004-12-02 2006-06-22 Renesas Technology Corp 半導体装置の製造方法
US7749896B2 (en) * 2005-08-23 2010-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method for forming the same
KR100720531B1 (ko) * 2005-12-29 2007-05-22 동부일렉트로닉스 주식회사 반도체 소자의 금속배선 및 그의 형성방법
US7666781B2 (en) * 2006-11-22 2010-02-23 International Business Machines Corporation Interconnect structures with improved electromigration resistance and methods for forming such interconnect structures
US7745324B1 (en) * 2009-01-09 2010-06-29 International Business Machines Corporation Interconnect with recessed dielectric adjacent a noble metal cap

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6096659A (en) * 1998-04-13 2000-08-01 Advanced Micro Devices, Inc. Manufacturing process for reducing feature dimensions in a semiconductor
US6475929B1 (en) * 2001-02-01 2002-11-05 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer producing diffusion to an adjacent low-k dielectric layer lowering the constant

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