200428582 五、發明說明（1) 【發明所屬之技術領域】 本發明係關於一種半導體製造方法，尤指於避免破 電係數材質的雙嵌刻（dual damascene)開口之製造 【先前技術】 進入超大型積體電路的時代後，是需要藉由多層金 結構才能滿足複雜之連接線路的設計。相鄰之金屬 間係藉由低介電係數之介電層作電性隔離，以防止 短路發生。在金屬間之介電層内形成若干的介層窗 以作為頂層金屬溝渠（trench)與底層金屬層連接之 述溝渠又可稱為連接線（interc〇nnect)。然而，實 上常發生溝渠與介層窗無法準確對準的問題。進而 屬層間連接之阻值提高，而無法達到產品高速運作 求。因此，為消除上述無法準確對準的問題，而提 藉由分別形成一介層窗和一溝渠而製作出的一種稱 嵌刻（dual damascene)結構。並且，隨著密度更高 佈局’其介電質之低介電性更顯得重要。 請參閱第1 A〜1E圖，第1 A〜1£圖為習知製作雙嵌刻開 面步驟圖。首先在一半導體基底1〇上完成各電子元 繪），如：電晶體。接著，再利用例如化學氣相形文 的方式，形成一第一介電層丨2於半導體基底1〇上。j 電層12之介電係數需要為低介電係數材料（約低於 壞低介 方法。 屬圖案 圖案層 不當的# (via)， 用。上 際製程 導致金 的要 出一種 之為雙 的電路 口之剖❸ 件（未描 良（CVD) 第一介 3.0)， 200428582 五、發明說明（2) 藉以防止不當的短路發生。接著，披覆一抗反射介電層 14(dielectric anti-Reflective coatings, DARC)於第一 * 介電層12上，藉以防止第一介電層丨2之表面反光而影響之 後光阻曝光步驟的準確度。然後進行介層窗光罩之曝光、 顯影並#刻抗反射介電層1 4和第一介電層1 2，形成如第1a 圖所示之介層窗開口 1 6。然後，如第丨B圖所示，於抗反射 介電層1 4上塗佈一層光阻層1 8 ( PR )以及同時將介層窗内填 滿光阻層1 8。之後’進行溝渠光罩曝光、顯影而形成第一 溝渠開口 2 0，如第1 C圖所示。再以活性離子蝕刻第一介電 層1 2，形成如第1 D圖所示之第二溝渠開口 2 2。最後，除去暴 原先塗佈於抗反射介電層1 4上的光阻層1 8以及介層窗内所 充填的光阻層1 8，完成如第1 E圖所示之雙嵌刻開口 2 4。 然而’上述的方法中光阻1 8與第一介電層1 2有直接接觸， 而導致低介電質的第一介電層1 2與光阻1 8起反應，使得產 生較差的曝光、顯影效果，而有殘留光阻於介層窗開口表 面附近。此外，由於上述方法中，介層窗填滿光阻後需要 去除光阻過程時，也會因破壞第一介電層的分子結構導致 電係數提兩’並且’光阻也會殘留於介層窗的角落 (corner)之中，提高介層窗的阻值。200428582 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing semiconductors, and particularly to the manufacture of dual damascene openings made of a material with a breaking coefficient [prior art] Entering a very large After the era of integrated circuits, it was necessary to meet the design of complex connection lines through a multilayer gold structure. Adjacent metals are electrically isolated by a low-k dielectric layer to prevent short circuits. A plurality of dielectric windows are formed in the dielectric layer between the metals, and the trenches which are connected to the bottom metal layer as the top metal trench are also called interconnects. However, in fact, the problem that the trench and the interlayer window cannot be accurately aligned often occurs. Furthermore, the resistance value of the inter-layer connection is increased, and the high-speed operation of the product cannot be achieved. Therefore, in order to eliminate the above-mentioned problem of inaccurate alignment, a dual damascene structure is formed by forming a via window and a trench respectively. Moreover, with a higher density layout, its low dielectricity becomes more important. Please refer to Figures 1A ~ 1E, and Figures 1A ~ 1 £ are the steps for making a double-inset engraved surface. First complete the drawing of each electronic element on a semiconductor substrate 10), such as a transistor. Next, a method such as chemical vapor inscription is used to form a first dielectric layer 2 on the semiconductor substrate 10. The dielectric constant of the electric layer 12 needs to be a low dielectric constant material (about lower than the bad low dielectric method. It belongs to the pattern pattern layer inappropriate # (via), which is used. The upper process causes the gold to be produced in one way and the other is double. Cutaway of Circuit Port (CVD) First Medium 3.0, 200428582 V. Description of the Invention (2) To prevent improper short circuit. Then, cover an anti-reflective dielectric layer 14 (dielectric anti-Reflective coatings, DARC) on the first * dielectric layer 12 to prevent the surface reflection of the first dielectric layer 2 from affecting the accuracy of the subsequent photoresist exposure step. Then the exposure of the dielectric window mask, development and # Engraving the anti-reflection dielectric layer 14 and the first dielectric layer 12 to form a dielectric window opening 16 as shown in Fig. 1a. Then, as shown in Fig. 丨 B, the anti-reflection dielectric layer 1 4 is formed. Apply a photoresist layer 18 (PR) on top and fill the interlayer window with photoresist layer 18 at the same time. After that, the trench mask is exposed and developed to form the first trench opening 20, as shown in FIG. 1C. The first dielectric layer 12 is then etched with active ions to form a second trench as shown in FIG. 1D. 2 2. Finally, remove the photoresist layer 18 previously coated on the anti-reflective dielectric layer 14 and the photoresist layer 18 filled in the dielectric window to complete the double-embedding as shown in FIG. 1E. Engraved opening 2 4. However, in the above method, the photoresist 18 is in direct contact with the first dielectric layer 12 and the low-dielectric first dielectric layer 12 and the photoresist 18 are reacted, so that Produces poor exposure and development effects, and there is residual photoresist near the opening surface of the interlayer window. In addition, in the above method, when the photoresist needs to be removed after the interlayer window is filled with photoresist, it will also damage the first dielectric The molecular structure of the electrical layer causes the electric coefficient to increase by two and the photoresist will also remain in the corners of the interlayer window, increasing the resistance of the interlayer window.
II 【發明内容】 本發明的主要目的在於提供一種避免因光阻與介電層有直 接接觸所導致的較差的曝光、顯影效果而殘留的光阻。II [Summary of the Invention] The main object of the present invention is to provide a photoresist that is left out due to poor exposure and development effects caused by direct contact between the photoresist and the dielectric layer.
第7頁 200428582 五、發明說明（3) 而導致 層窗的 ’係用 層内， 法，首 抗反射 層窗 L介電層 窗開 空洞。 圖案4匕 表面。 射介電 及所附 Φ 提 本 角 依 以 並 先 c-目的在於提供一種避免去除 徒同介電層之介電係數。 狂 另一目的在於提供一種避免光阻殘留於介 述的目的，本發明提供一種半導體製造方法 表k 一雙後刻（dual damascene)開口於一層介電 且此介電層係形成於基材上。本發明所揭露的方 ’將一第一介電層形成於前述基材上。接著，一 電層形成於前述第一介電層上。接著，形成一介 C,v i、a)於抗反射介電層和第一介電層内。接著，第;|二 形成於抗反射介電層，並且第二介電層封閉住介層 口三此介層窗係被封閉並且於該介層窗内形成一; 接著’形成一圖案化光阻層於第二介電層上，並且 光阻層並未遮掩住封閉介層窗開口的第二介電層上 最後，移除未遮掩住的第二介電層以及其下的&反 層和第一介電層，以形成雙嵌刻開口。 關於本發明之優點與精神可以藉由以下的發明詳述 圖式得到進一步的瞭解。 一 實施方式】 請參閱第2A〜2F圖，第2A〜2F圖為本發明製作雙嵌刻（仏以 famascene)開口之剖面步驟圖。運用本發明之方法製造雙 嵌刻開口（由一介層窗和一溝渠所組成）開口時，首先在一Page 7 200428582 V. Description of the invention (3) The layer window's use of the in-layer method, the first anti-reflection layer window, the L dielectric layer window, has holes. Patterned 4 dagger surface. The dielectric and attached Φ extraction angle are based on and first c- The purpose is to provide a dielectric coefficient that avoids removing the dielectric layer. Another object is to provide a purpose of preventing photoresist from remaining in the description. The present invention provides a semiconductor manufacturing method. A dual damascene is opened in a layer of dielectric, and the dielectric layer is formed on a substrate. In the method disclosed in the present invention, a first dielectric layer is formed on the aforementioned substrate. Next, an electrical layer is formed on the first dielectric layer. Next, a dielectric C, vi, a) is formed in the anti-reflection dielectric layer and the first dielectric layer. Then, the second; | is formed in the anti-reflection dielectric layer, and the second dielectric layer closes the interlayer port. The third interlayer window is closed and forms a within the interlayer window; then 'forms a patterned light. The resist layer is on the second dielectric layer, and the photoresist layer does not cover the second dielectric layer that closes the opening of the dielectric window. Finally, the unmasked second dielectric layer and the & Layer and the first dielectric layer to form a double inscribed opening. The advantages and spirit of the present invention can be further understood by the following detailed drawings. First Embodiment] Please refer to Figs. 2A to 2F. Figs. 2A to 2F are cross-sectional steps for making a double-engraved (famascene) opening in the present invention. When the method of the present invention is used to manufacture a double engraved opening (composed of a via window and a trench), the opening is first
200428582 五、發明說明（4) 半導體基底1 0上完成各電子元件（未描繪），如：電晶體。 接著，形成一第一介電層26於半導體基底10上。接著，披 覆一抗反射介電層 28(dielectric anti 〜Refiective coatings，DARC)於第一介電層26上。然後進行介層窗 (v i a)光罩之曝光、顯影並钱刻抗反射介電層2 8和第一介電 層26，形成如弟2A圖所示之介層窗開口 30。第一介電層26 之介電係數需要為約低於3 · 〇的低介電係數材質，以防止不 當的短路發生。 ' 然後，利用如化學氣相形成（CVD)而形成一第二介電層32於 第一介電層26和介層窗開口 3〇。但由於CVD製程的特性，使 得在介層窗開口 30容易被封閉起來而於介層窗開口 3〇内形 1 一中空洞31，如，2B圖所示。其中，若利用低溫的CV])製 程可使中空洞3 1的高度大於一半的第一介電層“的厚度， 而獲得更好的封閉介層窗開口 3〇的效果。 層32之材料可選用二氧化石々 ^ 乳化矽（Si02)、氮化矽（Si D、氮氯 化矽（Si〇N)、氧碳化矽（Sinr、太山气翁功几仏,3 乳乳 ’、ύιΟ〇、石厌虱乳矽化物（si0CH)或其 任f組合，以及第二介電層32的厚度約為1〇00 A以上。八 开> 成一層如第2C圖所示的楚一 叉帘忐筮-八發麻^的第二介電層34。於第二介電層32 一介電芦1 糸為了增加對於介層窗開口 30和第 川电層2 6的保護。而繁一入 第二介電層32材質之4 =電層W材料可選用近似於 氧化矽（SiON)、氧碳化矽（ 氮 ..^ ，μ _ y、Si〇C)或其任忍組合。 接者’如第2D圖所示，开彡士、 t成圖案化的一光阻層36於第三介200428582 V. Description of the invention (4) Various electronic components (not depicted) are completed on the semiconductor substrate 10, such as transistors. Next, a first dielectric layer 26 is formed on the semiconductor substrate 10. Next, an anti-reflection dielectric layer 28 (dielectric anti-refiective coatings, DARC) is coated on the first dielectric layer 26. Exposure, development, and engraving of the anti-reflection dielectric layer 28 and the first dielectric layer 26 of the dielectric window (v i a) mask are then performed to form the dielectric window opening 30 as shown in FIG. 2A. The dielectric constant of the first dielectric layer 26 needs to be a low-dielectric constant material that is less than about 3.0 to prevent an inappropriate short circuit. 'Then, a second dielectric layer 32 is formed in the first dielectric layer 26 and the dielectric window opening 30 by, for example, chemical vapor deposition (CVD). However, due to the characteristics of the CVD process, the interstitial window opening 30 is easily closed, and the interstitial window opening 30 is internally shaped as a hollow 31, as shown in FIG. 2B. Among them, if the low-temperature CV]) process is used, the height of the hollow 31 can be greater than half the thickness of the first dielectric layer, and a better effect of closing the interstitial window opening 30 is obtained. The material of the layer 32 can be Select stone dioxide ^ emulsified silicon (Si02), silicon nitride (Si D, silicon nitrogen chloride (SiON), silicon oxycarbide (Sinr, Taishan Qi Weng Gongji, 3 milk milk ', ύιΟ〇) , Stone lice milk silicide (Si0CH) or any combination thereof, and the thickness of the second dielectric layer 32 is about 1000 A or more. Octagonal opening> As shown in Figure 2C The second dielectric layer 34 of YF is a dielectric layer 1 on the second dielectric layer 32. In order to increase the protection of the dielectric window opening 30 and the second dielectric layer 26, it is complicated. 4 of the material of the second dielectric layer 32 = the material of the electrical layer W can be similar to silicon oxide (SiON), silicon oxycarbide (nitrogen .. ^, μ_y, SiOC) or any combination thereof. As shown in FIG. 2D, a patterned photoresist layer 36 is formed on the third substrate.
第9頁 然後，依據該 電層3 4和第二 成一中繼溝渠 該介層窗開口 移光阻層3 6所 接著，利用一 3 6，而形成如 層3 6的過程， 除光阻層3 6過 且，本發明特 層窗有接觸， 介電層 4 2以及 仍保持 定義的 乾式清 第2E圖 始終不 程而導 殊的製 所以没 200428582 五、發明說明（5) 電層3 4上，並曝露出位於介層窗開口 30上方的第二介電 3 2之上表面。光阻層3 6係藉著曝光 '顯影而定義溝渠的 置。上述的製程步驟，是有別於習知如第丨A圖所示進行 ^光罩之曝光、顯影製程是在可能具有複數個介層窗的 洞之不平坦的表面上進行，本發明之溝渠光罩之曝光、 影製程是在如第2 D圖所示的第三介電層3 4之平坦表面上 行。並且，為定義溝渠所使用的光阻層36，也因前述第 介電層3 2和第三介電層3 4的阻絕而沒有直接接觸，避免 阻層36與第一介電層26直接接觸後產生反應，破壞光阻 3 6的分子結構。因此’採用本發明的方法，可以有效避 光阻層3 6的分子結構被破壞，而與先前技術相比具有較 的曝光、顯影效果，使得不會有光阻殘留在介層窗開口 面附近。 3 6所定義的該溝渠位置， 3 2直至曝露出抗反射介電 封住中空洞31的介電層區 封住狀態，所以中繼溝渠 溝渠。 潔（如電漿蝕刻）或溼式清 所不之剖面圖。並且，由 會與第一介電層2 6接觸， 致提高第一電介層之介電 作方法’使得光阻層3 6完 有殘留光阻層3 6的問題。 層 位 溝 孔 顯 進 光 層 免 佳 表 介 形 且 轉 阻 阻 去 介 蝕刻第三 層28，而 塊3 5。並 4 2可視為 潔除去光 於除去光 因此避免 係數。並 全不會與 200428582 護，因 部分也 同時去 深度淺 圖所示 渠所組 層2 6的 藉由以 本發明 施例來 能涵蓋 利範圍 轉移的溝渠位置 電層2 6，由於第 三介電層3 4可被 介電層34已去除 由於介電層區塊 介電層區塊35也 刻開口 3 8。而雙 中溝渠的部分如 面4 0和於第二介 具體實施例之詳 與精神’而並非 明之範疇加以限 變及具相等性的 内〇 五、發明說明（6) 最後，依據已 和部分第一介 此該第 因第三 除，也 ，所以 之雙嵌 成，其 傾斜底 上較佳 之特徵 對本發 各種改 的範疇 ’繼續蝕刻抗 三介電層34已 完全去除，而 ，所以第二介 3 5的厚度比所 會被去除，最 嵌刻開口 3 8係 第2F圖所示具 電層3 2的傾斜 述，係希望能 以上述所揭露 制。相反地， 安排於本發明 反射介電層28 無光阻層3 6保 第二介電層32 電層3 2也可被 欲形成的溝渠 後形成如第2F 為介層窗和溝 有於第一介電 側壁41。 更加清楚描述 的較佳具體實 其目的是希望 所欲申請之專Page 9 Then, according to the electrical layer 34 and the second relay trench, the opening of the interlayer window is moved to the photoresist layer 36, and then a 36 is used to form a process such as layer 36, removing the photoresist layer. In addition, the special-layer window of the present invention has contact, and the dielectric layer 42 and the dry-type clear 2E drawing that is still defined are always made inconsistently. Therefore, no 200428582 V. Description of the invention (5) Electrical layer 3 4 And expose the upper surface of the second dielectric 32 above the dielectric window opening 30. The photoresist layers 36 and 6 define the positions of the trenches by exposure and development. The above process steps are different from the conventional exposure of the photomask as shown in FIG. 丨 A. The development process is performed on an uneven surface that may have a plurality of vias. The trench of the present invention The exposure and shadow process of the photomask is performed on the flat surface of the third dielectric layer 34 as shown in FIG. 2D. In addition, the photoresist layer 36 used to define the trench has no direct contact due to the blocking of the aforementioned second dielectric layer 32 and the third dielectric layer 34, so as to prevent the resist layer 36 from directly contacting the first dielectric layer 26. After the reaction occurs, the molecular structure of the photoresist 36 is destroyed. Therefore, by using the method of the present invention, the molecular structure of the photoresist layer 36 can be effectively prevented from being destroyed, and compared with the prior art, it has a better exposure and development effect, so that no photoresist will remain near the opening surface of the interlayer window. . The position of the trench defined by 36, 3 2 until the anti-reflection dielectric is exposed, and the dielectric layer region sealing the hollow 31 is sealed, so the trench is relayed. Clean (such as plasma etching) or wet cleaning section. In addition, since it will be in contact with the first dielectric layer 26, the method of improving the dielectric operation of the first dielectric layer 'causes the photoresist layer 36 to have the problem of remaining the photoresist layer 36. The layer-drilling hole enters the light-emitting layer to prevent the surface from being shaped and resists the removal of the third layer 28, and the block 35. And 4 2 can be considered as removing the light and removing the light so the coefficient is avoided. It will not be protected at the same time as 200428582, because part of the trench layer layer 6 shown in the shallow depth map is also used to cover the trench position of the electrical layer 26 by using the embodiment of the present invention. The dielectric layer 34 can be removed by the dielectric layer 34 because the dielectric layer block 35 and the dielectric layer block 35 are also engraved with an opening 38. The part of the Shuangzhong ditch is as shown in Figure 40 and the details and spirit of the second embodiment of the second embodiment, but not limited to the scope of the explicit and equivalent. Fifth, the description of the invention (6) Finally, according to the already and part The first reason is that the third factor is divided into three, so it is double-embedded, and its better features on the inclined bottom are different from the scope of the present invention. 'Continue to etch the anti-dielectric layer 34 has been completely removed, and so the second The thickness ratio of the medium 35 will be removed. The most inscribed opening 3 8 is the oblique description of the electrified layer 32 shown in Figure 2F. It is hoped that it can be made as disclosed above. Conversely, the reflective dielectric layer 28, the photoresist layer 36, and the second dielectric layer 32, which are arranged in the reflective dielectric layer 32 of the present invention, can also be formed after the trenches to be formed. A dielectric sidewall 41. A better, more concrete, more specific description, the purpose of which is to
200428582 圖式簡單說明 【圖式簡單說明】 第1 A〜1 E圖為習知製作雙敌刻（dual damascene)開口之剖面 步驟圖。 第2A〜2 F圖為本發明製作雙喪刻（dual damascene)開口之剖 面步驟圖。 【元件代表符號簡單說明】 1 〇半導體基底 籲 12、26第一介電層 14、28抗反射介電層 1 6、3 0介層窗開口 1 8、3 6光阻層 2 0第一溝渠開口 2 2第二溝渠開口 2 4、3 8雙嵌刻開口 32第二介電層 34第三介電層 3 5介電層區塊 ί > 4 0傾斜底面 4 1傾斜側壁 4 2中繼溝渠200428582 Brief description of the drawings [Simplified description of the drawings] Figures 1 A to 1 E are the steps of the conventional process of making dual damascene openings. Figures 2A to 2F are cross-sectional steps for making a dual damascene opening in the present invention. [Simple description of element representative symbols] 1 0 semiconductor substrate 12, 26 first dielectric layer 14, 28 anti-reflective dielectric layer 16, 3 0 dielectric window opening 1 8, 3 6 photoresist layer 2 0 first trench Opening 2 2 Second trench opening 2 4, 3 8 Double engraved opening 32 Second dielectric layer 34 Third dielectric layer 3 5 Dielectric layer block ί > 4 0 Inclined bottom surface 4 1 Inclined sidewall 4 2 Relay ditch
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