KR100268515B1 - A manufacturing method of contact holes - Google Patents
A manufacturing method of contact holes Download PDFInfo
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- KR100268515B1 KR100268515B1 KR1019980003088A KR19980003088A KR100268515B1 KR 100268515 B1 KR100268515 B1 KR 100268515B1 KR 1019980003088 A KR1019980003088 A KR 1019980003088A KR 19980003088 A KR19980003088 A KR 19980003088A KR 100268515 B1 KR100268515 B1 KR 100268515B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
Description
본 발명은 반도체 소자의 접촉구 형성 방법에 관한 것으로서, 특히 실리콘 기판과 금속 사이의 연결을 위한 접촉구 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly to a method for forming a contact hole for a connection between a silicon substrate and a metal.
최근, 반도체 집적회로가 고집적화됨에 따라 제한된 면적 내에서 배선과 배선을 효과적으로 연결하는 방법들이 제시되고 있다. 그 중, 집적 회로에서의 배선을 다층화하는 다층 배선 방법이 주로 사용되고 있는데, 반도체 소자간에 배선이 통과되는 공간을 고려할 필요가 없기 때문에 반도체 칩의 크기를 작게 가져갈 수 있다. 그러나, 배선간의 교차부인 접촉구에서의 단차에 의해 생기는 스텝 커버리지 불량이나 접촉 불량 등이 문제가 되고 있다.Recently, as semiconductor integrated circuits are highly integrated, methods for effectively connecting wirings and wirings within a limited area have been proposed. Among them, a multilayer wiring method for multilayering wiring in an integrated circuit is mainly used. Since it is not necessary to consider a space through which wiring passes between semiconductor elements, the size of a semiconductor chip can be reduced. However, there is a problem of poor step coverage, poor contact, and the like caused by a step in a contact hole that is an intersection between the wirings.
그러면, 도 1을 참고로 하여 종래의 기술에 따른 접촉구 형성 방법에 대하여 설명한다.Next, a method of forming a contact hole according to the related art will be described with reference to FIG. 1.
도 1에 도시한 바와 같이, 규소 기판(1) 위에 규소 티타늄(TiSi) 등의 실리사이드(silicide)막(2)을 형성하고, 그 위에 TEOS(thetraethyle orthosilicate)막(3) 및 BPSG막(4) 등으로 이루어진 절연막을 형성한 다음, TEOS막(3)과 BPSG막(4)을 동시에 식각하여 접촉구를 형성한다. 그 위에 스퍼터링으로 티타늄(Ti) 및 질화 티타늄(TiN)을 증착하고 어닐링(annealing)을 실시하여 전기적 접촉 특성을 향상시키기 위한 오믹 접촉 금속층(5)을 형성하고, 화학 기상 증착(chemical vapor deposition:CVD) 방식으로 플러그 형성을 위한 텅스텐(W)막(6)을 증착한다.As shown in FIG. 1, a silicide film 2 such as silicon titanium (TiSi) is formed on the silicon substrate 1, and thereon, a TEOS (thetraethyle orthosilicate) film 3 and a BPSG film 4 are formed thereon. After forming an insulating film made of, or the like, the TEOS film 3 and the BPSG film 4 are simultaneously etched to form contact holes. On top of that, by sputtering, titanium (Ti) and titanium nitride (TiN) are deposited and annealed to form an ohmic contact metal layer 5 for improving electrical contact characteristics, and chemical vapor deposition (CVD) The tungsten (W) film 6 for the plug formation is deposited in the following manner.
종래의 방법에서, 접촉구의 폭이 좁기 때문에 임의의 방향으로 스퍼터(sputter)된 티타늄 및 질화 티타늄 입자는 접촉구의 안쪽보다 위쪽 모서리 부분에서 상대적으로 두껍게 증착된다. 따라서, 접촉구의 입구가 아래쪽보다 좁아지거나 접촉구의 바닥 측면을 티타늄 및 질화 티타늄이 완전히 산화막을 덮지 못한다. 그러면, 텅스텐막을 증착하는 과정에서 접촉구 내부에 텅스텐(W)이 완전히 채워지지 않고 금속막(3)에 구멍이 생기거나, 텅스텐막 증착에 사용되는 기체인 WF6의 F가 규소 티타늄과 반응한다. 이는 접촉 저항을 증가시키고, 이에 따른 전류의 누설을 가져온다.In the conventional method, the titanium and titanium nitride particles sputtered in any direction because of the narrow width of the contact hole are deposited relatively thick at the upper edge portion of the contact hole. Therefore, the inlet of the contact becomes narrower than the lower side, or titanium and titanium nitride do not completely cover the oxide film on the bottom side of the contact. Then, in the process of depositing the tungsten film, a hole is formed in the metal film 3 without completely filling tungsten (W) inside the contact hole, or F of WF 6 , a gas used for tungsten film deposition, reacts with the titanium titanium. . This increases the contact resistance, resulting in leakage of current.
본 발명은 이러한 문제점을 해결하기 위한 것으로서, 규소 기판과 상부 배선이 접촉하는 접촉구에서의 접촉 저항이나 전류 누설을 감소시키는 것이 과제이다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and it is a problem to reduce contact resistance or current leakage at the contact hole where the silicon substrate and the upper wiring contact.
도 1은 종래의 접촉구에서의 플러그(plug) 구조를 도시한 단면도이고,1 is a cross-sectional view showing a plug structure in a conventional contact hole,
도 2a 내지 도 2h는 본 발명에 따른 접촉구 형성 방법을 공정 순서에 따라 도시한 단면도이다.2A to 2H are cross-sectional views illustrating a method for forming a contact hole according to the present invention in a process sequence.
이러한 과제를 해결하기 위한 본 발명에 따른 접촉구 형성 방법에서는 접촉구가 형성되어 있는 절연막 위에 산화막을 증착하고, 에치백 방식으로 식각하여 접촉구 바깥쪽 및 위쪽 모서리 부분 및 바닥 부분의 산화막이 제거되도록 한다.In the contact hole forming method according to the present invention for solving this problem, the oxide film is deposited on the insulating film on which the contact hole is formed, and etched by etching to remove the oxide film on the outer and upper corner portions and the bottom portion of the contact hole. do.
이때, 산화막은 반응성 이온 식각 방식으로 식각할 수 있으며, 반응성 이온 식각의 반응성 기체로는 SF6, CF4또는 CHF3기체를 사용할 수 있다.In this case, the oxide layer may be etched by a reactive ion etching method, and as a reactive gas of reactive ion etching, SF 6 , CF 4, or CHF 3 gas may be used.
또한, 층간 절연막 상부 및 접촉구 내에 티타늄/질화 티타늄을 차례로 증착하여 오믹 접촉층을 형성하고, 오믹 접촉층 상부에 화학 기상 증착 방식으로 배선용 금속을 증착하는 것이 바람직하다.In addition, it is preferable to deposit an ohmic contact layer by sequentially depositing titanium / titanium nitride in the interlayer insulating film and the contact hole, and depositing a wiring metal on the ohmic contact layer by chemical vapor deposition.
산화막에는 플라스마 방식으로 증착한 TEOS막 또는 열산화 방식으로 형성한 산화규소막 등이 쓰일 수 있다.As the oxide film, a TEOS film deposited by a plasma method or a silicon oxide film formed by a thermal oxidation method may be used.
또한, 층간 절연막은 하부층인 TEOS층과 상부층인 BPSG층을 차례로 증착하여 이중층으로 형성할 수 있으며, BPSG층을 증착한 후에는 물리·화학적 연마를 실시하여 그 일부를 제거하는 것이 바람직하다.In addition, the interlayer insulating film may be formed as a double layer by sequentially depositing the TEOS layer, which is the lower layer, and the BPSG layer, which is the upper layer. After depositing the BPSG layer, it is preferable to remove part of the interlayer insulating film by performing physical and chemical polishing.
이처럼, 본 발명에 따른 반도체 소자의 제조 방법에서는 반응성 이온 식각으로 접촉구의 위쪽 모서리를 둥글게 처리하여 접촉구의 입구를 넓힘으로써, 배리어(barrier) 금속을 증착하는 다음 단계에서 배리어 금속이 접촉구 내부에 충분히 채워지도록 한다.As described above, in the method of manufacturing a semiconductor device according to the present invention, the upper edge of the contact hole is rounded by reactive ion etching to widen the contact hole, so that the barrier metal is sufficiently inside the contact hole in the next step of depositing the barrier metal. To be filled.
그러면, 첨부한 도면을 참고로 하여 본 발명의 실시예에 따른 접촉구 형성방법을 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세하게 설명한다.Then, the contact hole forming method according to an embodiment of the present invention with reference to the accompanying drawings will be described in detail to be easily carried out by those of ordinary skill in the art.
도 2a 내지 도 2h는 본 발명에 따른 접촉구 형성 방법을 공정 순서에 따라 도시한 단면도로서, 접촉구의 위쪽 모서리를 둥글게 형성하는 방법에 관한 것이다.2A to 2H are cross-sectional views illustrating a method of forming a contact hole according to the present invention in a process sequence, and a method of rounding an upper edge of the contact hole.
규소 기판(1) 위에 빠른 열 공정(rapid thermal process:RTP)을 통해 규소티타늄(TiSi)의 실리사이드막(2)을 600Å 정도의 두께로 형성한다. 그 위에 플라스마 방식으로 TEOS막(3) 및 BPSG막(4)을 각각 1,500Å, 14,000Å 정도의 두께로 적층하여 절연막을 형성한 다음, 물리· 화학적 연마를 실시하여 BPSG막(4)을 5,500Å 정도 제거한다(도 2a 참조).A silicide film 2 of titanium (TiSi) is formed on the silicon substrate 1 by a rapid thermal process (RTP) to a thickness of about 600 kPa. On top of that, the TEOS film 3 and the BPSG film 4 were laminated to a thickness of about 1,500 kPa and 14,000 kPa, respectively, to form an insulating film. Then, the physical and chemical polishing was performed to make the BPSG film 4 5,500 kPa. Remove to a degree (see FIG. 2A).
그 위에 접촉구 형성을 위한 포토레지스트 패턴(PR)을 형성하고(도 2b 참조), 포토레지스트 패턴(PR)을 마스크로 하여 TEOS막(3)과 BPSG막(4)을 동시에 식각하여 접촉구(C)를 형성한다. 이때, 접촉구(C)의 측벽은 수직으로 형성된다. 그후, 애싱(ashing)을 실시하여 포토레지스트 패턴을 제거한 후, 세정을 실시한다( 도 2c 참조).A photoresist pattern PR for forming a contact hole is formed thereon (see FIG. 2B), and the TEOS film 3 and the BPSG film 4 are simultaneously etched using the photoresist pattern PR as a mask. Form C). At this time, the side wall of the contact hole (C) is formed vertically. Thereafter, ashing is performed to remove the photoresist pattern, followed by cleaning (see FIG. 2C).
다음, 플라즈마 방식으로 TEOS를 500~2,000Å의 두께로 증착하여 산화막(10)을 형성한다. 이때, 열산화 방식을 이용하여 산화 규소(SiO2)막(10)을 형성할 수도 있다. 이때, 접촉구(C)의 바닥에 쌓이는 두께와 측벽에 쌓이는 두께는 일정하게 유지한다(도 2d 참조).Next, the oxide film 10 is formed by depositing TEOS to a thickness of 500 to 2,000 mW using a plasma method. In this case, the silicon oxide (SiO 2 ) film 10 may be formed using a thermal oxidation method. At this time, the thickness stacked on the bottom of the contact hole (C) and the thickness stacked on the side wall is kept constant (see Fig. 2d).
다음, 에치백(etchback) 방식의 식각, 특히 SF6, CF4및 CHF3기체를 이용하여 반응성 이온 식각(recative ion etching:RIE)을 실시한다. 반응성 이온 식각을 실시하는 경우, 이방성 식각 즉, 좌·우로는 식각이 거의 이루어지지 않고 상·하(10) 방향으로만 식각이 이루어지므로, 접촉구(C)의 측벽에만 산화막(11)이 남고 접촉구(C) 바깥쪽에 위치한 평탄한 부분, 접촉구(C) 위쪽의 모서리 부분 및 바닥의 산화막(10)이 제거되어, 접촉구(C) 위쪽 모서리가 둥근 형태를 가지게 된다. 다음, 세정을 실시한다(도 2e 참조).Next, reactive ion etching (RIE) is performed using etchback etching, particularly SF 6 , CF 4 and CHF 3 gas. When reactive ion etching is performed, the anisotropic etching, that is, the etching is performed only in the up and down directions in the left and right directions, and thus the oxide film 11 remains only on the sidewall of the contact hole C. The flat portion located outside the contact hole C, the corner portion above the contact hole C, and the oxide layer 10 at the bottom are removed, so that the upper edge of the contact hole C is rounded. Next, washing is performed (see FIG. 2E).
그 위에 티타늄 및 질화 티타늄을 스퍼터링 방식으로 각각 350Å, 1,200Å 정도의 두께로 증착하여 오믹 접촉 금속층을 형성한 다음, 700℃에서 어닐링 처리하여 접촉막 특성을 안정시킨다(도 2f 참조).Titanium and titanium nitride are deposited to a thickness of about 350 kPa and 1,200 kPa, respectively, by sputtering to form an ohmic contact metal layer, and then annealing at 700 ° C. to stabilize the contact film properties (see FIG. 2F).
다음, 텅스텐(W)을 화학 기상 증착 방식으로 4,500Å 정도로 플러그 형성을 위한 금속막(6)을 증착하고(도 2g 참조), 에치백 방식으로 접촉구(C) 바깥 평면에 위치한 금속막(6)을 제거하여 플러그(6')를 형성한다(도 2h 참조). 플러그(6')는 다음 단계에서 형성되는 알루미늄(Al) 배선 등과 연결된다.Next, tungsten (W) is deposited using a chemical vapor deposition method to deposit a metal film 6 for plug formation at about 4,500Å (see FIG. 2G), and the metal film 6 located on the outer surface of the contact hole C by an etch back method. ) Is removed to form plug 6 '(see Figure 2H). The plug 6 'is connected to an aluminum (Al) wire formed in the next step.
이상에서와 같이, 반응성 이온 식각으로 접촉구의 위쪽 모서리를 둥글게 처리하여 접촉구의 입구를 넓힘으로써, 플러그 형성용 금속을 증착하는 다음 단계에서 금속이 접촉구 내부에 충분히 채워지도록 한다. 이에 따라, 접촉구 부근에서 금속막 내에 구멍이 생기는 것을 막으며, WF6의 F가 TiSi와 반응하지 못하기 때문에, 접촉 저항 및 누설 전류를 감소시킨다.As described above, the upper edge of the contact is rounded by reactive ion etching to widen the entrance of the contact, so that the metal is sufficiently filled in the contact in the next step of depositing the metal for plug formation. This prevents the formation of holes in the metal film in the vicinity of the contact hole and reduces the contact resistance and leakage current because F of WF 6 does not react with TiSi.
Claims (10)
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| KR1019980003088A KR100268515B1 (en) | 1998-02-04 | 1998-02-04 | A manufacturing method of contact holes |
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| KR1019980003088A KR100268515B1 (en) | 1998-02-04 | 1998-02-04 | A manufacturing method of contact holes |
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| KR100604803B1 (en) * | 2000-03-16 | 2006-07-26 | 삼성전자주식회사 | Method for forming contact plug for semiconductor device |
| KR100558008B1 (en) | 2003-12-29 | 2006-03-06 | 삼성전자주식회사 | method of forming interconnection lines in a semiconductor device |
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