DE10339990B8 - Verfahren zur Herstellung einer Metallleitung mit einer erhöhten Widerstandsfähigkeit gegen Elektromigration entlang einer Grenzfläche einer dielektrischen Barrierenschicht mittels Implantieren von Material in die Metalleitung - Google Patents

Verfahren zur Herstellung einer Metallleitung mit einer erhöhten Widerstandsfähigkeit gegen Elektromigration entlang einer Grenzfläche einer dielektrischen Barrierenschicht mittels Implantieren von Material in die Metalleitung Download PDF

Info

Publication number
DE10339990B8
DE10339990B8 DE10339990A DE10339990A DE10339990B8 DE 10339990 B8 DE10339990 B8 DE 10339990B8 DE 10339990 A DE10339990 A DE 10339990A DE 10339990 A DE10339990 A DE 10339990A DE 10339990 B8 DE10339990 B8 DE 10339990B8
Authority
DE
Germany
Prior art keywords
metal line
fabricating
interface
barrier layer
increased resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE10339990A
Other languages
English (en)
Other versions
DE10339990B4 (de
DE10339990A1 (de
Inventor
Hans-Jürgen Engelmann
Ehrenfried Zschech
Peter Hübler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to DE10339990A priority Critical patent/DE10339990B8/de
Priority to US10/813,223 priority patent/US7183629B2/en
Publication of DE10339990A1 publication Critical patent/DE10339990A1/de
Publication of DE10339990B4 publication Critical patent/DE10339990B4/de
Application granted granted Critical
Publication of DE10339990B8 publication Critical patent/DE10339990B8/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE10339990A 2003-08-29 2003-08-29 Verfahren zur Herstellung einer Metallleitung mit einer erhöhten Widerstandsfähigkeit gegen Elektromigration entlang einer Grenzfläche einer dielektrischen Barrierenschicht mittels Implantieren von Material in die Metalleitung Expired - Lifetime DE10339990B8 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE10339990A DE10339990B8 (de) 2003-08-29 2003-08-29 Verfahren zur Herstellung einer Metallleitung mit einer erhöhten Widerstandsfähigkeit gegen Elektromigration entlang einer Grenzfläche einer dielektrischen Barrierenschicht mittels Implantieren von Material in die Metalleitung
US10/813,223 US7183629B2 (en) 2003-08-29 2004-03-30 Metal line having an increased resistance to electromigration along an interface of a dielectric barrier layer by implanting material into the metal line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10339990A DE10339990B8 (de) 2003-08-29 2003-08-29 Verfahren zur Herstellung einer Metallleitung mit einer erhöhten Widerstandsfähigkeit gegen Elektromigration entlang einer Grenzfläche einer dielektrischen Barrierenschicht mittels Implantieren von Material in die Metalleitung

Publications (3)

Publication Number Publication Date
DE10339990A1 DE10339990A1 (de) 2005-03-31
DE10339990B4 DE10339990B4 (de) 2012-11-22
DE10339990B8 true DE10339990B8 (de) 2013-01-31

Family

ID=34202239

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10339990A Expired - Lifetime DE10339990B8 (de) 2003-08-29 2003-08-29 Verfahren zur Herstellung einer Metallleitung mit einer erhöhten Widerstandsfähigkeit gegen Elektromigration entlang einer Grenzfläche einer dielektrischen Barrierenschicht mittels Implantieren von Material in die Metalleitung

Country Status (2)

Country Link
US (1) US7183629B2 (de)
DE (1) DE10339990B8 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004021239B4 (de) * 2004-04-30 2017-04-06 Infineon Technologies Ag Lange getemperte integrierte Schaltungsanordnungen und deren Herstellungsverfahren
US7989338B2 (en) * 2005-06-15 2011-08-02 Globalfoundries Singapore Pte. Ltd. Grain boundary blocking for stress migration and electromigration improvement in CU interconnects
DK2024372T3 (da) * 2006-04-26 2010-09-20 Hoffmann La Roche Thieno[3,2-d]pyrimidin-derivat, der er egnet som P13K inhibitor
US7531384B2 (en) * 2006-10-11 2009-05-12 International Business Machines Corporation Enhanced interconnect structure
US20080258303A1 (en) * 2007-04-23 2008-10-23 Ming-Shih Yeh Novel structure for reducing low-k dielectric damage and improving copper EM performance
DE102007052048A1 (de) * 2007-10-31 2009-05-14 Advanced Micro Devices, Inc., Sunnyvale Doppelintegrationsschema für Metallschicht mit geringem Widerstand
US7737013B2 (en) * 2007-11-06 2010-06-15 Varian Semiconductor Equipment Associates, Inc. Implantation of multiple species to address copper reliability
DE102012109272B4 (de) * 2012-09-28 2022-07-28 PV TECH Plasma und Vakuum Technologie GmbH Nanostrukturierte offenporige Diffusionsschicht für die kontrollierte Abgabe von Kupferionen zum gezielten Abtöten von MRE-Keimen
US11791204B2 (en) * 2020-04-21 2023-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with connecting structure having a doped layer and method for forming the same
TWI784450B (zh) 2020-04-28 2022-11-21 台灣積體電路製造股份有限公司 半導體裝置及其形成方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5960275A (en) * 1996-10-28 1999-09-28 Magemos Corporation Power MOSFET fabrication process to achieve enhanced ruggedness, cost savings, and product reliability
US6023100A (en) * 1997-07-23 2000-02-08 Advanced Micro Devices, Inc. Metallization stack structure to improve electromigration resistance and keep low resistivity of ULSI interconnects
WO2001008213A1 (en) * 1999-07-27 2001-02-01 International Business Machines Corporation REDUCED ELECTROMIGRATION AND STRESS INDUCED MIGRATION OF Cu WIRES BY SURFACE COATING
US6232244B1 (en) * 1997-12-18 2001-05-15 Advanced Micro Devices, Inc. Methodology for achieving dual gate oxide thicknesses
US6268291B1 (en) * 1995-12-29 2001-07-31 International Business Machines Corporation Method for forming electromigration-resistant structures by doping
WO2001097283A1 (en) * 2000-06-14 2001-12-20 Advanced Micro Devices, Inc. Copper interconnects with improved electromigration resistance and low resistivity
US20020076925A1 (en) * 2000-12-18 2002-06-20 Marieb Thomas N. Copper alloys for interconnections having improved electromigration characteristics and methods of making same
US6518184B1 (en) * 2002-01-18 2003-02-11 Intel Corporation Enhancement of an interconnect
US20030118798A1 (en) * 2001-12-25 2003-06-26 Nec Electronics Corporation Copper interconnection and the method for fabricating the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU6831801A (en) * 2000-06-12 2001-12-24 Previsor Inc Computer-implemented system for human resources management

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6268291B1 (en) * 1995-12-29 2001-07-31 International Business Machines Corporation Method for forming electromigration-resistant structures by doping
US5960275A (en) * 1996-10-28 1999-09-28 Magemos Corporation Power MOSFET fabrication process to achieve enhanced ruggedness, cost savings, and product reliability
US6023100A (en) * 1997-07-23 2000-02-08 Advanced Micro Devices, Inc. Metallization stack structure to improve electromigration resistance and keep low resistivity of ULSI interconnects
US6232244B1 (en) * 1997-12-18 2001-05-15 Advanced Micro Devices, Inc. Methodology for achieving dual gate oxide thicknesses
WO2001008213A1 (en) * 1999-07-27 2001-02-01 International Business Machines Corporation REDUCED ELECTROMIGRATION AND STRESS INDUCED MIGRATION OF Cu WIRES BY SURFACE COATING
WO2001097283A1 (en) * 2000-06-14 2001-12-20 Advanced Micro Devices, Inc. Copper interconnects with improved electromigration resistance and low resistivity
US20020076925A1 (en) * 2000-12-18 2002-06-20 Marieb Thomas N. Copper alloys for interconnections having improved electromigration characteristics and methods of making same
US20030118798A1 (en) * 2001-12-25 2003-06-26 Nec Electronics Corporation Copper interconnection and the method for fabricating the same
US6518184B1 (en) * 2002-01-18 2003-02-11 Intel Corporation Enhancement of an interconnect

Also Published As

Publication number Publication date
DE10339990B4 (de) 2012-11-22
US20050046031A1 (en) 2005-03-03
US7183629B2 (en) 2007-02-27
DE10339990A1 (de) 2005-03-31

Similar Documents

Publication Publication Date Title
ATE447942T1 (de) Verfahren zur herstellung einer gegen missbrauch gesicherten darreichungsform
DE602005002661D1 (de) Verfahren zur Herstellung einer leitfähigen Diamantelektrode
DE602005015548D1 (de) Verfahren zur herstellung einer elektrisch leitfähigen verbindung vom mayenit-typ
DE60325603D1 (de) Gewinnungsverfahren einer unverseifbaren avocadofraktion mit einem höheren furanlipidengehalt
DE602004018079D1 (de) Verfahren zur Herstellung eines elektrischen Widerstandsheizelements
DE10339990B8 (de) Verfahren zur Herstellung einer Metallleitung mit einer erhöhten Widerstandsfähigkeit gegen Elektromigration entlang einer Grenzfläche einer dielektrischen Barrierenschicht mittels Implantieren von Material in die Metalleitung
DE60209148D1 (de) Beschichteter gegenstand mit verbesserter barriereschichtstruktur und verfahren zu dessen herstellung
DE60218109D1 (de) Verfahren zur Herstellung einer transparenten leitfähigen Schicht, eine durch dieses Verfahren hergestellte transparente und leitfähige Schicht und Material, das diese Schicht enthält
DE60318537D1 (de) Verfahren zur Herstellung eines berührungsempfindlichen Widerstandsbildschirms
DE502004008037D1 (de) Verbindung zur bildung einer selbstorganisierenden monolage, schichtstruktur, halbleiterbauelement mit einer schichtstruktur und verfahren zur herstellung einer schichtstruktur
DE60234088D1 (de) Verfahren zur recherche in einer elektronischer programmführung
EP1621696A3 (de) Platte aus Schaumstoff mit verschmolzener Oberfläche
ATE501150T1 (de) Verfahren zur herstellung von oxycodonhydrochlorid mit weniger als 25 ppm 14- hydroxycodeinon
DE60039257D1 (de) Verfahren zur herstellung einer kupferfolie mit au
PL1658324T3 (pl) Termochromowa folia polimerowa i sposób jej wytwarzania
DE602004021601D1 (de) Positivphotoresistzusammensetzung und verfahren zur ausbildung einer resiststruktur
DE60228711D1 (de) Verfahren zur herstellung einer sinterlegierung
DE10295883T1 (de) Mit einem isolierenden Bauteil ausgestatteter Kern und Verfahren zur Herstellung desselben
DE50313093D1 (de) Verfahren zur herstellung dünner metallhaltiger schichten mit geringem elektrischen widerstand
DE60216825D1 (de) Verfahren zum herstellen einer im wesentlichen transparenten elektrisch leitenden schichtanordnung
DE502004009020D1 (de) Integrierte schaltung mit einem organischen halbleiter und verfahren zur herstellung einer integrierten schaltung
DE60317152D1 (de) Verfahren zur Bestimmung der Penetration von Hydrogenperoxiddampf in einem Lumen
DE60330600D1 (de) Elektrisch leitendes zinkoxydpulver und dessen herstellungsverfahren und elektrisch leitende zusammensetzung
DE502004012455D1 (de) Verfahren zur Herstellung einer Lötstoppbarriere
DE502005004753D1 (de) Verfahren zur bestimmung eines leitenden teilnehmers in einem netzwerk

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
R079 Amendment of ipc main class

Free format text: PREVIOUS MAIN CLASS: H01L0023532000

Ipc: H01L0021768000

R016 Response to examination communication
R018 Grant decision by examination section/examining division
R079 Amendment of ipc main class

Free format text: PREVIOUS MAIN CLASS: H01L0023532000

Ipc: H01L0021768000

Effective date: 20120627

R020 Patent grant now final

Effective date: 20130223

R071 Expiry of right