JP2007027303A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- JP2007027303A JP2007027303A JP2005205303A JP2005205303A JP2007027303A JP 2007027303 A JP2007027303 A JP 2007027303A JP 2005205303 A JP2005205303 A JP 2005205303A JP 2005205303 A JP2005205303 A JP 2005205303A JP 2007027303 A JP2007027303 A JP 2007027303A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- conductive film
- semiconductor device
- film
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/924—Active solid-state devices, e.g. transistors, solid-state diodes with passive device, e.g. capacitor, or battery, as integral part of housing or housing element, e.g. cap
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/957—Making metal-insulator-metal device
Abstract
【解決手段】 半導体装置1は、配線12、導電膜14(第1の導電膜)、絶縁膜20(第1の絶縁膜)、導電膜30(第2の導電膜)、絶縁膜40(第2の絶縁膜)、ビアプラグ52(第1のビアプラグ)、およびビアプラグ54(第2のビアプラグ)を備えている。半導体装置1において、導電膜14、絶縁膜20および導電膜30は、MIMキャパシタ(容量素子)を構成している。具体的には、導電膜14、絶縁膜20および導電膜30がそれぞれ下部電極、容量絶縁膜および上部電極として機能する。絶縁膜40は、導電膜30および配線12の双方を覆っている。この絶縁膜40は、ビアプラグ52,54に対するエッチングストッパとして機能する。
【選択図】 図1
Description
(第1実施形態)
(第2実施形態)
(第3実施形態)
(第4実施形態)
2 半導体装置
3 半導体装置
4 半導体装置
10 層間絶縁膜
12 配線
14 導電膜
15 導電膜
16 絶縁膜
18 絶縁膜
20 絶縁膜
20a 絶縁膜
30 導電膜
40 絶縁膜
50 層間絶縁膜
52 ビアプラグ
54 ビアプラグ
56 ビアプラグ
60 絶縁膜
70 層間絶縁膜
72,74,76 配線
Claims (11)
- 第1の層間絶縁膜中に設けられた配線と、
前記配線と離間して設けられた第1の導電膜と、
前記第1の導電膜上に設けられた第1の絶縁膜と、
前記第1の絶縁膜を挟んで前記第1の導電膜に対向する位置に設けられ、前記第1の導電膜および前記第1の絶縁膜と共に容量素子を構成する第2の導電膜と、
前記第2の導電膜および前記配線の双方を覆う第2の絶縁膜と、
第2の層間絶縁膜中に設けられ、前記第2の絶縁膜を貫通して前記配線に接続された第1のビアプラグと、
前記第2の層間絶縁膜中に設けられ、前記第2の絶縁膜を貫通して前記第2の導電膜に接続された第2のビアプラグと、
を備えることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1の導電膜は、前記第1の層間絶縁膜中に設けられており、前記容量素子を構成するとともに配線として機能する半導体装置。 - 請求項1に記載の半導体装置において、
前記第2の絶縁膜を貫通して前記第1の導電膜に接続された第3のビアプラグを更に備え、
前記第1の導電膜は、前記第1の層間絶縁膜上に設けられている半導体装置。 - 請求項1乃至3いずれかに記載の半導体装置において、
前記第2の導電膜は、平面視で、前記第1の導電膜よりも面積が小さく且つ前記第1の導電膜に内包される半導体装置。 - 請求項1乃至3いずれかに記載の半導体装置において、
前記第2の導電膜は、平面視で、前記第1の導電膜よりも面積が大きく且つ前記第1の導電膜を内包する半導体装置。 - 請求項1乃至5いずれかに記載の半導体装置において、
前記第1の絶縁膜は、前記第1の導電膜および前記配線のうち前記第1の導電膜上にのみ設けられている半導体装置。 - 請求項1乃至6いずれかに記載の半導体装置において、
前記配線は、銅配線である半導体装置。 - 配線を形成する工程と、
前記配線と離間させて第1の導電膜を形成する工程と、
前記配線を形成する工程よりも後に、前記第1の導電膜上に第1の絶縁膜を形成する工程と、
前記第1の絶縁膜上に、当該第1の絶縁膜を挟んで前記第1の導電膜に対向するように、前記第1の導電膜および前記第1の絶縁膜と共に容量素子を構成する第2の導電膜を形成する工程と、
前記第2の導電膜および前記配線の双方を覆うように、第2の絶縁膜を形成する工程と、
前記第2の絶縁膜をエッチングストッパとして、前記配線に接続されるように第1のビアプラグを形成する工程と、
前記第2の絶縁膜をエッチングストッパとして、前記第2の導電膜に接続されるように第2のビアプラグを形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 請求項8に記載の半導体装置の製造方法において、
前記第1の導電膜を形成する工程においては、前記配線と同一の層間絶縁膜中に当該第1の導電膜を形成し、
前記配線を形成する工程と前記第1の導電膜を形成する工程とは、同時に実行される半導体装置の製造方法。 - 請求項8に記載の半導体装置の製造方法において、
前記第2の絶縁膜をエッチングストッパとして、前記第1の導電膜に接続されるように第3のビアプラグを形成する工程を更に含み、
前記第1の導電膜を形成する工程においては、前記配線が形成された層間絶縁膜上に当該第1の導電膜を形成する半導体装置の製造方法。 - 請求項8乃至10いずれかに記載の半導体装置の製造方法において、
前記配線を形成する工程においては、前記配線として銅配線をダマシン法によって形成する半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005205303A JP5154744B2 (ja) | 2005-07-14 | 2005-07-14 | 半導体装置およびその製造方法 |
US11/483,533 US7719085B2 (en) | 2005-07-14 | 2006-07-11 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005205303A JP5154744B2 (ja) | 2005-07-14 | 2005-07-14 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007027303A true JP2007027303A (ja) | 2007-02-01 |
JP5154744B2 JP5154744B2 (ja) | 2013-02-27 |
Family
ID=37660924
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005205303A Expired - Fee Related JP5154744B2 (ja) | 2005-07-14 | 2005-07-14 | 半導体装置およびその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7719085B2 (ja) |
JP (1) | JP5154744B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015191948A (ja) * | 2014-03-27 | 2015-11-02 | 旭化成エレクトロニクス株式会社 | キャパシタの製造方法及び半導体装置の製造方法、並びにキャパシタ及び半導体装置 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7494939B2 (en) | 2004-08-31 | 2009-02-24 | Micron Technology, Inc. | Methods for forming a lanthanum-metal oxide dielectric layer |
CN102299106B (zh) * | 2010-06-25 | 2013-09-18 | 中芯国际集成电路制造(上海)有限公司 | 相变存储器存储单元的制作方法 |
CN102487120B (zh) * | 2010-12-03 | 2014-03-12 | 中芯国际集成电路制造(北京)有限公司 | 相变存储器的形成方法 |
US10306433B1 (en) * | 2017-05-01 | 2019-05-28 | Sprint Communications Company L.P. | Mobile phone differentiated user set-up |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01225147A (ja) * | 1988-03-04 | 1989-09-08 | Toshiba Corp | 半導体装置とその製造方法 |
JPH03218063A (ja) * | 1990-01-23 | 1991-09-25 | Matsushita Electron Corp | 半導体集積回路装置 |
JPH03231453A (ja) * | 1990-02-07 | 1991-10-15 | Toshiba Corp | キャパシターを備えた半導体装置 |
JPH10144865A (ja) * | 1996-11-06 | 1998-05-29 | Samsung Electron Co Ltd | 薄膜キャパシタ及びその製造方法 |
JP2002009248A (ja) * | 2000-06-26 | 2002-01-11 | Oki Electric Ind Co Ltd | キャパシタおよびその製造方法 |
US20030211731A1 (en) * | 2002-05-07 | 2003-11-13 | Chartered Semiconductor Manufacturing Ltd. | Metal sandwich structure for MIM capacitor onto dual damascene |
JP2003324153A (ja) * | 2002-04-26 | 2003-11-14 | Nec Electronics Corp | 半導体容量素子及びその製造方法 |
JP2005340818A (ja) * | 2004-05-28 | 2005-12-08 | Samsung Electronics Co Ltd | 大容量mimキャパシタ及びその製造方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100324591B1 (ko) * | 1998-12-24 | 2002-04-17 | 박종섭 | 티타늄 알루미늄 질소 합금막을 상부전극의 확산방지막으로서 이용하는 캐패시터 제조 방법 |
US6958572B2 (en) * | 2002-02-06 | 2005-10-25 | Ut-Battelle Llc | Controlled non-normal alignment of catalytically grown nanostructures in a large-scale synthesis process |
KR100505658B1 (ko) * | 2002-12-11 | 2005-08-03 | 삼성전자주식회사 | MIM(Metal-Insulator-Metal)커패시터를 갖는 반도체 소자 |
KR100505682B1 (ko) * | 2003-04-03 | 2005-08-03 | 삼성전자주식회사 | 금속-절연체-금속 커패시터를 포함하는 이중 다마신 배선구조 및 그 제조방법 |
DE10344389A1 (de) * | 2003-09-25 | 2005-05-19 | Infineon Technologies Ag | Verfahren zur Herstellung einer multifunktionellen Dielektrikumschicht auf einem Substrat |
US6876028B1 (en) * | 2003-09-30 | 2005-04-05 | International Business Machines Corporation | Metal-insulator-metal capacitor and method of fabrication |
US7169665B2 (en) * | 2004-05-04 | 2007-01-30 | Tawian Semiconductor Manufacturing Company, Ltd. | Capacitance process by using passivation film scheme |
KR100755365B1 (ko) * | 2005-02-15 | 2007-09-04 | 삼성전자주식회사 | 엠. 아이. 엠 커패시터들 및 그 형성방법들 |
US20070080426A1 (en) * | 2005-10-11 | 2007-04-12 | Texas Instruments Incorporated | Single lithography-step planar metal-insulator-metal capacitor and resistor |
US7585722B2 (en) * | 2006-01-10 | 2009-09-08 | International Business Machines Corporation | Integrated circuit comb capacitor |
JP2007207878A (ja) * | 2006-01-31 | 2007-08-16 | Nec Electronics Corp | 半導体装置 |
-
2005
- 2005-07-14 JP JP2005205303A patent/JP5154744B2/ja not_active Expired - Fee Related
-
2006
- 2006-07-11 US US11/483,533 patent/US7719085B2/en not_active Expired - Fee Related
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01225147A (ja) * | 1988-03-04 | 1989-09-08 | Toshiba Corp | 半導体装置とその製造方法 |
JPH03218063A (ja) * | 1990-01-23 | 1991-09-25 | Matsushita Electron Corp | 半導体集積回路装置 |
JPH03231453A (ja) * | 1990-02-07 | 1991-10-15 | Toshiba Corp | キャパシターを備えた半導体装置 |
JPH10144865A (ja) * | 1996-11-06 | 1998-05-29 | Samsung Electron Co Ltd | 薄膜キャパシタ及びその製造方法 |
JP2002009248A (ja) * | 2000-06-26 | 2002-01-11 | Oki Electric Ind Co Ltd | キャパシタおよびその製造方法 |
JP2003324153A (ja) * | 2002-04-26 | 2003-11-14 | Nec Electronics Corp | 半導体容量素子及びその製造方法 |
US20030211731A1 (en) * | 2002-05-07 | 2003-11-13 | Chartered Semiconductor Manufacturing Ltd. | Metal sandwich structure for MIM capacitor onto dual damascene |
JP2005340818A (ja) * | 2004-05-28 | 2005-12-08 | Samsung Electronics Co Ltd | 大容量mimキャパシタ及びその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015191948A (ja) * | 2014-03-27 | 2015-11-02 | 旭化成エレクトロニクス株式会社 | キャパシタの製造方法及び半導体装置の製造方法、並びにキャパシタ及び半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US7719085B2 (en) | 2010-05-18 |
JP5154744B2 (ja) | 2013-02-27 |
US20070013028A1 (en) | 2007-01-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7301218B2 (en) | Parallel capacitor of semiconductor device | |
US7749852B2 (en) | Methods of forming metal-insulator-metal (MIM) capacitors with passivation layers on dielectric layers | |
JP2004063667A (ja) | 多層配線層内に形成されたキャパシタを有する半導体装置 | |
JP2009277719A (ja) | 半導体装置及びその製造方法 | |
KR20010019262A (ko) | 반도체 집적회로의 커패시터 제조방법 | |
JP2007049089A (ja) | 半導体装置およびその製造方法 | |
JP5154744B2 (ja) | 半導体装置およびその製造方法 | |
JP2005026641A (ja) | 半導体装置およびその製造方法 | |
KR100843143B1 (ko) | 반도체 소자 및 이의 제조 방법 | |
JP2009295733A (ja) | 半導体装置及びその製造方法 | |
JP2005347334A (ja) | 半導体装置 | |
JP4573784B2 (ja) | 半導体装置の製造方法 | |
JP2005079513A (ja) | 半導体装置及びその製造方法 | |
JP4118202B2 (ja) | 半導体装置及びその製造方法 | |
KR20020061713A (ko) | 다중층의 스토리지 노드 콘택 플러그를 갖는 반도체메모리 소자 및 그 제조방법 | |
US11264322B2 (en) | Semiconductor structure and manufacturing method thereof | |
JP2008147300A (ja) | 半導体装置およびその製造方法 | |
JP2008053320A (ja) | 半導体装置およびその製造方法 | |
JP5165868B2 (ja) | 誘電膜上のパッシベーション膜と共に金属−絶縁体−金属キャパシタ(metal−insulator−metalmimcapacitors)を形成する方法 | |
JP2001298154A (ja) | 半導体装置およびその製造方法 | |
JP2007214284A (ja) | 半導体装置 | |
JP2004134613A (ja) | 半導体装置 | |
JP2009170637A (ja) | 半導体記憶装置の製造方法および半導体記憶装置 | |
JP2002141472A (ja) | 半導体装置及びその製造方法 | |
KR20000035524A (ko) | 반도체장치 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080613 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110630 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110705 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110905 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120605 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120730 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20121204 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20121206 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20151214 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5154744 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |