JP2006502595A - 半導体装置パッケージ - Google Patents
半導体装置パッケージ Download PDFInfo
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- JP2006502595A JP2006502595A JP2005501079A JP2005501079A JP2006502595A JP 2006502595 A JP2006502595 A JP 2006502595A JP 2005501079 A JP2005501079 A JP 2005501079A JP 2005501079 A JP2005501079 A JP 2005501079A JP 2006502595 A JP2006502595 A JP 2006502595A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 239000000758 substrate Substances 0.000 claims description 20
- 229910000679 solder Inorganic materials 0.000 claims description 14
- 239000004593 Epoxy Substances 0.000 claims description 13
- 239000000853 adhesive Substances 0.000 claims description 13
- 230000001070 adhesive effect Effects 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 10
- 239000012790 adhesive layer Substances 0.000 claims description 7
- 239000010410 layer Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 230000001360 synchronised effect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000002161 passivation Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002893 slag Substances 0.000 description 1
- 239000002470 thermal conductor Substances 0.000 description 1
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Abstract
Description
6 基板
7 半導体構成部品
8 ハウジング
10 半導体パッケージ
12 回路基板
16G1 外部コネクタ
16G2、16G3 出力コネクタ
16G4、16G5、16G6 ゲートコネクタ
16A、16B、16C 外部コネクタ
16V+ 外部コネクタ
16ground アースコネクタ
18T1、18T2、18T3、18T4、18T5、18T6 ソース導電性パッド
19 パシベーション(不動態)層
20T1、20T2、20T3、20T4、20T5、20T6 ドレイン導電性パッド
22 導電性経路
24T1、24T2、24T3、24T4、24T5、24T6 ゲート導電性パッド
28G4、28G5、28G6 ゲート相互接続パッド
28V+ 相互接続導電性パッド
28ground アース相互接続パッド
29G4、29G5、29G6 ゲート相互接続パッド
29V+ 相互接続パッド
29ground アース相互接続パッド
30 導電性経路
32 経路
33 導電性接着剤層
35 相互接続部
37 エポキシ(アンダーフィリング)
39 外部コネクタ
40 ヒートシンク
42 回路基板
44 回路基板
45 導電性ランド
47 構成部品
50 制御MOSFET
51 導電性パッド
52 同期MOSFET
Claims (27)
- 第1の回路基板であって、その主要面上に配置された少なくとも1つの導電性パッドを含む第1の回路基板と、
第2の回路基板であって、その主要面上の少なくとも1つの導電性パッドを含む第2の回路基板と、
半導体ダイであって、その第1の主要面上における第1の電気接点、及び前記半導体ダイの第2の主要面上における第2の電気接点、を含む半導体ダイと、を有し、
前記半導体ダイは、前記第1の回路基板上の前記少なくとも1つの導電性パッドと前記第2の回路基板上の前記少なくとも1つの導電性パッドとの間に配置され、
前記第1の電気接点は、前記第1の回路基板上の前記少なくとも1つの導電性パッドに電気的に接続され、かつ、前記第2の電気接点は前記第2の回路基板上の前記少なくとも1つの導電性パッドに電気的に接続されることを特徴とする半導体パッケージ。 - 前記半導体ダイの前記第1の電気接点と前記第2の電気接点とに接続された端子をさらに有し、前記端子が少なくとも1つの前記基板上に配置されている請求項1に記載の半導体パッケージ。
- 各々の前記回路基板が絶縁された金属基板である請求項1に記載の半導体パッケージ。
- 前記半導体ダイが制御端子を含むスイッチング出力半導体装置(switching power semiconductor)であり、前記制御端子が前記ダイの前記第1の主要面と前記ダイの前記第2の主要面とのうち1つの上に配置され、前記回路基板のうち1つの上の導電性パッドに電気的に接続され、前記回路基板のうち1つの上に配置された端子に電気的に接続されている請求項1に記載の半導体パッケージ。
- 前記半導体ダイがMOSFET及びIGBTのうちの1つである請求項1に記載の半導体パッケージ。
- 前記半導体ダイの前記第1の電気接点と前記第2の電気接点とが、導電性接着剤のそれぞれの層を介してそれぞれの導電性パッドに接続されている請求項1に記載の半導体パッケージ。
- 前記導電性接着剤がハンダ及び導電性エポキシのうちの1つである請求項6に記載の半導体パッケージ。
- 前記回路基板の間に配置されたエポキシのアンダーフィリングをさらに有する請求項1に記載の半導体パッケージ。
- 前記回路基板のうち1つの上に配置されたヒートシンクをさらに有する請求項1に記載の半導体パッケージ。
- 各々の前記回路基板の上に配置された少なくとも1つのヒートシンクをさらに有する請求項1に記載の半導体パッケージ。
- 第1の熱伝導性の基板であって、その主要面上に配置された複数の導電性パッドを含む第1の熱伝導性の基板と、
第2の熱伝導性の基板であって、その主要面上に配置された複数の導電性パッドを含む第2の熱伝導性の基板と、
複数の出力半導体装置であって、その第1の主要面上の第1の電源接点、及びその反対側にある第2の主要面上の第2の電源接点と制御接点、を各々が含む複数の出力半導体装置と、を有し
前記複数の出力半導体装置が、前記第1の熱伝導性の基板の前記第1の主要面と前記第2の熱伝導性の基板の前記第1の主要面との間に配置され、また、前記出力半導体装置の各々の前記接点が前記複数の導電性パッドの1つ1つにそれぞれ電気的に接続され、また、前記熱伝導性の基板上の前記導電性パッドが相互接続されて回路の一部を形成する半導体パッケージ。 - 前記導電性パッドを介して前記出力半導体装置に接続され、前記基板のうち少なくとも1つに配置された出力端子をさらに有する請求項11に記載の半導体パッケージ
- 前記熱伝導性の基板が絶縁された金属基板である請求項11に記載の半導体パッケージ。
- 前記出力半導体装置がパワーMOSFET及びIGBTのうちの1つである請求項11に記載の半導体パッケージ。
- 前記出力半導体装置が導電性接着剤層を介して前記導電性パッドに接続される請求項11に記載の半導体パッケージ。
- 前記導電性接着剤がハンダ及び導電性エポキシのうちの1つである請求項15に記載の半導体パッケージ。
- 前記出力半導体装置が半ブリッジ構造に接続される請求項11に記載の半導体パッケージ。
- 前記出力半導体装置が複数の半ブリッジ構造を形成するように接続される請求項11に記載の半導体パッケージ。
- 前記出力半導体装置の動作を制御するためのコントロール装置をさらに有する請求項11に記載の半導体パッケージ。
- 前記第1及び第2の熱伝導性の基板間の空間を満たすエポキシをさらに有する請求項11に記載の半導体パッケージ。
- 前記熱伝導性の基板のうちの1つに熱接触する少なくとも1つのヒートシンクをさらに有する請求項11に記載の半導体パッケージ。
- 前記熱伝導性のそれぞれに熱接触するヒートシンクをさらに有する請求項11に記載の半導体パッケージ。
- 第1の回路基板の第1の主要面上に配置される少なくとも1つの導電性パッドを備える前記第1の回路基板を供給する段階と、
前記導電性パッド上に導電性接着剤のペーストを印刷する段階と、
前記導電性接着剤上に半導体装置を搭載する段階と、
第2の回路基板の第1の主要面上に配置される少なくとも1つの導電性パッドを備える前記第2の回路基板を供給する段階と、
前記第2の回路基板上の前記導電性パッド上に導電性接着剤のペーストを印刷する段階と、
前記第2の回路基板上の前記導電性接着剤が前記半導体装置に接触するように、前記第2の回路基板を前記半導体装置の上に搭載する段階と、
熱を加えて前記導電性接着剤をリフローする段階と、
を有する半導体パッケージを製造する方法。 - 前記導電性接着剤がハンダ及び導電性エポキシのうちの1つである請求項23に記載の方法。
- エポキシによって前記回路基板の間の空間を満たす段階をさらに有する請求項23に記載の方法。
- 前記回路基板が絶縁された金属基板である請求項23に記載の方法。
- 各々の搭載段階がピック・アンド・プレイス法によって行われる請求項23に記載の方法。
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DE60235906D1 (de) * | 2001-10-11 | 2010-05-20 | Koninkl Philips Electronics Nv | Erfahren |
US20040080033A1 (en) * | 2002-04-09 | 2004-04-29 | Advanced Semiconductor Engineering Inc. | Flip chip assembly and method for producing the same |
US6946740B2 (en) * | 2002-07-15 | 2005-09-20 | International Rectifier Corporation | High power MCM package |
JP2004134762A (ja) * | 2002-09-19 | 2004-04-30 | Denso Corp | 半導体装置 |
JP2005101356A (ja) * | 2003-09-25 | 2005-04-14 | Toshiba Corp | 無線カード |
US7315081B2 (en) * | 2003-10-24 | 2008-01-01 | International Rectifier Corporation | Semiconductor device package utilizing proud interconnect material |
-
2003
- 2003-10-01 US US10/677,069 patent/US7045884B2/en not_active Expired - Lifetime
- 2003-10-02 AU AU2003277266A patent/AU2003277266A1/en not_active Abandoned
- 2003-10-02 WO PCT/US2003/031362 patent/WO2004034428A2/en active Application Filing
- 2003-10-02 DE DE10393437T patent/DE10393437T5/de not_active Ceased
- 2003-10-02 JP JP2005501079A patent/JP2006502595A/ja active Pending
-
2006
- 2006-02-06 US US11/348,392 patent/US7364949B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010097999A (ja) * | 2008-10-14 | 2010-04-30 | Fuji Electric Systems Co Ltd | 半導体装置及び半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
AU2003277266A1 (en) | 2004-05-04 |
US20060128067A1 (en) | 2006-06-15 |
US20040119148A1 (en) | 2004-06-24 |
US7364949B2 (en) | 2008-04-29 |
WO2004034428A3 (en) | 2004-11-11 |
US7045884B2 (en) | 2006-05-16 |
WO2004034428A2 (en) | 2004-04-22 |
DE10393437T5 (de) | 2005-10-27 |
AU2003277266A8 (en) | 2004-05-04 |
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