CN117043936A - 具有一体式散热器的电子封装 - Google Patents

具有一体式散热器的电子封装 Download PDF

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Publication number
CN117043936A
CN117043936A CN202280024024.3A CN202280024024A CN117043936A CN 117043936 A CN117043936 A CN 117043936A CN 202280024024 A CN202280024024 A CN 202280024024A CN 117043936 A CN117043936 A CN 117043936A
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China
Prior art keywords
gan
substrate
semiconductor die
electronic device
electronic package
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CN202280024024.3A
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English (en)
Inventor
查尔斯·拜利
乔治·朱
D·M·金策
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Navidas Semiconductor Co ltd
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Navidas Semiconductor Co ltd
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Publication of CN117043936A publication Critical patent/CN117043936A/zh
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    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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Abstract

一种电子器件，该电子器件包括衬底和形成在第一半导体管芯上、电耦接到该衬底的第一氮化镓(GaN)晶体管。第二GaN晶体管形成在第二半导体管芯上并且也电耦接到该衬底。一体式散热器热耦接到该第一氮化镓半导体管芯和该第二氮化镓半导体管芯，并且电耦接到该衬底。第一偏置电压经由该一体式散热器施加到该第一GaN晶体管，并且第二偏置电压经由该一体式散热器施加到该第二GaN晶体管。

Description

具有一体式散热器的电子封装
其他申请的交叉引用
本申请要求于2022年3月23日申请的名称为“ELECTRONIC PACKAGES WITHINTEGRAL HEAT SPREADERS”的美国专利申请序列号17/702,694的权益和于2021年3月24日申请的名称为“ELECTRONIC PACKAGES WITH TOP SIDE COOLING”的美国临时专利申请序列号63/165,529的权益，该申请以引用方式全文并入本文以用于所有目的。
背景技术
当前存在各种各样的电子器件，它们可彼此结合使用以形成一个或多个电路用于功率管理。为了提高此类电子器件的性能，通常将它们附接到一个或多个热沉。然而，对于诸如氮化镓的电子器件，其可能采用电偏置的半导体衬底，常规热沉技术和电子封装结构可能不能在电偏置半导体衬底的同时还提供有效的散热。
对于氮化镓半导体器件，需要新的电子封装架构和集成式热沉。
发明内容
本公开的一些实施方案涉及用于氮化镓基半导体器件的电子封装。一些实施方案涉及电子封装，其能够实现低热阻并且能够向氮化镓基半导体器件的半导体衬底施加电压偏置。另外的实施方案可以使得多个氮化镓半导体器件能够被共同封装，从而形成电源电路的一个或多个相。
在一些实施方案中，电子器件包括衬底，并且包括形成在第一半导体管芯上并且电耦接到衬底的第一氮化镓(GaN)基晶体管。第二GaN基晶体管形成在第二半导体管芯上并且电耦接到衬底。一体式散热器热耦接到第一半导体管芯和第二半导体管芯。在各种实施方案中，一体式散热器包括夹置在底部金属层与顶部金属层之间的含陶瓷层。在一些实施方案中，一体式散热器包括夹置在底部金属层与顶部金属层之间的陶瓷层，底部铜层包括电耦接到第一半导体管芯的第一部分和电耦接到第二半导体管芯的第二部分，并且其中第一部分与第二部分电隔离。
在一些实施方案中，衬底电耦接到第一部分并且向第一半导体管芯供应第一偏置电压，并且其中衬底电耦接到第二部分并且向第二半导体管芯供应第二偏置电压。在各种实施方案中，第一半导体管芯定位在附接到衬底的第一中间电子封装内，并且其中第二半导体管芯定位在附接到衬底的第二中间电子封装内。在一些实施方案中，第一半导体管芯包括与背侧相对的有源器件侧，并且其中有源器件侧面向衬底，并且背侧面向一体式散热器。
在一些实施方案中，背侧附接到定位在第一中间电子封装的顶表面处的引线框架桨状件。在一些实施方案中，第一中间电子封装包括控制器件，该控制器件包括耦接到第一GaN基晶体管的栅极驱动器电路。在一些实施方案中，控制器件是形成在硅基半导体管芯上的电路。在各种实施方案中，电子器件还包括隔离器器件，该隔离器器件耦接到衬底并且布置成隔离控制信号，该控制信号控制第一GaN基晶体管和第二GaN基晶体管的操作。
在一些实施方案中，第一GaN基晶体管是高侧晶体管，第二GaN基晶体管是低侧晶体管，并且其中第一GaN基晶体管与第二GaN基晶体管串联耦接以形成单相半桥电路。在各种实施方案中，电子器件还包括形成在第三半导体管芯上并且电耦接到衬底的第三GaN基晶体管和形成在第四半导体管芯上并且电耦接到衬底的第四GaN基晶体管。在一些实施方案中，第一GaN基晶体管和第二GaN基晶体管形成电源电路的第一相，并且其中第三GaN基晶体管和第四GaN基晶体管形成电源电路的第二相。
在一些实施方案中，衬底、第一半导体管芯、第二半导体管芯和一体式散热器定位在形成在电子封装中的腔内，并且用填充材料密封在腔内，并且其中电子封装包括布置成耦接到电路板的一个或多个引脚。在各种实施方案中，电子器件还包括模制化合物，该模制化合物从衬底延伸并且封装第一半导体管芯、第二半导体管芯和一体式散热器的至少一部分。在一些实施方案中，一体式散热器的一部分形成电子器件的顶表面的一部分，并且布置成耦接到热沉。在各种实施方案中，衬底是多层印刷电路板。
在一些实施方案中，一种形成电子封装的方法包括：将一个或多个GaN基半导体管芯耦接到衬底，以及将一体式热沉附接到该一个或多个GaN基半导体管芯，以及将一体式热沉电耦接到衬底。封装该一个或多个GaN基半导体管芯和一体式热沉的至少一部分。在各种实施方案中，该方法还包括经由一体式热沉将电偏置施加到该一个或多个GaN基半导体管芯。在一些实施方案中，该方法还包括将该一个或多个GaN基半导体管芯集成到一个或多个相应的中间电子封装中。
通过本发明实现了优于常规技术的许多益处。例如，本发明的实施方案提供了在单个电子封装中共同封装多个氮化镓基半导体器件的能力，该电子封装还可以向每个半导体器件的衬底施加单独的电压偏置。在封装内使用一体式散热器可以使得功率密度降低，热量因此可以通过热界面材料有效地传递到热沉或冷却板。半导体管芯在单个电子封装内的紧密接近使得能够提高开关速度和电路稳定性，同时一体式散热器减轻了由于多个氮化镓器件的紧密接近而导致的增加的功率密度的负面热影响。总而言之，可以在减小的空间量内形成较高性能的电路，同时保持在安全操作温度内有效地操作器件的能力。
本发明的这些和其他实施方案及其许多优点和特征将结合下文和附图更详细地描述。为了更好地理解本公开的性质和优点，应参考以下描述和附图。然而，应理解，这些附图中的每一者仅出于说明的目的而提供，并不旨在作为对本公开范围的限制的定义。另外，作为一般规则，除非明显与描述相反，否则在不同附图中的元件使用相同的附图标记的情况下，这些元件通常在功能或目的上相同或至少类似。
附图说明
图1根据本公开的实施方案的电子封装的简化局部截面图，该电子封装包括一对氮化镓(GaN)半导体管芯和顶侧冷却；
图2示出了图1中所示的电子封装的简化底部平面图；
图3示出了图1和图2中所示的电子封装的简化顶视图；
图4示出了根据本公开的实施方案的包括两个一体式散热器的电子封装的简化局部截面图；
图5示出了图4中所示的电子封装的简化底视图；
图6示出了图4中所示的电子封装的简化底视图；
图7示出了根据本公开实施方案的在中间电子封装中包括GaN管芯的电子封装的简化局部截面图；
图8示出了图7中所示的一体式热沉的底部铜层的平面图；
图9示出了根据本公开的实施方案的包括电源电路的两个相的电子封装的简化局部截面图；
图10示出了根据本公开的实施方案的可以与底侧冷却一起使用的电子封装的简化局部截面图；
图11示出了根据本公开的实施方案的通孔电子封装的简化局部截面图；
图12示出了根据本公开的实施方案的单相半桥电路的简化电气示意图；并且
图13示出了根据本公开的实施方案的与形成电子封装的方法1300相关联的步骤。
具体实施方式
本文所公开的技术整体涉及包括一个或多个氮化镓功率晶体管的电子封装。更具体地，本文所公开的技术涉及使得电子封装能够有效冷却的电子封装，该电子封装包括具有电偏置的衬底的氮化镓功率晶体管。本文中描述各种发明性实施方案，包括方法、过程、系统、器件等。
现在将参考附图描述几个说明性实施方案，附图形成说明书的一部分。随后的描述仅提供实施方案，并且不旨在限制本公开的范围、适用性或构型。相反，随后对实施方案的描述将向本领域技术人员提供用于实现一个或多个实施方案的使能描述。应理解，在不脱离本公开的实质和范围的情况下，可以对元件的功能和布置进行各种改变。在以下描述中，出于解释的目的，阐述了具体细节以便提供对某些发明性实施方案的透彻理解。然而，将显而易见的是，可以在没有这些具体细节的情况下实践各种实施方案。附图和说明书不旨在是限制性的。本文使用的词语“示例”或“示例性”是指“用作示例、实例或说明”。本文描述为“示例性”或“示例”的任何实施方案或设计不一定被解释为比其他实施方案或设计优选或有利。
图1示出了根据本公开的实施方案的电子封装100的简化局部截面图，该电子封装包括一对氮化镓(GaN)半导体管芯和顶侧冷却。如图1中所示，电子封装100分别包括第一GaN管芯105和第二GaN管芯110，其布置成形成半桥功率转换器的一部分，然而在其他实施方案中，更多数量或更少数量的GaN管芯可以被使用并且可以被用于不同的电路功能。在该特定示例性实施方案中，第一GaN管芯105是同步降压转换器电路的高侧晶体管，并且第二GaN管芯110是同步降压转换器电路的低侧晶体管。第一GaN管芯105和第二GaN管芯110分别以倒装芯片构型附接到衬底115，即有源器件和每个管芯的互连侧面向衬底。电互连120分别形成在第一GaN管芯105和第二GaN管芯110与衬底115之间，在一个实施方案中，电互连是焊接到衬底的铜柱，然而在其他实施方案中，互连可以包括焊球、焊盘或者可以是任何其他合适的互连结构。倒装芯片构型使第一GaN管芯105和第二GaN管芯110中的每一者的背侧125分别暴露，这将在下面更详细地讨论。
一体式热沉130包括分别夹置在顶部铜层140a与底部铜层140b之间的非导电陶瓷层135(例如，Al203、AlN、BeO等)。在一些实施方案中，一体式热沉130可以是直接接合铜(DBC)衬底或绝缘金属衬底(IMS)组件，然而也可以使用其他合适的构型。DBC和IMS衬底通常都采用夹置在顶部金属层与底部金属层之间的含陶瓷层。如本文所定义，含陶瓷层包括完全或部分由陶瓷形成的层，包括通常用于IMS衬底的聚合物陶瓷复合物。在一些实施方案中，金属是铜、铝、其组合或其他合适的材料。在一些实施方案中，底部铜层140b可以分成两个电隔离区，其中使用导电环氧树脂、焊料、银、完全和/或部分烧结的银或其他合适的导电材料，第一隔离区145a附接到第一GaN管芯105的暴露的背侧125，并且第二隔离区145b附接到第二GaN管芯110的暴露的背侧125。第一隔离区145a和第二隔离区145b中的每一者分别可以经由一个或多个延伸铜柱150(例如，100微米或其他合适的高度)电耦接到衬底115，这些延伸铜柱可以用焊料或其他合适的导电材料(例如，焊料或导电粘合剂)来附接。在另外的实施方案中，可以使用其他合适的互连结构，诸如但不限于引线、导线、夹片、翼部或部件(例如，在底层145a与衬底115之间垂直取向的电阻器、电容器等)。第一隔离区145a和第二隔离区145b可以经由衬底115独立地电偏置，以分别向第一GaN管芯105和第二GaN管芯110中的每一者的块状衬底施加适当的电压偏置。
在一些实施方案中，顶部铜层140a是连续的，这使得能够有效地横向扩散分别由第一GaN管芯105和第二GaN管芯110产生的热能，并且因此在电子封装100的顶表面155处实现降低的热功率密度。顶部铜层140a可以基本上暴露在电子封装100的顶表面155处，因此其可以经由热界面材料160直接热耦接到冷却板165、热沉或其他设备，以有效地将热能分别从第一GaN管芯105和第二GaN管芯110中的每一者通过底部铜层140b、通过陶瓷135、通过热界面材料160传递，并且传递到冷却板165。一体式热沉130内的陶瓷135分别在顶部铜层140a与第一GaN管芯145a和第二GaN管芯145b的块状衬底之间提供电隔离，并且还在每个GaN管芯的块状衬底中的每一者之间提供电隔离。在一些实施方案中，陶瓷135约250微米厚，并且顶部铜层140a和底部铜层140b各自约300微米厚，然而也可以使用其他合适的厚度。
在一些实施方案中，一个或多个控制和/或隔离IC 170可以附接到衬底115并且构造成提供分别形成在第一GaN管芯105和第二GaN管芯110中的控制信号和/或驱动晶体管。控制和/或隔离IC 170可以使用引线接合、倒装芯片技术或其他合适的互连来电耦接到衬底115。控制和/或隔离IC 170可以提供隔离、短路保护、开关波形控制、过冲保护、故障报告、过温保护、ESD保护和/或其他特征和功能，如下面更详细描述的。
如本文所述，在该特定实施方案中，第一GaN管芯105和第二GaN管芯110形成半桥降压转换器电路的一部分，其中衬底115包括VIN端子151、开关节点端子153和接地端子157。第一GaN管芯105和第二GaN管芯110的紧密接近以及形成连接第一GaN管芯105和第二GaN管芯110的开关节点端子153(在该实施方案中形成在衬底115内)的铜的大横截面积可以使得封装100具有超低栅极回路电感和超低换向回路电感，从而实现提高的开关速度和改善的电路稳定性。
一个或多个集成式无源电子部件175(例如，电阻器、电容器、电感器)可以与其他分立的有源部件(例如，二极管、晶闸管等)一起附接到衬底115。在一些实施方案中，一个或多个无源元件175可以与控制和/或隔离IC 170中的开关功能组合以提供自举电路。在一些实施方案中，衬底115是多层有机基衬底，诸如但不限于具有通过多个通孔互连的多个铜层的四层BT衬底，然而在另外的实施方案中，可以使用其他合适的材料和数量的电气布线层。电子封装100可以用与顶部铜层140a基本上共面或稍稍嵌进其中的模制化合物180或其他合适的材料来封装，使得顶部铜层可以与热界面材料160和冷却板165紧密接触。
图2示出了图1中所示的封装100的简化底部平面图。如图2中所示，衬底115包括具有三个大功率连接的焊盘栅格阵列，这三个大功率连接包括耦接到第一GaN管芯105(例如，用作半桥电路中的高侧管芯)的Vin焊盘205(Vin端子151)、耦接到分别形成在第一GaN管芯105与第二GaN管芯110之间的互连的SW(开关节点)焊盘210(开关节点端子153)，以及耦接到第二GaN管芯110(例如，用作半桥电路中的低侧管芯)的PGND焊盘215(接地端子157)。衬底115还包括多个I/O连接220，其可以将信号(诸如栅极控制信号、故障信号、逻辑功率信号等)耦接到封装100中和从其中耦接出来。图2是可以形成在封装100上的电连接的一个示例，并且另外的实施方案可以具有其他合适的连接布置、尺寸和构型。
图3示出了图1和图2中所示的封装100的简化顶视图。如图3中所示，一体式热沉130的顶部铜层140a暴露并且被模制化合物180包围。在一些实施方案中，顶部铜层140a与模制化合物共面，然而在其他实施方案中，模制化合物稍稍嵌进其中，使得铜略微延伸出封装的顶部以便于形成与热界面材料的可靠界面。在一些实施方案中，顶表面165可以被阳极化、电镀或涂覆有涂料、热界面材料或其他合适的材料。
图4示出了具有与图1至图3(其中，类似的附图标记指示类似的特征)中所示的电子封装100类似的特征的电子封装400的简化局部截面图，然而，电子封装400包括两个ePad，以代替电子封装100中使用的一体式热沉130。在一些实施方案中，ePad 405、410可以主要由电镀有一种或多种金属的铜制成，然而其他实施方案可以包括铜钨合金、铜铍合金、银、金、铝、陶瓷、金刚石、碳化硅或其他合适的材料。如图4中所示，封装400分别包括高侧GaN管芯105和低侧GaN管芯110，其各自分别耦接到各自约200微米厚的单独的铜ePad405、410。ePad 405、410彼此电隔离，并且电耦接到相应的GaN管芯块状衬底105、110并且电耦接到衬底115。衬底115可以向每个管芯105、110的块状衬底施加单独的偏置电压。在一些实施方案中，在ePad 405、410与冷却板165之间使用电绝缘的热界面材料460，以确保电绝缘。在一些实施方案中，封装400可以具有与图1至图3中所示的电子封装100相比减小的热阻抗，这是因为移除了可以具有比铜的热导率更低的热导率的陶瓷中间层。然而在其他实施方案中，封装100可以具有减小的热阻抗，只要一体式热沉大到足以减小功率密度从而有效地横穿热界面材料。
图5示出了图4中所示的电子封装400的简化底视图，并且示出了类似于电子封装100的互连布局的焊盘栅格阵列。
图6示出了图4和图5中所示的电子封装400的简化顶视图。如图6中所示，存在暴露在电子封装400的顶表面415处的两个单独的电偏置的ePad 405、410。
图7示出了具有与图1至图3(其中，类似的附图标记指示类似的特征)中所示的电子封装100类似的特征的电子封装700的简化局部截面图，然而，电子封装700在中间封装705、710中包括GaN和硅管芯。如图7中所示，电子封装700包括高侧GaN管芯715和低侧GaN管芯720，其各自分别在单独的中间电子封装705、710中。在该特定实施方案中，GaN管芯715、720具有背表面725，其各自使用导电环氧树脂、焊料、银、完全和/或部分烧结的银或其他合适的导电材料附接到引线框架部分727、729(也称为桨状件)。使用导电环氧树脂、焊料、银、完全和/或部分烧结的银或其他合适的导电材料将引线框架部分727、729附接到一体式热沉130的隔离区145a、145b。
如图7中进一步所示，在该实施方案中，中间电子封装705、710各自分别包括单独的控制管芯730、735，其可以是硅、GaN或分别耦接到GaN管芯715、720的其他半导体器件。GaN管芯715、720和控制管芯730、735可以经由引线接合、倒装芯片或其他合适的互连方法电连接到中间电子封装705、710，并且用模制材料740包覆模制。在一些实施方案中，GaN管芯715、720的块状衬底可以经由中间封装连接和/或经由类似于延伸铜柱150(见图1)的外部连接被电偏置。在该实施方案中，中间电子封装705、710是双扁平无引线(DFN)封装，然而，中间封装可以是任何合适的引线接合、倒装芯片、芯片级或其他封装，并且可以包括一个或多个GaN和/或硅管芯附接到其上的金属焊盘。
在一些实施方案中，中间电子封装705、710的使用可以使得电子封装700的产量提高，这是因为能够在集成之前测试中间电子封装705、710。此外，中间电子封装705、710的使用可以实现电子封装700的简化组装，这是由于中间电子封装的特征尺寸增加，并且与处理裸管芯时所需的那些程序相比，清洁和处置程序减少。
在一些实施方案中，可以选择模制化合物180来充当填充中间电子封装705、710与电子封装700之间的间隙的底部填充材料。在各种实施方案中，模制化合物180、740和一体式热沉130的热膨胀系数(CTE)可以被选择为大致相同，以使内应力最小化。
图8示出了一体式热沉130的底部铜层140b的平面图。如图8中所示，在一些实施方案中，第一隔离区145a与第二隔离区145b之间的界面区805可以不规则、阶梯状、锯齿形或其他合适的几何形状布置以增加铜对陶瓷的粘附。
图9示出了具有与图7(其中，类似的附图标记指示类似的特征)中所示的电子封装700类似的特征的电子封装900的简化局部截面图，然而，与具有单相架构的电子封装700相比，电子封装900包括两相架构。如图9中所示，电子封装900包括第一相半桥电路905和第二相半桥电路910。如本文更详细解释的，每个相可以包括单独的高侧和低侧GaN基晶体管。其他实施方案可以在单个电子封装内包括三个相、四个相或更多数量的相。
如图9中进一步所示，电子封装900包括定位在衬底920内的通孔引脚915。通孔引脚915可以被构造成焊接到接收板的通孔中、连接到插座或者压力配合到接收板的通孔中。本文所公开的电子封装中的任何电子封装可以使用通孔构型，并且类似地，电子封装900也可以被构造成如图1至图2中所示的焊盘栅格阵列。
图10示出了具有与图7(其中，类似的附图标记指示类似的特征)中所示的电子封装700类似的特征的电子封装1000的简化局部截面图，然而，电子封装1000是具有倒置的中间电子封装的底部冷却式架构。如图10中所示，电子封装1000包括两个中间电子封装1005、1010，其各自包括分别附接到每个相应的中间电子封装的引线框架部分1025、1030的GaN晶体管1015、1020。在一些实施方案中，每个中间电子封装1005、1010可以包括一个或多个控制器件，如本文所述。然而在该实施方案中，控制器件1035被示出为在中间电子封装外部并且附接到衬底1040。在一些实施方案中，衬底1040可以是通常被称为绝缘金属衬底(IMS)的衬底，其具有相对高的热导率，使得热能能够从GaN晶体管1015、1020经由热界面材料1045耦接到冷却板1040。
图11示出了具有与图9(其中，类似的附图标记指示类似的特征)中所示的电子封装900类似的特征的电子封装1100的简化局部截面图，然而，电子封装1100在通孔模块1100内包括两相架构。如图11中所示，模块1100包括塑料主体1105，其包括可以是焊接构型或压力配合构型的多个通孔引脚1110。塑料主体1105可以包括接收耦接到引脚1110的衬底1120的腔1115。衬底1120可以包括全部耦接到整体一体式热沉1130的四个GaN基晶体管1125a至1125d。GaN基晶体管1125a至1125d可以放置在中间封装内，如图所示，例如在图7中，或者可以是裸管芯，例如在图1和图4中。一体式热沉1130可以具有本文所示的构造中的任何构造或任何其他合适的构造。腔1115可以用填充材料1135填充，该填充材料可以是任何类型的凝胶、填料、模制化合物、底部填充或任何其他合适的材料。一个或多个控制管芯可以附接到衬底1120或者定位在如本文所公开的中间电子封装内。受益于本公开的本领域普通技术人员可以理解，在模块1100内可以形成更多数量或更少数量的相。
图12示出了可以在本文所示的电子封装中的任何电子封装中采用的单相半桥电路1200的简化电气示意图。第一GaN管芯1205是高侧GaN晶体管并且第二GaN管芯1210是低侧GaN晶体管，二者以半桥构型耦接在一起，从而在这两个管芯之间形成开关节点(Vsw)1215。第一GaN管芯1205可以耦接到第一控制管芯1220，并且第二GaN管芯1210可以耦接到第二控制管芯1225。控制管芯1220、1225可以各自包括以下电路中的一者或多者：栅极驱动器、欠压锁定、dV/dt检测和保护、功率调节、过温保护、电平移位、自举电源、隔离、过流保护、修整功能和/或保护电路。每个控制管芯1220、1225可以布置成经由任选的隔离器器件1235从控制器1230接收控制信号，该隔离器器件可以是例如光耦接、数字耦接、磁耦接或其他合适类型的隔离器件。在其他实施方案中，可以不使用隔离器器件1235。在一些实施方案中，隔离器1235、控制管芯1220、1225以及第一GaN管芯1205和第二GaN管芯1210分别可以集成在单个电子封装1240内，然而其他实施方案可以将这些器件中的一者或多者集成在电子封装内。
图13示出了根据本公开的实施方案的与形成电子封装的方法1300相关联的步骤。步骤1305包括形成衬底。在一些实施方案中，衬底可以是多层印刷电路板，然而在其他实施方案中，其可以仅具有一层和/或可以由其他材料制成，诸如陶瓷、金属、电介质等。
步骤1310包括形成一个或多个GaN管芯。在一些实施方案中，每个GaN管芯可以包括一个或多个晶体管，然而在其他实施方案中，每个GaN管芯可以包括一个或多个逻辑、驱动器和/或控制电路。在一些实施方案中，每个GaN管芯可以具有包括该一个或多个晶体管的有源表面，该有源表面定位成与作为块状半导体衬底的一部分的背表面相对。
步骤1315包括将该一个或多个GaN管芯附接到衬底。在一些实施方案中，该一个或多个GaN管芯以倒装芯片构型附接到衬底，其中管芯的有源表面面向衬底，然而在其他实施方案中，管芯可以附接成背侧附接到衬底，并且有源表面经由引线接合电耦接到衬底。
步骤1320包括形成一体式热沉。在一些实施方案中，一体式热沉包括夹置在两个铜层之间的陶瓷层，并且可以被称为直接接合铜(DBC)或绝缘金属衬底(IMS)。在其他实施方案中，一体式热沉可以包括一层或多层相对高热导率的材料，诸如铜、铝、陶瓷、金刚石等。
步骤1325包括将一体式热沉附接到该一个或多个GaN管芯以及将一体式热沉电耦接到衬底。在一些实施方案中，一体式热沉可以用焊料、导电粘合剂、烧结的银、扩散接合或其他合适的技术电耦接和热耦接到该一个或多个GaN管芯。在各种实施方案中，一体式热沉可以电耦接到衬底，使得衬底可以经由一体式热沉将电偏置电压施加到块状半导体衬底。在一些实施方案中，柱、引线或其他互连可以用于从衬底向每个GaN管芯施加电偏置电压。
步骤1330包括封装该一个或多个GaN管芯和一体式热沉的至少一部分。在一些实施方案中，使用模制化合物，然而在其他实施方案中，可以使用任何类型的凝胶、底部填充或其他合适的材料。
应理解，过程1300是说明性的，并且各种变形和修改是可能的。顺序描述的步骤可以并行执行，步骤的顺序可以改变，并且步骤可以被修改、组合、添加或省略。
尽管前述实施方案中讨论的GaN管芯被描述为形成半桥电路，但是受益于本公开的本领域普通技术人员将理解，单个GaN器件以及任何数量的GaN器件可以用于不同的电学目的，并且可以根据所公开的实施方案中的一个或多个实施方案来使用。例如，在一个实施方案中，一系列GaN器件可以用于多相电机驱动器电路，而在另一个实施方案中，多个GaN器件可以用于高速、高功率多路复用开关矩阵。这些实施方案中的任何实施方案可以被整合到本文所公开的封装构型中的一个或多个构型中。
为了简单起见，各种外围部件，诸如电容器、电阻器、二极管等，未在附图和电路图中示出。
在一些实施方案中，GaN基管芯可以包括形成在硅基衬底上的一个或多个氮化镓和/或其他层，其中有源器件形成在该一个或多个氮化镓层中，并且硅充当管芯的块状衬底。GaN晶体管可以包括其中可形成导电沟道的二维电子气区。
在前述说明书中，已参考许多具体细节描述了本公开的实施方案，这些细节可以随具体实施而变化。因此，应将本说明书和附图视为例示性的而非限制性的。本公开的范围的唯一且排他的指示以及申请人预期的本公开的范围是从本申请发布的一组权利要求的字面和等效范围，这些权利要求以具体形式发出，包括任何后续修正。可在不脱离本公开的实施方案的实质和范围的情况下以任何合适的方式组合特定实施方案的具体细节。
另外，空间相关的术语诸如“底部”或“顶部”等可以用于描述元件和/或特征与另一元件和/或特征的关系，例如，如图中所示。应理解，这些空间相关的术语旨在涵盖除了图中所描绘的取向之外的器件在使用和/或操作中的不同取向。例如，如果图中的器件被翻转，则被描述为“底部”表面的元件然后可以被取向为在其他元件或特征“上方”。器件能够以其他方式取向(例如，旋转90度或以其他取向)，并相应地解释本文使用的空间相关描述符。
如本文所用，术语“和”、“或”、“和/或”可以包括多种含义，这些含义也预期至少部分地取决于使用这些术语的上下文。通常，“或”如果用于关联列表，诸如A、B或C，则旨在表示A、B和C(此处用于包含性含义)，以及A、B或C(此处用于排他性含义)。此外，如本文所用，术语“一个或多个”可以用于描述单数的任何特征、结构或特性，或者可以用于描述特征、结构或特性的一些组合。然而，应注意，这仅为例示性示例并且要求保护的主题不限于该示例。此外，术语“至少一个”如果用于关联列表，诸如A、B或C，则可以被解释为表示A、B和/或C的任何组合，诸如A、B、C、AB、AC、BC、AA、AAB、ABC、AABBCCC等。
本说明书通篇对“一个示例”、“示例”、“某些示例”或“示例性具体实施”的引用意味着结合该特征和/或示例描述的特定特征、结构或特征可以包括在要求保护的主题的至少一个特征和/或示例中。因此，在本说明书通篇各处出现的短语“在一个示例中”、“示例”、“在某些示例中”、“在某些具体实施中”或其他类似短语不一定都指代相同的特征、示例和/或限制。此外，特定特征、结构或特性可以在一个或多个示例和/或特征中组合。
在一些具体实施中，操作或处理可以涉及物理量的物理操纵。通常，尽管不是必需的，这些量可以采用能够被存储、传送、组合、比较或以其他方式操纵的电信号或磁信号的形式。主要出于常见用法的原因，已证明有时将此类信号称为位、数据、值、元素、符号、字符、项、数字、标号等是方便的。然而，应理解，所有这些或类似术语都将与适当的物理量相关联，并且仅仅是方便的标记。除非另有明确说明，否则如从本文的讨论显而易见，应理解，在说明书通篇中，利用术语诸如“处理”、“计算”、“确定”等的讨论是指特定设备的动作或过程，诸如专用计算机、专用计算设备或类似的专用电子计算设备。因此，在本说明书的上下文中，专用计算机或类似专用电子计算设备能够操纵或变换信号，这些信号通常表示为专用计算机或类似专用电子计算设备的存储器、寄存器或其他信息存储设备、传输设备或显示设备内的物理电子量或磁性量。
在前述详细描述中，已阐述了许多具体细节以提供对所要求保护的主题的透彻理解。然而，本领域技术人员应理解，可以在没有这些具体细节的情况下实践所要求保护的主题。在其他情况下，没有详细描述本领域普通技术人员已知的方法和设备，以免混淆所要求保护的主题。因此，旨在所要求保护的主题不限于所公开的特定示例，而是此类所要求保护的主题还可以包括落入所附权利要求及其等同物的范围内的所有方面。

Claims (20)

1.一种电子器件，包括：
衬底；
第一氮化镓(GaN)基晶体管，所述第一GaN基晶体管形成在第一半导体管芯上并且电耦接到所述衬底；
第二GaN基晶体管，所述第二GaN基晶体管形成在第二半导体管芯上并且电耦接到所述衬底；和
一体式散热器，所述一体式散热器热耦接到所述第一半导体管芯和所述第二半导体管芯。
2.根据权利要求1所述的电子器件，其中所述一体式散热器包括夹置在底部金属层与顶部金属层之间的含陶瓷层。
3.根据权利要求1所述的电子器件，其中所述一体式散热器包括夹置在底部金属层与顶部金属层之间的陶瓷层，底部铜层包括电耦接到所述第一半导体管芯的第一部分和电耦接到所述第二半导体管芯的第二部分，并且其中所述第一部分与所述第二部分电隔离。
4.根据权利要求3所述的电子器件，其中所述衬底电耦接到所述第一部分并向所述第一半导体管芯供应第一偏置电压，并且其中所述衬底电耦接到所述第二部分并且向所述第二半导体管芯供应第二偏置电压。
5.根据权利要求1所述的电子器件，其中所述第一半导体管芯定位在附接到所述衬底的第一中间电子封装内，并且其中所述第二半导体管芯定位在附接到所述衬底的第二中间电子封装内。
6.根据权利要求5所述的电子器件，其中所述第一半导体管芯包括与背侧相对的有源器件侧，并且其中所述有源器件侧面向所述衬底，并且所述背侧面向所述一体式散热器。
7.根据权利要求6所述的电子器件，其中所述背侧附接到定位在所述第一中间电子封装的顶表面处的引线框架桨状件。
8.根据权利要求5所述的电子器件，其中所述第一中间电子封装包括控制器件，所述控制器件包括耦接到所述第一GaN基晶体管的栅极驱动器电路。
9.根据权利要求8所述的电子器件，其中所述控制器件是形成在硅基半导体管芯上的电路。
10.根据权利要求1所述的电子器件，还包括隔离器器件，所述隔离器器件耦接到所述衬底并且布置成隔离控制信号，所述控制信号控制所述第一GaN基晶体管和所述第二GaN基晶体管的操作。
11.根据权利要求1所述的电子器件，其中所述第一GaN基晶体管是高侧晶体管，并且所述第二GaN基晶体管是低侧晶体管，并且其中所述第一GaN基晶体管与所述第二GaN基晶体管串联耦接以形成单相半桥电路。
12.根据权利要求1所述的电子器件，还包括第三GaN基晶体管，所述第三GaN基晶体管形成在第三半导体管芯上并且电耦接到所述衬底；和
第四GaN基晶体管，所述第四GaN基晶体管形成在第四半导体管芯上并且电耦接到所述衬底。
13.根据权利要求12所述的电子器件，其中所述第一GaN基晶体管和所述第二GaN基晶体管形成电源电路的第一相，并且其中所述第三GaN基晶体管和所述第四GaN基晶体管形成电源电路的第二相。
14.根据权利要求1所述的电子器件，其中所述衬底、所述第一半导体管芯、所述第二半导体管芯和所述一体式散热器定位在形成在电子封装中的腔内，并且用填充材料密封在所述腔内，并且其中所述电子封装包括布置成耦接到电路板的一个或多个引脚。
15.根据权利要求1所述的电子器件，还包括模制化合物，所述模制化合物从所述衬底延伸并且封装所述第一半导体管芯、所述第二半导体管芯和所述一体式散热器的至少一部分。
16.根据权利要求15所述的电子器件，其中所述一体式散热器的一部分形成所述电子器件的顶表面的一部分，并且布置成耦接到热沉。
17.根据权利要求1所述的电子器件，其中所述衬底是多层印刷电路板。
18.一种形成电子封装的方法，所述方法包括：
将一个或多个GaN基半导体管芯耦接到衬底；
将一体式热沉附接到所述一个或多个GaN基半导体管芯，并且将所述一体式热沉电耦接到所述衬底；以及
封装所述一个或多个GaN基半导体管芯和所述一体式热沉的至少一部分。
19.根据权利要求18所述的方法，还包括经由所述一体式热沉将电偏置施加到所述一个或多个GaN基半导体管芯。
20.根据权利要求18所述的方法，还包括将所述一个或多个GaN基半导体管芯集成到一个或多个相应的中间电子封装中。
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